covert ALU FU to CommonInputStage

diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index 6e6b1c8540f3a8c7a0d141eaae0342f1de4d0936..0534de4cc379ac4b14edb500010b3e6a1a097cab 100644 (file)
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -26,14 +26,12 @@ class Driver(Elaboratable):
         comb = m.d.comb
 
         rec = CompALUOpSubset()
-        recwidth = 0
         # Setup random inputs for dut.op
         for p in rec.ports():
             width = p.width
-            recwidth += width
             comb += p.eq(AnyConst(width))
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
+        pspec = ALUPipeSpec(id_wid=2)
         m.submodules.dut = dut = ALUMainStage(pspec)
 
         # convenience variables

diff --git a/src/soc/fu/alu/input_stage.py b/src/soc/fu/alu/input_stage.py
index 426f1248a5fbea6db594df71c2d9464f836c714e..75ed7b2d718fb458c77f6c8b41a941fc7d60c0f3 100644 (file)
--- a/src/soc/fu/alu/input_stage.py
+++ b/src/soc/fu/alu/input_stage.py
@@ -2,15 +2,11 @@
 # the acutal ALU. Things like handling inverting the input, xer_ca
 # generation for subtraction, and handling of immediates should happen
 # here
-from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
-                    unsigned)
-from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import InternalOp
+from soc.fu.common_input_stage import CommonInputStage
 from soc.fu.alu.pipe_data import ALUInputData
-from soc.decoder.power_enums import CryIn
 
 
-class ALUInputStage(PipeModBase):
+class ALUInputStage(CommonInputStage):
     def __init__(self, pspec):
         super().__init__(pspec, "input")
 
@@ -21,37 +17,11 @@ class ALUInputStage(PipeModBase):
         return ALUInputData(self.pspec)
 
     def elaborate(self, platform):
-        m = Module()
+        m = super().elaborate(platform) # covers A-invert, carry, and SO.
         comb = m.d.comb
         ctx = self.i.ctx
 
-        ##### operand A #####
-
-        # operand a to be as-is or inverted
-        a = Signal.like(self.i.a)
-
-        with m.If(ctx.op.invert_a):
-            comb += a.eq(~self.i.a)
-        with m.Else():
-            comb += a.eq(self.i.a)
-
-        comb += self.o.a.eq(a)
+        # operand b
         comb += self.o.b.eq(self.i.b)
 
-        ##### carry-in #####
-
-        # either copy incoming carry or set to 1/0 as defined by op
-        with m.Switch(ctx.op.input_carry):
-            with m.Case(CryIn.ZERO):
-                comb += self.o.xer_ca.eq(0b00)
-            with m.Case(CryIn.ONE):
-                comb += self.o.xer_ca.eq(0b11) # set both CA and CA32
-            with m.Case(CryIn.CA):
-                comb += self.o.xer_ca.eq(self.i.xer_ca)
-
-        ##### sticky overflow and context (both pass-through) #####
-
-        comb += self.o.xer_so.eq(self.i.xer_so)
-        comb += self.o.ctx.eq(ctx)
-
         return m