rename sys_clk to sys_pllclk - conflict with litex

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index 737039d3a9fab6f9fcfd5d8ce0e6d48dce05ca37..d0393eabf4bee6d0e4adef28cf92fb49c5d1918b 100644 (file)
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -206,7 +206,7 @@ def pinparse(psp, pinspec):
         # SYS
         elif name.startswith('sys'):
             domain = 'SYS'
-            if name == 'sys_clk':
+            if name == 'sys_pllclk':
                 pad = ["p_"+name, name, name]
             elif name == 'sys_rst':
                 #name = 'p_sys_rst_1'

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index d30bc03d1f9ad204a0eb200f677409db4775da65..d93f82a9769d3b46241621b878ae9c4f6c766445 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -285,7 +285,7 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-',                       # incoming clock (to PLL)
+    return (['PLLCLK-',                       # incoming clock (to PLL)
              'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
              'PLLTESTOUT+',                # divided-output (for testing)
              'PLLVCOUT+',                  # PLL VCO analog out (for testing)