remove & rd_l.q, is now in group picker

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 3a997fdb8236fe32b67ce2909f559a734c49fac8..c6f52cb844b2d0f9d254abf6295f75f5caf78107 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -342,7 +342,7 @@ def scoreboard_sim(dut, alusim):
             else:
                 src1 = 5
                 src2 = 3
-                dest = 7
+                dest = 4
 
             #op = (i+1) % 2
             op = i

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index fc05a9af3c198583b46ae3dc546c516a91ae9f72..c8fc8d76e80d35023d0967034e303272588f9e96 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -165,7 +165,7 @@ class FnUnit(Elaboratable):
         ro = Signal(reset_less=True)
         m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
         m.d.comb += ro.eq(~g_rd.bool())
-        m.d.comb += self.readable_o.eq(ro & rd_l.q)
+        m.d.comb += self.readable_o.eq(ro)
 
         # writable output signal
         g_wr_v = Signal(self.reg_width, reset_less=True)