add in SVP64 LD/ST basic test for ISACaller

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index f7a015adf44e0f3131d1e2cb540d7aa95c07dc72..f6c83e672370cfcd4b0b0aebdf69da0b6a67a2cf 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -836,6 +836,10 @@ class ISACaller:
             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 
+        # get SVSTATE VL
+        if self.is_svp64_mode:
+            vl = self.svstate.vl.asint(msb0=True)
+
         # VL=0 in SVP64 mode means "do nothing: skip instruction"
         if self.is_svp64_mode and vl == 0:
             self.pc.update(self.namespace, self.is_svp64_mode)

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 118886c18d36faa9ff4f18cc5a2216d573500f2b..1eebf7bfbd8244d764556b6328030af0cf8312a6 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -21,6 +21,24 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
+    def test_sv_load_store(self):
+        lst = SVP64Asm(["addi 1, 0, 0x0010",
+                        "addi 2, 0, 0x1234",
+                        "sv.stw 2, 0(1)",
+                        "sv.lwz 3, 0(1)"])
+        lst = list(lst)
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 1 # VL
+        svstate.maxvl[0:7] = 1 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate)
+            print(sim.gpr(1))
+            self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
+
     def test_sv_add(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234