Fix flake8 errors in part_cmp/

diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py
index 4614776d54a2d482b58356e82fcbc35aad6f28bb..4cc8a0ef081a43fdc6bb4727f6626a172da58afa 100644 (file)
--- a/src/ieee754/part_cmp/eq_gt_ge.py
+++ b/src/ieee754/part_cmp/eq_gt_ge.py
@@ -15,14 +15,12 @@ See:
 * http://bugs.libre-riscv.org/show_bug.cgi?id=171
 """
 
-from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.cli import main, rtlil
+from nmigen import Signal, Module, Elaboratable, Cat, C
+from nmigen.back.pysim import Simulator, Delay
 
 from ieee754.part_mul_add.partpoints import PartitionPoints
 from ieee754.part_cmp.gt_combiner import GTCombiner
 from ieee754.part_cmp.reorder_results import ReorderResults
-from ieee754.part_cmp.ripple import RippleLSB
 
 
 class PartitionedEqGtGe(Elaboratable):
@@ -47,7 +45,7 @@ class PartitionedEqGtGe(Elaboratable):
         self.mwidth = len(self.partition_points)+1
         self.output = Signal(self.mwidth, reset_less=True)
         assert self.partition_points.fits_in_width(width), \
-                "partition_points doesn't fit in width"
+            "partition_points doesn't fit in width"
 
     def elaborate(self, platform):
         m = Module()
@@ -110,6 +108,7 @@ class PartitionedEqGtGe(Elaboratable):
                 self.partition_points.as_sig(),
                 self.output]
 
+
 if __name__ == "__main__":
     from ieee754.part_mul_add.partpoints import make_partition
     m = Module()

diff --git a/src/ieee754/part_cmp/gt_combiner.py b/src/ieee754/part_cmp/gt_combiner.py
index 2828cd16d1311f63ac0b8cf7e9e72b7345efb65d..05082028cdf8f5d9b68482d2182b59a4d9a5f113 100644 (file)
--- a/src/ieee754/part_cmp/gt_combiner.py
+++ b/src/ieee754/part_cmp/gt_combiner.py
@@ -1,5 +1,5 @@
 from nmigen import Signal, Module, Elaboratable, Mux
-from ieee754.part_mul_add.partpoints import PartitionPoints
+
 
 class Combiner(Elaboratable):
 
@@ -28,6 +28,7 @@ class Combiner(Elaboratable):
 # equal flag is set AND the previous partition's greater than output
 # is true
 
+
 class GTCombiner(Elaboratable):
 
     def __init__(self, width):
@@ -46,8 +47,8 @@ class GTCombiner(Elaboratable):
         self.aux_input = Signal(reset_less=True)  # right hand side mux input
         self.gt_en = Signal(reset_less=True)      # enable or disable gt signal
 
-        self.eqs = Signal(width, reset_less=True) # the flags for EQ
-        self.gts = Signal(width, reset_less=True) # the flags for GT
+        self.eqs = Signal(width, reset_less=True)  # the flags for EQ
+        self.gts = Signal(width, reset_less=True)  # the flags for GT
         self.gates = Signal(width-1, reset_less=True)
         self.outputs = Signal(width, reset_less=True)
 

diff --git a/src/ieee754/part_cmp/reorder_results.py b/src/ieee754/part_cmp/reorder_results.py
index 41c646527d6424e9a73ef03f365de653431ee94f..e1a03476e4319981f13f3622189dd7ebd28995f3 100644 (file)
--- a/src/ieee754/part_cmp/reorder_results.py
+++ b/src/ieee754/part_cmp/reorder_results.py
@@ -3,7 +3,7 @@
 # bits need to be reversed through the width of the partition. This
 # module does that
 from nmigen import Signal, Module, Elaboratable, Mux
-from ieee754.part_mul_add.partpoints import PartitionPoints
+
 
 class ReorderResults(Elaboratable):
     def __init__(self, width):