<li>GL_ARB_shader_group_vote on radeonsi</li>
<li>GL_ARB_transform_feedback2 on i965/gen6</li>
<li>GL_ARB_transform_feedback_overflow_query on i965/gen6+</li>
+<li>GL_NV_fill_rectangle on nvc0</li>
<li>Geometry shaders enabled on swr</li>
</ul>
#define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__ESIZE 0x00000004
#define NVC0_3D_VTX_ATTR_MASK_UNK0DD0_ALT__LEN 0x00000004
+#define NVC0_3D_FILL_RECTANGLE 0x0000113c
+#define NVC0_3D_FILL_RECTANGLE_ENABLE 0x00000002
+
#define NVC0_3D_UNK1140 0x00001140
#define NVC0_3D_UNK1144 0x00001144
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
case PIPE_CAP_TGSI_FS_FBFETCH:
return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+ case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+ return class_3d >= GM200_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_CLOCK:
- case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
return 0;
case PIPE_CAP_VENDOR_ID:
const struct pipe_rasterizer_state *cso)
{
struct nvc0_rasterizer_stateobj *so;
+ uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
uint32_t reg;
so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
+ if (class_3d >= GM200_3D_CLASS) {
+ SB_IMMED_3D(so, FILL_RECTANGLE,
+ cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
+ NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
+ }
+
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
struct nvc0_rasterizer_stateobj {
struct pipe_rasterizer_state pipe;
int size;
- uint32_t state[42];
+ uint32_t state[43];
};
struct nvc0_zsa_stateobj {