add reg allocation requirements

diff --git a/libreriscv b/libreriscv
index 2d8ae9db6019c3a7ed881f14612f2b66bb263a9e..f7602e599e6557e45249b80d888631a9cf241cb7 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 2d8ae9db6019c3a7ed881f14612f2b66bb263a9e
+Subproject commit f7602e599e6557e45249b80d888631a9cf241cb7

diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 710e5e1e85743ff5c43682d88767f3af0c63001f..f3bb8f13d673f525d5400643c088dcb1204d3e13 100644 (file)
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -15,6 +15,22 @@ class IntegerData:
     def eq(self, i):
         return [self.ctx.eq(i.ctx)]
 
+"""
+    def op_b(LR):
+    def op_ba(LR):
+    def op_bl(LR):
+    def op_bla(LR):
+    def op_bc(LR, CR, CTR):
+    def op_bca(LR, CR, CTR):
+    def op_bcl(LR, CR, CTR):
+    def op_bcla(LR, CR, CTR):
+    def op_bclr(LR, CR, CTR):
+    def op_bclrl(LR, CR, CTR):
+    def op_bcctr(LR, CR, CTR):
+    def op_bcctrl(LR, CR, CTR):
+    def op_bctar(LR, CR, CTR, TAR):
+    def op_bctarl(LR, CR, CTR, TAR):
+"""
 
 class BranchInputData(IntegerData):
     def __init__(self, pspec):