update comment-headers (TODO include page numbers to v3.0B spec)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 25 Jul 2020 11:14:31 +0000 (12:14 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 25 Jul 2020 11:14:31 +0000 (12:14 +0100)
src/soc/fu/trap/main_stage.py

index 80cb913c3fc5b37b59add6fb80be5ca937e68d90..780a2976141a81042f3c45cc8fce4445dcdad567 100644 (file)
@@ -177,7 +177,10 @@ class TrapMainStage(PipeModBase):
 
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
-            #### trap ####
+
+            ###############
+            # TDI/TWI/TD/TW.  v3.0B p90-91
+
             with m.Case(MicrOp.OP_TRAP):
                 # trap instructions (tw, twi, td, tdi)
                 with m.If(should_trap):
@@ -199,7 +202,9 @@ class TrapMainStage(PipeModBase):
                     # when SRR1 is written to, update MSR bits
                     self.msr_exception(m, trapaddr)
 
-            # move to MSR
+            ###################
+            # MTMSR/D.  v3.0B p TODO - move to MSR
+
             with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):
                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 # start with copy of msr
@@ -232,12 +237,17 @@ class TrapMainStage(PipeModBase):
 
                 comb += msr_o.ok.eq(1)
 
-            # move from MSR
+            ###################
+            # MFMSR.  v3.0B p TODO - move from MSR
+
             with m.Case(MicrOp.OP_MFMSR):
                 # some of the bits need zeroing?  apparently not
                 comb += o.data.eq(msr_i)
                 comb += o.ok.eq(1)
 
+            ###################
+            # RFID.  v3.0B p955
+
             with m.Case(MicrOp.OP_RFID):
                 # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
                 # XXX f_out.priv_mode <= not b_in(MSR.PR);
@@ -267,7 +277,9 @@ class TrapMainStage(PipeModBase):
 
                 comb += msr_o.ok.eq(1)
 
-            # OP_SC
+            #################
+            # SC.  v3.0B p952
+
             with m.Case(MicrOp.OP_SC):
                 # scv is not covered here. currently an illegal instruction.
                 # raising "illegal" is the decoder's job, not ours, here.