make carry output handling optional in common output stage

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 96de016b495486cfe0607cc970c082e4cc063af1..cddf311fceae2fce8b23c1f430583f828166fe90 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -32,9 +32,12 @@ class CommonOutputStage(PipeModBase):
         with m.Else():
             comb += target.eq(o)
 
-        # Handle carry_out
-        comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
-        comb += self.o.xer_ca.ok.eq(op.output_carry)
+        # carry-out only if actually present in this input spec
+        # (note: MUL and DIV do not have it, but ALU and Logical do)
+        if hasattr(self.i.xer_ca):
+            # Handle carry_out
+            comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
+            comb += self.o.xer_ca.ok.eq(op.output_carry)
 
         # create condition register cr0 and sticky-overflow
         is_nzero = Signal(reset_less=True)