missed some variables in the cleanup

diff --git a/libreriscv b/libreriscv
index 2d8ae9db6019c3a7ed881f14612f2b66bb263a9e..f7602e599e6557e45249b80d888631a9cf241cb7 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 2d8ae9db6019c3a7ed881f14612f2b66bb263a9e
+Subproject commit f7602e599e6557e45249b80d888631a9cf241cb7

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index de1fdcb170061d4d1e3881de2c86b6d91610532d..9a3279068f6557a45521c132bb977752159f337a 100644 (file)
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -83,11 +83,10 @@ class BranchMainStage(PipeModBase):
                 comb += bd.eq(b_fields['BD'][0:-1])
                 bd_sgn = bd[-1]
 
-                comb += branch_imm_addr.eq(
+                comb += br_imm_addr.eq(
                     Cat(Const(0, 2), bd,
                         Repl(bd_sgn, 64-(bd.width + 2))))
-                comb += branch_taken.eq(bc_taken)
-
+                comb += br_taken.eq(bc_taken)
 
         comb += self.o.nia_out.data.eq(br_addr)
         comb += self.o.nia_out.ok.eq(br_taken)