more remove wildcard imports

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 4c4154d68ab41d5da5676e0a4811419ecfe292f4..3d4d7a3912420b68c7d64e0997f1c0bbe2ae7ea2 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -1,6 +1,6 @@
 import os
 
-from migen import *
+from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU

diff --git a/src/soc/litex/florent/microwatt/core.py b/src/soc/litex/florent/microwatt/core.py
index b57f7bcf01941da7a985808317ebc2b6103be213..704eb18fbc0ad007f7a18f00c9892ce37d88d0b7 100644 (file)
--- a/src/soc/litex/florent/microwatt/core.py
+++ b/src/soc/litex/florent/microwatt/core.py
@@ -4,7 +4,7 @@
 
 import os
 
-from migen import *
+from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -48,8 +48,8 @@ class Microwatt(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.ibus         = ibus = wishbone.Interface(data_width=64, adr_width=29)
-        self.dbus         = dbus = wishbone.Interface(data_width=64, adr_width=29)
+        self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
+        self.dbus = dbus = wishbone.Interface(data_width=64, adr_width=29)
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index a24833d800e1459470a82c43273ede009a4dffab..09674ae69c771ce4e0ac445827f69f16952736a6 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -3,7 +3,7 @@
 import os
 import argparse
 
-from migen import Signal, FSM
+from migen import Signal, FSM, If, Display, Finish
 
 from litex.build.generic_platform import Pins, Subsignal
 from litex.build.sim import SimPlatform