do mix-in for test_sim.py so that jacob can write some div tests without

having to run all the other ones

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 9ab807d6094de356427829969d5aa8eea48b90bd..de4193bc5f3bacd7311a984682e728c52484b6a4 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -207,7 +207,7 @@ class GeneralTestCases(FHDLTestCase):
         self.test_data.append(tc)
 
 
-class DecoderTestCase(GeneralTestCases):
+class DecoderBase:
 
     def run_tst(self, generator, initial_mem=None):
         m = Module()
@@ -290,5 +290,9 @@ class DecoderTestCase(GeneralTestCases):
             self.assertEqual(qemu_val, sim_val)
 
 
+class DecoderTestCase(DecoderBase, GeneralTestCases):
+    pass
+
+
 if __name__ == "__main__":
     unittest.main()