shrink test memory size down to only 64 words

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index eb79f676ca6366d5ac24a78917822fe801dcbd0f..bd3422f0a97c737e7a357037acab1607188b9e9d 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -205,7 +205,9 @@ class TestMemoryPortInterface(Elaboratable):
     """
 
     def __init__(self, regwid=64, addrwid=4):
-        self.mem = TestMemory(regwid, addrwid, granularity=regwid//8)
+        # hard-code memory addressing width to 6 bits
+        self.mem = TestMemory(regwid, 6, granularity=regwid//8,
+                              init=False)
         self.regwid = regwid
         self.addrwid = addrwid
         self.pi = LDSTPort(0, regwid, addrwid)

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 5a1165de7dc994e5d3d7d693d79771fa0e4ba5d0..02000d89e375f830a1760c13ef818f68cfc1287d 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -2,13 +2,17 @@ from nmigen import Module, Elaboratable, Memory
 
 
 class TestMemory(Elaboratable):
-    def __init__(self, regwid, addrw, granularity=None):
+    def __init__(self, regwid, addrw, granularity=None, init=True):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.depth = depth
         self.regwid = regwid
-        self.mem   = Memory(width=regwid, depth=depth,
-                            init=range(0, depth*2, 2))
+        print ("test memory", regwid, depth)
+        if init is True:
+            init = range(0, depth*2, 2)
+        else:
+            init = None
+        self.mem = Memory(width=regwid, depth=depth, init=init)
         self.rdport = self.mem.read_port() # not now transparent=False)
         self.wrport = self.mem.write_port(granularity=granularity)