test actual reg values being produced in core test

diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 02f0ca831014bec4b908b39eed855c83fb196118..80eebf48f06af96da4ae10586613a2946324d88d 100644 (file)
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -363,6 +363,9 @@ class SelectableInt:
     def __len__(self):
         return self.bits
 
+    def asint(self):
+        return self.value
+
 def onebit(bit):
     return SelectableInt(1 if bit else 0, 1)
 

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 877c215ebb5cb6aa55a3acfcd88e83a8ccb22326..5ec289dc8263b5991d57d20f5227d71eaad0c2d8 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -13,8 +13,8 @@ from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok # hack
 
 # test with ALU data and Logical data
-#from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
-from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data
+from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
+#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data
 
 
 def set_cu_input(cu, idx, data):
@@ -176,13 +176,10 @@ class TestRunner(FHDLTestCase):
                         rval = yield core.regs.int.regs[i].reg
                         intregs.append(rval)
                     print ("int regs", intregs)
-                    if False:
-                        yield Settle()
-                        # get all outputs (one by one, just "because")
-                        res = yield from get_cu_outputs(cu, code)
-
-                        yield from self.iodef.check_cu_outputs(res, pdecode2,
-                                                                sim, code)
+                    for i in range(32):
+                        simregval = sim.gpr[i].asint()
+                        self.assertEqual(simregval, intregs[i],
+                            "int reg %d not equal %s" % (i, repr(code)))
 
         sim.add_sync_process(process)
         with sim.write_vcd("core_simulator.vcd", "core_simulator.gtkw",