Fix instructions in comment
authorRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)
src/ls2.py

index 21a71fa81659772dc403fe217cc4f63a3f4134b2..235caf89689d1a3f9d86bd085725a757685be9d8 100644 (file)
@@ -513,7 +513,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         if hasattr(self, "spi0"):
             # add Tercel verilog source. assumes a directory
-            # structure where ls2 has been checked out in a common
+            # structure where microwatt has been checked out in a common
             # subdirectory as https://git.libre-soc.org/git/microwatt.git
             raptor_tercel = "../../microwatt/tercel"
             pth = os.path.split(__file__)[0]