remove io_in/io_out from niolib experiments10

diff --git a/experiments10/add.py b/experiments10/add.py
index a3b6f085958152a1e2df940e779bcd409a1f8cfb..3f0653237607bf93ae7dfd0fd6c39840ac80f635 100644 (file)
--- a/experiments10/add.py
+++ b/experiments10/add.py
@@ -17,8 +17,6 @@ class ADD(Elaboratable):
         self.a      = Signal(width)
         self.b      = Signal(width)
         self.f      = Signal(width)
-        self.io_in  = Signal(1)
-        self.io_out = Signal(1)
 
         # set up JTAG
         self.jtag = TAP(ir_width=3)
@@ -35,8 +33,6 @@ class ADD(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.io_in.eq(False)
-        m.d.comb += self.io_out.eq(True)
 
         m.submodules.jtag = jtag = self.jtag
         m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
@@ -55,7 +51,6 @@ def create_ilang(dut, ports, test_name):
 if __name__ == "__main__":
     alu = ADD(width=4)
     create_ilang(alu, [alu.a, alu.b, alu.f,
-                       alu.io_in, alu.io_out,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
                         alu.jtag.bus.tdo,

diff --git a/experiments10/doDesign.py b/experiments10/doDesign.py
index 3dc4bc6949437df29ea6b7dcc897fa8f4b1b6982..21d45b0e715731ec7400bb0f78653e1056e6a830 100644 (file)
--- a/experiments10/doDesign.py
+++ b/experiments10/doDesign.py
@@ -38,30 +38,30 @@ def scriptMain ( **kw ):
         #     Spec: 
         # | Side        | Pos | Instance     | Pad net   |Core net | Direction |
         ioPadsSpec = [
-           (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'   , 'io_in'   )
-         , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'   , 'io_in'   )
+           (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'     )
+         , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'     )
          , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
          , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
-         , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'   , 'io_in'   )
-         , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'   , 'io_in'   )
-         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'    , 'io_in'   )
-         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'    , 'io_out'  )
+         , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'     )
+         , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'     )
+         , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'      )
+         , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'      )
          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
-         , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'    , 'io_in'   )
-         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'    , 'io_in'   )
-         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'    , 'io_in'   )
-         , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'   , 'io_in'   )
+         , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'      )
+         , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'      )
+         , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'      )
+         , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
          , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
-         , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'   , 'io_in'   )
+         , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
-         , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'   , 'io_in'   )
-         , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'    , 'io_in'   )
-         , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'   , 'io_out'  )
-         , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'   , 'io_out'  )
+         , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
+         , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'      )
+         , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
+         , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
-         , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'   , 'io_out'  )
-         , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'   , 'io_out'  )
-         , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'   , 'io_in'   )
+         , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'     )
+         , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'     )
+         , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'     )
         ]
         adderConf = ChipConf( cell, ioPads=ioPadsSpec )
         adderConf.cfg.etesian.bloat = 'nsxlib'