attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec19"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec19"
module \dec19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 10 \opcode_switch
process $group_0
assign \opcode_switch 10'0000000000
assign \opcode_switch \opcode_in [10:1]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch$1
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \function_unit 10'0000100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \function_unit 10'0000100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \function_unit 10'0000100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \function_unit 10'0010000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \form 5'01001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \form 5'01001
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'00111
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \internal_op 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \internal_op 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \internal_op 7'0001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \internal_op 7'0001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \internal_op 7'0001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \internal_op 7'0100100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \internal_op 7'1000110
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0000000
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \in1_sel 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \in1_sel 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \in1_sel 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \in1_sel 3'011
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \in2_sel 4'1100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \in2_sel 4'1100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \in2_sel 4'1100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \in2_sel 4'1100
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \in3_sel 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \out_sel 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \out_sel 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \out_sel 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \out_sel 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \cr_in 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \cr_in 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \cr_in 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \cr_in 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \cr_in 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \cr_in 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \cr_out 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \cr_out 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \ldst_len 4'0000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \rc_sel 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \cry_in 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \asmcode 8'01101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \asmcode 8'00100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \asmcode 8'00100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \asmcode 8'00100111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \asmcode 8'00101000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \asmcode 8'00101001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \asmcode 8'00101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \asmcode 8'00101011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \asmcode 8'00101100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \asmcode 8'00010110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \asmcode 8'00010111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \asmcode 8'00011000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \asmcode 8'01001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \asmcode 8'10001110
end
sync init
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \inv_a 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \inv_out 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \cry_out 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \br 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \sgn_ext 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \upd 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \rsrv 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \is_32b 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \sgn 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \lk 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \lk 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \lk 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \lk 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000000000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100000001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010000001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0100100001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011100001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000100001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0111000001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0110100001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0011000001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000010000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0000010000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'1000110000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 10'0010010110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 10'0000010010
assign \sgl_pipe 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec30"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec30"
module \dec30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 4 \opcode_switch
process $group_0
assign \opcode_switch 4'0000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \function_unit 10'0000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \form 5'10101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \form 5'10101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \form 5'10100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \form 5'10100
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \internal_op 7'0111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \internal_op 7'0111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \internal_op 7'0111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \internal_op 7'0111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \internal_op 7'0111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \internal_op 7'0111010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \asmcode 8'10010001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \asmcode 8'10010001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \asmcode 8'10010010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \asmcode 8'10010010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \asmcode 8'10010011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \asmcode 8'10010011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \asmcode 8'10010100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \asmcode 8'10010100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \asmcode 8'10001111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \asmcode 8'10010000
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'0111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 4'1001
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub10"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub10"
module \dec_sub10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \internal_op 7'0000010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in2_sel 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_in 2'10
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'00000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'00001100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'00000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'00000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'00000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \asmcode 8'00000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'00001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \asmcode 8'00001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \asmcode 8'00001101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \asmcode 8'00001110
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_out 1'1
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub28"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub28"
module \dec_sub28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \function_unit 10'0000010000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \internal_op 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \internal_op 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \internal_op 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \internal_op 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \internal_op 7'1000011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'00001111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'00010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'00011001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \asmcode 8'00011011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'01000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \asmcode 8'10000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'10000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \asmcode 8'10000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \asmcode 8'10000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \asmcode 8'11001001
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub0"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub0"
module \dec_sub0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'11000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0001100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0111011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'011
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'00011010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'00011100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'00011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10011000
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub26"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub26"
module \dec_sub26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \function_unit 10'0000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \form 5'10000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \internal_op 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \internal_op 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \internal_op 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \internal_op 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \internal_op 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \internal_op 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \internal_op 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in2_sel 4'1010
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'00100001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'00100010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \asmcode 8'00100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'00100100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \asmcode 8'01000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \asmcode 8'01000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \asmcode 8'01000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'10001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \asmcode 8'10001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \asmcode 8'10001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \asmcode 8'10001100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10001101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'10011100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \asmcode 8'10011101
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_out 1'1
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub19"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub19"
module \dec_sub19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \form 5'01010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \form 5'01010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'1000111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \internal_op 7'0101110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \internal_op 7'0110001
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in1_sel 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \out_sel 2'11
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01101110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \asmcode 8'01101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \asmcode 8'01110110
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub22"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub22"
module \dec_sub22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \internal_op 7'0100001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \internal_op 7'0000001
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'00101110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'00101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'00110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'00110001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \asmcode 8'01001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'01011100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'01100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \asmcode 8'10100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \asmcode 8'10101001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \asmcode 8'10101110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \asmcode 8'10101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \asmcode 8'10110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \asmcode 8'11000100
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \br 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \br 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub9"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub9"
module \dec_sub9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \function_unit 10'0100000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \internal_op 7'0110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0110010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \internal_op 7'0110010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \asmcode 8'00110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \asmcode 8'00110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \asmcode 8'00110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \asmcode 8'00110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \asmcode 8'00111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \asmcode 8'00111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \asmcode 8'00110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \asmcode 8'00111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'01110010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'01110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \asmcode 8'01110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'01111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'01111011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \asmcode 8'01111100
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub11"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub11"
module \dec_sub11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'1000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \function_unit 10'0100000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \internal_op 7'0011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \internal_op 7'0011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0101111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \internal_op 7'0110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0110100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0110010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \internal_op 7'0110010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \asmcode 8'00111110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \asmcode 8'00111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \asmcode 8'00111100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \asmcode 8'00111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \asmcode 8'01000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \asmcode 8'01000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \asmcode 8'00111011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \asmcode 8'01000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'01110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'01110001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \asmcode 8'01111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'01111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'01111110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \asmcode 8'01111111
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub27"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub27"
module \dec_sub27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \form 5'10000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0111100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \internal_op 7'0111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in2_sel 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'10011010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \asmcode 8'10011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'10100000
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub15"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub15"
module \dec_sub15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \function_unit 10'0001000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \function_unit 10'0001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \form 5'10010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \form 5'10010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \internal_op 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \internal_op 7'0100011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_in 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_in 3'101
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \asmcode 8'01001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \asmcode 8'01001010
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11111
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub20"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub20"
module \dec_sub20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \function_unit 10'0000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \ldst_len 4'1000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'01001100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01010010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'01010011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'01011000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01100010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \asmcode 8'10101000
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \br 1'1
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub23"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub23"
module \dec_sub23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0100
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'01001111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'01010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \asmcode 8'01011010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \asmcode 8'01011011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \asmcode 8'01011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \asmcode 8'01100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'01101000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01101001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'10100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \asmcode 8'10100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \asmcode 8'10110001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \asmcode 8'10110010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \asmcode 8'10110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10111000
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub21"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub21"
module \dec_sub21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'1000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'01010101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'01010110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \asmcode 8'01100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \asmcode 8'01100100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \asmcode 8'10101011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10101100
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub16"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub16"
module \dec_sub16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'01010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0110000
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'110
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'100
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'01110100
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub18"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub18"
module \dec_sub18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \internal_op 7'1001000
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_in 2'00
end
end
process $group_13
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_a 1'0
end
end
process $group_14
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \inv_out 1'0
end
end
process $group_15
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \cry_out 1'0
end
end
process $group_16
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \br 1'0
end
end
process $group_17
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn_ext 1'0
end
end
process $group_18
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \upd 1'0
end
end
process $group_19
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \rsrv 1'0
end
end
process $group_20
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \is_32b 1'0
end
end
process $group_21
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgn 1'0
end
end
process $group_22
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \lk 1'0
end
end
process $group_23
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00101
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub8"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub8"
module \dec_sub8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \function_unit 10'0000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \form 5'10001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \internal_op 7'0000010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in2_sel 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in2_sel 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_in 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_in 2'10
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \asmcode 8'10000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \asmcode 8'10000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \asmcode 8'10111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \asmcode 8'11000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'10111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'10111011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \asmcode 8'10111100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \asmcode 8'10111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \asmcode 8'10111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \asmcode 8'11000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \asmcode 8'11000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \asmcode 8'11000011
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_a 1'1
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \cry_out 1'1
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10110
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub24"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub24"
module \dec_sub24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \function_unit 10'0000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0111100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \internal_op 7'0111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \internal_op 7'0111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in2_sel 4'1011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rc_sel 2'10
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'10011011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \asmcode 8'10011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \asmcode 8'10011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \asmcode 8'10100001
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'11001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'10000
assign \sgl_pipe 1'0
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31.dec_sub4"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub4"
module \dec_sub4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \function_unit 10'0010000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \function_unit 10'0010000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \form 5'01000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \internal_op 7'0111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \internal_op 7'0111111
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \ldst_len 4'0000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \asmcode 8'11000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \asmcode 8'11000111
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 5'00000
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec31"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31"
module \dec31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub10_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub10_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub10_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub10_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub10_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub10_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub10_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub10_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub10_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub10_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub10_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub10_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub10_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub10_sgl_pipe
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub10_asmcode
cell \dec_sub10 \dec_sub10
connect \opcode_in \dec_sub10_opcode_in
connect \sgl_pipe \dec_sub10_sgl_pipe
connect \asmcode \dec_sub10_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub28_opcode_in
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attribute \enum_value_1000000000 "DIV"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub28_function_unit
attribute \enum_base_type "Form"
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attribute \enum_value_11100 "Z23"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub28_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
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wire width 7 \dec_sub28_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub28_in1_sel
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wire width 4 \dec_sub28_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub28_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub28_out_sel
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wire width 3 \dec_sub28_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_100 "WHOLE_REG"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub28_cr_out
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wire width 2 \dec_sub28_rc_sel
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wire width 4 \dec_sub28_ldst_len
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attribute \enum_value_00 "ZERO"
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wire width 2 \dec_sub28_cry_in
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wire width 1 \dec_sub28_inv_a
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wire width 1 \dec_sub28_inv_out
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wire width 1 \dec_sub28_cry_out
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wire width 1 \dec_sub28_br
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wire width 1 \dec_sub28_sgn_ext
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wire width 1 \dec_sub28_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub28_rsrv
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wire width 1 \dec_sub28_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub28_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub28_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub28_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
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wire width 8 \dec_sub28_asmcode
cell \dec_sub28 \dec_sub28
connect \opcode_in \dec_sub28_opcode_in
connect \sgl_pipe \dec_sub28_sgl_pipe
connect \asmcode \dec_sub28_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
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wire width 32 \dec_sub0_opcode_in
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wire width 10 \dec_sub0_function_unit
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wire width 5 \dec_sub0_form
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wire width 7 \dec_sub0_internal_op
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wire width 3 \dec_sub0_in1_sel
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wire width 4 \dec_sub0_in2_sel
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wire width 2 \dec_sub0_in3_sel
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wire width 2 \dec_sub0_out_sel
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wire width 3 \dec_sub0_cr_in
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wire width 3 \dec_sub0_cr_out
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wire width 4 \dec_sub0_ldst_len
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wire width 2 \dec_sub0_cry_in
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wire width 1 \dec_sub0_inv_a
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wire width 1 \dec_sub0_inv_out
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wire width 1 \dec_sub0_cry_out
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wire width 1 \dec_sub0_br
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wire width 1 \dec_sub0_sgn_ext
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wire width 1 \dec_sub0_upd
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wire width 1 \dec_sub0_is_32b
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wire width 1 \dec_sub0_sgn
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wire width 1 \dec_sub0_lk
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wire width 1 \dec_sub0_sgl_pipe
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wire width 8 \dec_sub0_asmcode
cell \dec_sub0 \dec_sub0
connect \opcode_in \dec_sub0_opcode_in
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connect \asmcode \dec_sub0_asmcode
end
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wire width 32 \dec_sub26_opcode_in
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wire width 10 \dec_sub26_function_unit
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wire width 5 \dec_sub26_form
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wire width 7 \dec_sub26_internal_op
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wire width 3 \dec_sub26_in1_sel
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wire width 4 \dec_sub26_in2_sel
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wire width 2 \dec_sub26_in3_sel
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wire width 2 \dec_sub26_out_sel
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wire width 3 \dec_sub26_cr_in
attribute \enum_base_type "CROutSel"
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wire width 3 \dec_sub26_cr_out
attribute \enum_base_type "RC"
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wire width 2 \dec_sub26_rc_sel
attribute \enum_base_type "LdstLen"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub26_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub26_cry_in
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub26_inv_a
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub26_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub26_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub26_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub26_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub26_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub26_asmcode
cell \dec_sub26 \dec_sub26
connect \opcode_in \dec_sub26_opcode_in
connect \sgl_pipe \dec_sub26_sgl_pipe
connect \asmcode \dec_sub26_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub19_opcode_in
attribute \enum_base_type "Function"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub19_function_unit
attribute \enum_base_type "Form"
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attribute \enum_value_11100 "Z23"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub19_form
attribute \enum_base_type "InternalOp"
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attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
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wire width 7 \dec_sub19_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
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wire width 3 \dec_sub19_in1_sel
attribute \enum_base_type "In2Sel"
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wire width 4 \dec_sub19_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
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wire width 2 \dec_sub19_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
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attribute \enum_value_11 "SPR"
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wire width 2 \dec_sub19_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_110 "WHOLE_REG"
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wire width 3 \dec_sub19_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_100 "WHOLE_REG"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub19_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
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attribute \enum_value_10 "RC"
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wire width 2 \dec_sub19_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
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attribute \enum_value_0100 "is4B"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
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wire width 4 \dec_sub19_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
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wire width 2 \dec_sub19_cry_in
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wire width 1 \dec_sub19_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub19_inv_out
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wire width 1 \dec_sub19_cry_out
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wire width 1 \dec_sub19_br
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wire width 1 \dec_sub19_sgn_ext
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wire width 1 \dec_sub19_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub19_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub19_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub19_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub19_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub19_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub19_asmcode
cell \dec_sub19 \dec_sub19
connect \opcode_in \dec_sub19_opcode_in
connect \sgl_pipe \dec_sub19_sgl_pipe
connect \asmcode \dec_sub19_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub22_opcode_in
attribute \enum_base_type "Function"
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attribute \enum_value_1000000000 "DIV"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub22_function_unit
attribute \enum_base_type "Form"
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attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub22_form
attribute \enum_base_type "InternalOp"
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attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
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wire width 7 \dec_sub22_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_100 "RS"
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wire width 3 \dec_sub22_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
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attribute \enum_value_1101 "RS"
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wire width 4 \dec_sub22_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
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wire width 2 \dec_sub22_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub22_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
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attribute \enum_value_110 "WHOLE_REG"
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wire width 3 \dec_sub22_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
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attribute \enum_value_100 "WHOLE_REG"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub22_cr_out
attribute \enum_base_type "RC"
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wire width 2 \dec_sub22_rc_sel
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attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub22_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec_sub22_cry_in
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub22_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub22_asmcode
cell \dec_sub22 \dec_sub22
connect \opcode_in \dec_sub22_opcode_in
connect \sgl_pipe \dec_sub22_sgl_pipe
connect \asmcode \dec_sub22_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub9_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub9_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub9_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub9_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub9_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub9_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub9_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub9_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub9_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub9_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub9_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub9_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub9_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub9_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub9_asmcode
cell \dec_sub9 \dec_sub9
connect \opcode_in \dec_sub9_opcode_in
connect \sgl_pipe \dec_sub9_sgl_pipe
connect \asmcode \dec_sub9_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub11_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub11_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub11_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub11_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub11_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub11_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub11_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub11_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub11_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub11_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub11_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub11_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub11_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub11_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub11_asmcode
cell \dec_sub11 \dec_sub11
connect \opcode_in \dec_sub11_opcode_in
connect \sgl_pipe \dec_sub11_sgl_pipe
connect \asmcode \dec_sub11_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub27_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub27_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub27_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub27_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub27_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub27_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub27_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub27_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub27_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub27_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub27_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
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wire width 8 \dec_sub27_asmcode
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end
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wire width 5 \dec_sub15_form
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end
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wire width 1 \dec_sub20_is_32b
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wire width 8 \dec_sub20_asmcode
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end
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wire width 10 \dec_sub23_function_unit
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wire width 5 \dec_sub23_form
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wire width 3 \dec_sub23_in1_sel
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wire width 4 \dec_sub23_in2_sel
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wire width 2 \dec_sub23_out_sel
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wire width 3 \dec_sub23_cr_in
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wire width 3 \dec_sub23_cr_out
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wire width 4 \dec_sub23_ldst_len
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wire width 8 \dec_sub23_asmcode
cell \dec_sub23 \dec_sub23
connect \opcode_in \dec_sub23_opcode_in
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connect \asmcode \dec_sub23_asmcode
end
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wire width 32 \dec_sub21_opcode_in
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wire width 10 \dec_sub21_function_unit
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wire width 5 \dec_sub21_form
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wire width 4 \dec_sub21_in2_sel
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wire width 1 \dec_sub21_is_32b
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wire width 1 \dec_sub21_sgl_pipe
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wire width 8 \dec_sub21_asmcode
cell \dec_sub21 \dec_sub21
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end
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wire width 5 \dec_sub16_form
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wire width 4 \dec_sub16_in2_sel
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wire width 4 \dec_sub16_ldst_len
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wire width 2 \dec_sub16_cry_in
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wire width 1 \dec_sub16_inv_a
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wire width 1 \dec_sub16_inv_out
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wire width 1 \dec_sub16_cry_out
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wire width 1 \dec_sub16_br
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wire width 1 \dec_sub16_sgn_ext
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wire width 1 \dec_sub16_upd
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wire width 1 \dec_sub16_rsrv
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wire width 1 \dec_sub16_is_32b
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wire width 1 \dec_sub16_sgn
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wire width 1 \dec_sub16_lk
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wire width 1 \dec_sub16_sgl_pipe
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub16_asmcode
cell \dec_sub16 \dec_sub16
connect \opcode_in \dec_sub16_opcode_in
connect \sgl_pipe \dec_sub16_sgl_pipe
connect \asmcode \dec_sub16_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
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wire width 32 \dec_sub18_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
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attribute \enum_value_1000000000 "DIV"
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wire width 10 \dec_sub18_function_unit
attribute \enum_base_type "Form"
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wire width 5 \dec_sub18_form
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attribute \enum_value_1000111 "OP_MFMSR"
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wire width 7 \dec_sub18_internal_op
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attribute \enum_value_000 "NONE"
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wire width 3 \dec_sub18_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
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wire width 4 \dec_sub18_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub18_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub18_out_sel
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attribute \enum_value_000 "NONE"
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wire width 3 \dec_sub18_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
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wire width 3 \dec_sub18_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub18_rc_sel
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wire width 4 \dec_sub18_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
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wire width 2 \dec_sub18_cry_in
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wire width 1 \dec_sub18_inv_a
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wire width 1 \dec_sub18_inv_out
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wire width 1 \dec_sub18_cry_out
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wire width 1 \dec_sub18_br
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wire width 1 \dec_sub18_sgn_ext
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wire width 1 \dec_sub18_upd
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wire width 1 \dec_sub18_rsrv
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wire width 1 \dec_sub18_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec_sub18_sgn
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wire width 1 \dec_sub18_lk
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wire width 1 \dec_sub18_sgl_pipe
cell \dec_sub18 \dec_sub18
connect \opcode_in \dec_sub18_opcode_in
connect \lk \dec_sub18_lk
connect \sgl_pipe \dec_sub18_sgl_pipe
end
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wire width 32 \dec_sub8_opcode_in
attribute \enum_base_type "Function"
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wire width 10 \dec_sub8_function_unit
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wire width 5 \dec_sub8_form
attribute \enum_base_type "InternalOp"
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attribute \enum_base_type "In1Sel"
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wire width 3 \dec_sub8_in1_sel
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wire width 4 \dec_sub8_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec_sub8_in3_sel
attribute \enum_base_type "OutSel"
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wire width 2 \dec_sub8_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_110 "WHOLE_REG"
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wire width 3 \dec_sub8_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
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attribute \enum_value_100 "WHOLE_REG"
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wire width 3 \dec_sub8_cr_out
attribute \enum_base_type "RC"
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wire width 2 \dec_sub8_rc_sel
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wire width 4 \dec_sub8_ldst_len
attribute \enum_base_type "CryIn"
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wire width 2 \dec_sub8_cry_in
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wire width 1 \dec_sub8_inv_a
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wire width 1 \dec_sub8_inv_out
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wire width 1 \dec_sub8_cry_out
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wire width 1 \dec_sub8_br
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wire width 1 \dec_sub8_sgn_ext
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wire width 1 \dec_sub8_upd
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wire width 1 \dec_sub8_rsrv
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wire width 1 \dec_sub8_is_32b
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wire width 1 \dec_sub8_sgn
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wire width 1 \dec_sub8_lk
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wire width 1 \dec_sub8_sgl_pipe
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub8_asmcode
cell \dec_sub8 \dec_sub8
connect \opcode_in \dec_sub8_opcode_in
connect \sgl_pipe \dec_sub8_sgl_pipe
connect \asmcode \dec_sub8_asmcode
end
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wire width 32 \dec_sub24_opcode_in
attribute \enum_base_type "Function"
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attribute \enum_value_1000000000 "DIV"
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wire width 10 \dec_sub24_function_unit
attribute \enum_base_type "Form"
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wire width 5 \dec_sub24_form
attribute \enum_base_type "InternalOp"
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attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub24_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub24_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub24_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub24_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub24_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub24_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub24_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub24_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub24_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub24_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub24_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub24_asmcode
cell \dec_sub24 \dec_sub24
connect \opcode_in \dec_sub24_opcode_in
connect \sgl_pipe \dec_sub24_sgl_pipe
connect \asmcode \dec_sub24_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 \dec_sub4_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 \dec_sub4_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub4_form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub4_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 \dec_sub4_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 \dec_sub4_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 \dec_sub4_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 \dec_sub4_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 \dec_sub4_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 \dec_sub4_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 \dec_sub4_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub4_ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub4_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec_sub4_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub4_asmcode
cell \dec_sub4 \dec_sub4
connect \opcode_in \dec_sub4_opcode_in
connect \sgl_pipe \dec_sub4_sgl_pipe
connect \asmcode \dec_sub4_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 10 \opcode_switch
process $group_0
assign \opcode_switch 10'0000000000
assign \opcode_switch \opcode_in [10:1]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:261"
wire width 5 \opc_in
process $group_1
assign \opc_in 5'00000
end
process $group_20
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \function_unit \dec_sub10_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \function_unit \dec_sub28_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \function_unit \dec_sub0_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \function_unit \dec_sub26_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \function_unit \dec_sub19_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \function_unit \dec_sub22_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \function_unit \dec_sub9_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \function_unit \dec_sub11_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \function_unit \dec_sub27_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \function_unit \dec_sub15_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \function_unit \dec_sub20_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \function_unit \dec_sub23_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \function_unit \dec_sub21_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \function_unit \dec_sub16_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \function_unit \dec_sub18_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \function_unit \dec_sub8_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \function_unit \dec_sub24_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \function_unit \dec_sub4_function_unit
end
end
process $group_21
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \form \dec_sub10_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \form \dec_sub28_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \form \dec_sub0_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \form \dec_sub26_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \form \dec_sub19_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \form \dec_sub22_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \form \dec_sub9_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \form \dec_sub11_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \form \dec_sub27_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \form \dec_sub15_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \form \dec_sub20_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \form \dec_sub23_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \form \dec_sub21_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \form \dec_sub16_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \form \dec_sub18_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \form \dec_sub8_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \form \dec_sub24_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \form \dec_sub4_form
end
end
process $group_22
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \internal_op \dec_sub10_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \internal_op \dec_sub28_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \internal_op \dec_sub0_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \internal_op \dec_sub26_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \internal_op \dec_sub19_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \internal_op \dec_sub22_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \internal_op \dec_sub9_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \internal_op \dec_sub11_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \internal_op \dec_sub27_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \internal_op \dec_sub15_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \internal_op \dec_sub20_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \internal_op \dec_sub23_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \internal_op \dec_sub21_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \internal_op \dec_sub16_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \internal_op \dec_sub18_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \internal_op \dec_sub8_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \internal_op \dec_sub24_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \internal_op \dec_sub4_internal_op
end
end
process $group_23
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \in1_sel \dec_sub10_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \in1_sel \dec_sub28_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \in1_sel \dec_sub0_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \in1_sel \dec_sub26_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \in1_sel \dec_sub19_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \in1_sel \dec_sub22_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \in1_sel \dec_sub9_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \in1_sel \dec_sub11_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \in1_sel \dec_sub27_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \in1_sel \dec_sub15_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \in1_sel \dec_sub20_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \in1_sel \dec_sub23_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \in1_sel \dec_sub21_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \in1_sel \dec_sub16_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \in1_sel \dec_sub18_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \in1_sel \dec_sub8_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \in1_sel \dec_sub24_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \in1_sel \dec_sub4_in1_sel
end
end
process $group_24
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \in2_sel \dec_sub10_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \in2_sel \dec_sub28_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \in2_sel \dec_sub0_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \in2_sel \dec_sub26_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \in2_sel \dec_sub19_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \in2_sel \dec_sub22_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \in2_sel \dec_sub9_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \in2_sel \dec_sub11_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \in2_sel \dec_sub27_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \in2_sel \dec_sub15_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \in2_sel \dec_sub20_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \in2_sel \dec_sub23_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \in2_sel \dec_sub21_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \in2_sel \dec_sub16_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \in2_sel \dec_sub18_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \in2_sel \dec_sub8_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \in2_sel \dec_sub24_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \in2_sel \dec_sub4_in2_sel
end
end
process $group_25
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \in3_sel \dec_sub10_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \in3_sel \dec_sub28_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \in3_sel \dec_sub0_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \in3_sel \dec_sub26_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \in3_sel \dec_sub19_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \in3_sel \dec_sub22_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \in3_sel \dec_sub9_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \in3_sel \dec_sub11_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \in3_sel \dec_sub27_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \in3_sel \dec_sub15_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \in3_sel \dec_sub20_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \in3_sel \dec_sub23_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \in3_sel \dec_sub21_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \in3_sel \dec_sub16_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \in3_sel \dec_sub18_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \in3_sel \dec_sub8_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \in3_sel \dec_sub24_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \in3_sel \dec_sub4_in3_sel
end
end
process $group_26
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \out_sel \dec_sub10_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \out_sel \dec_sub28_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \out_sel \dec_sub0_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \out_sel \dec_sub26_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \out_sel \dec_sub19_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \out_sel \dec_sub22_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \out_sel \dec_sub9_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \out_sel \dec_sub11_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \out_sel \dec_sub27_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \out_sel \dec_sub15_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \out_sel \dec_sub20_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \out_sel \dec_sub23_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \out_sel \dec_sub21_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \out_sel \dec_sub16_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \out_sel \dec_sub18_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \out_sel \dec_sub8_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \out_sel \dec_sub24_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \out_sel \dec_sub4_out_sel
end
end
process $group_27
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \cr_in \dec_sub10_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \cr_in \dec_sub28_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \cr_in \dec_sub0_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \cr_in \dec_sub26_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \cr_in \dec_sub19_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \cr_in \dec_sub22_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \cr_in \dec_sub9_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \cr_in \dec_sub11_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \cr_in \dec_sub27_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \cr_in \dec_sub15_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \cr_in \dec_sub20_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \cr_in \dec_sub23_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \cr_in \dec_sub21_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \cr_in \dec_sub16_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \cr_in \dec_sub18_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \cr_in \dec_sub8_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \cr_in \dec_sub24_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \cr_in \dec_sub4_cr_in
end
end
process $group_28
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \cr_out \dec_sub10_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \cr_out \dec_sub28_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \cr_out \dec_sub0_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \cr_out \dec_sub26_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \cr_out \dec_sub19_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \cr_out \dec_sub22_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \cr_out \dec_sub9_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \cr_out \dec_sub11_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \cr_out \dec_sub27_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \cr_out \dec_sub15_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \cr_out \dec_sub20_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \cr_out \dec_sub23_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \cr_out \dec_sub21_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \cr_out \dec_sub16_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \cr_out \dec_sub18_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \cr_out \dec_sub8_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \cr_out \dec_sub24_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \cr_out \dec_sub4_cr_out
end
end
process $group_29
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \rc_sel \dec_sub10_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \rc_sel \dec_sub28_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \rc_sel \dec_sub0_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \rc_sel \dec_sub26_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \rc_sel \dec_sub19_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \rc_sel \dec_sub22_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \rc_sel \dec_sub9_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \rc_sel \dec_sub11_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \rc_sel \dec_sub27_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \rc_sel \dec_sub15_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \rc_sel \dec_sub20_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \rc_sel \dec_sub23_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \rc_sel \dec_sub21_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \rc_sel \dec_sub16_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \rc_sel \dec_sub18_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \rc_sel \dec_sub8_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \rc_sel \dec_sub24_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \rc_sel \dec_sub4_rc_sel
end
end
process $group_30
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \ldst_len \dec_sub10_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \ldst_len \dec_sub28_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \ldst_len \dec_sub0_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \ldst_len \dec_sub26_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \ldst_len \dec_sub19_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \ldst_len \dec_sub22_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \ldst_len \dec_sub9_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \ldst_len \dec_sub11_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \ldst_len \dec_sub27_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \ldst_len \dec_sub15_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \ldst_len \dec_sub20_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \ldst_len \dec_sub23_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \ldst_len \dec_sub21_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \ldst_len \dec_sub16_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \ldst_len \dec_sub18_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \ldst_len \dec_sub8_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \ldst_len \dec_sub24_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \ldst_len \dec_sub4_ldst_len
end
end
process $group_31
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \cry_in \dec_sub10_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \cry_in \dec_sub28_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \cry_in \dec_sub0_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \cry_in \dec_sub26_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \cry_in \dec_sub19_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \cry_in \dec_sub22_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \cry_in \dec_sub9_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \cry_in \dec_sub11_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \cry_in \dec_sub27_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \cry_in \dec_sub15_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \cry_in \dec_sub20_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \cry_in \dec_sub23_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \cry_in \dec_sub21_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \cry_in \dec_sub16_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \cry_in \dec_sub18_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \cry_in \dec_sub8_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \cry_in \dec_sub24_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \cry_in \dec_sub4_cry_in
end
end
process $group_32
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \inv_a \dec_sub10_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \inv_a \dec_sub28_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \inv_a \dec_sub0_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \inv_a \dec_sub26_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \inv_a \dec_sub19_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \inv_a \dec_sub22_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \inv_a \dec_sub9_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \inv_a \dec_sub11_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \inv_a \dec_sub27_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \inv_a \dec_sub15_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \inv_a \dec_sub20_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \inv_a \dec_sub23_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \inv_a \dec_sub21_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \inv_a \dec_sub16_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \inv_a \dec_sub18_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \inv_a \dec_sub8_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \inv_a \dec_sub24_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \inv_a \dec_sub4_inv_a
end
end
process $group_33
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \inv_out \dec_sub10_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \inv_out \dec_sub28_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \inv_out \dec_sub0_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \inv_out \dec_sub26_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \inv_out \dec_sub19_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \inv_out \dec_sub22_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \inv_out \dec_sub9_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \inv_out \dec_sub11_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \inv_out \dec_sub27_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \inv_out \dec_sub15_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \inv_out \dec_sub20_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \inv_out \dec_sub23_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \inv_out \dec_sub21_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \inv_out \dec_sub16_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \inv_out \dec_sub18_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \inv_out \dec_sub8_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \inv_out \dec_sub24_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \inv_out \dec_sub4_inv_out
end
end
process $group_34
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \cry_out \dec_sub10_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \cry_out \dec_sub28_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \cry_out \dec_sub0_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \cry_out \dec_sub26_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \cry_out \dec_sub19_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \cry_out \dec_sub22_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \cry_out \dec_sub9_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \cry_out \dec_sub11_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \cry_out \dec_sub27_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \cry_out \dec_sub15_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \cry_out \dec_sub20_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \cry_out \dec_sub23_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \cry_out \dec_sub21_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \cry_out \dec_sub16_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \cry_out \dec_sub18_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \cry_out \dec_sub8_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \cry_out \dec_sub24_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \cry_out \dec_sub4_cry_out
end
end
process $group_35
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \br \dec_sub10_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \br \dec_sub28_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \br \dec_sub0_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \br \dec_sub26_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \br \dec_sub19_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \br \dec_sub22_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \br \dec_sub9_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \br \dec_sub11_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \br \dec_sub27_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \br \dec_sub15_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \br \dec_sub20_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \br \dec_sub23_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \br \dec_sub21_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \br \dec_sub16_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \br \dec_sub18_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \br \dec_sub8_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \br \dec_sub24_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \br \dec_sub4_br
end
end
process $group_36
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \sgn_ext \dec_sub10_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \sgn_ext \dec_sub28_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \sgn_ext \dec_sub0_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \sgn_ext \dec_sub26_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \sgn_ext \dec_sub19_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \sgn_ext \dec_sub22_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \sgn_ext \dec_sub9_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \sgn_ext \dec_sub11_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \sgn_ext \dec_sub27_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \sgn_ext \dec_sub15_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \sgn_ext \dec_sub20_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \sgn_ext \dec_sub23_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \sgn_ext \dec_sub21_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \sgn_ext \dec_sub16_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \sgn_ext \dec_sub18_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \sgn_ext \dec_sub8_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \sgn_ext \dec_sub24_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \sgn_ext \dec_sub4_sgn_ext
end
end
process $group_37
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \upd \dec_sub10_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \upd \dec_sub28_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \upd \dec_sub0_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \upd \dec_sub26_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \upd \dec_sub19_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \upd \dec_sub22_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \upd \dec_sub9_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \upd \dec_sub11_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \upd \dec_sub27_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \upd \dec_sub15_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \upd \dec_sub20_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \upd \dec_sub23_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \upd \dec_sub21_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \upd \dec_sub16_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \upd \dec_sub18_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \upd \dec_sub8_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \upd \dec_sub24_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \upd \dec_sub4_upd
end
end
process $group_38
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \rsrv \dec_sub10_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \rsrv \dec_sub28_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \rsrv \dec_sub0_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \rsrv \dec_sub26_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \rsrv \dec_sub19_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \rsrv \dec_sub22_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \rsrv \dec_sub9_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \rsrv \dec_sub11_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \rsrv \dec_sub27_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \rsrv \dec_sub15_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \rsrv \dec_sub20_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \rsrv \dec_sub23_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \rsrv \dec_sub21_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \rsrv \dec_sub16_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \rsrv \dec_sub18_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \rsrv \dec_sub8_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \rsrv \dec_sub24_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \rsrv \dec_sub4_rsrv
end
end
process $group_39
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \is_32b \dec_sub10_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \is_32b \dec_sub28_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \is_32b \dec_sub0_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \is_32b \dec_sub26_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \is_32b \dec_sub19_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \is_32b \dec_sub22_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \is_32b \dec_sub9_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \is_32b \dec_sub11_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \is_32b \dec_sub27_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \is_32b \dec_sub15_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \is_32b \dec_sub20_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \is_32b \dec_sub23_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \is_32b \dec_sub21_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \is_32b \dec_sub16_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \is_32b \dec_sub18_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \is_32b \dec_sub8_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \is_32b \dec_sub24_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \is_32b \dec_sub4_is_32b
end
end
process $group_40
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \sgn \dec_sub10_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \sgn \dec_sub28_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \sgn \dec_sub0_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \sgn \dec_sub26_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \sgn \dec_sub19_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \sgn \dec_sub22_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \sgn \dec_sub9_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \sgn \dec_sub11_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \sgn \dec_sub27_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \sgn \dec_sub15_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \sgn \dec_sub20_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \sgn \dec_sub23_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \sgn \dec_sub21_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \sgn \dec_sub16_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \sgn \dec_sub18_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \sgn \dec_sub8_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \sgn \dec_sub24_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \sgn \dec_sub4_sgn
end
end
process $group_41
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \lk \dec_sub10_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \lk \dec_sub28_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \lk \dec_sub0_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \lk \dec_sub26_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \lk \dec_sub19_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \lk \dec_sub22_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \lk \dec_sub9_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \lk \dec_sub11_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \lk \dec_sub27_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \lk \dec_sub15_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \lk \dec_sub20_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \lk \dec_sub23_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \lk \dec_sub21_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \lk \dec_sub16_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \lk \dec_sub18_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \lk \dec_sub8_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \lk \dec_sub24_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \lk \dec_sub4_lk
end
end
process $group_42
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \sgl_pipe \dec_sub10_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \sgl_pipe \dec_sub28_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \sgl_pipe \dec_sub0_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \sgl_pipe \dec_sub26_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \sgl_pipe \dec_sub19_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \sgl_pipe \dec_sub22_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \sgl_pipe \dec_sub9_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \sgl_pipe \dec_sub11_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \sgl_pipe \dec_sub27_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \sgl_pipe \dec_sub15_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \sgl_pipe \dec_sub20_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \sgl_pipe \dec_sub23_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \sgl_pipe \dec_sub21_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \sgl_pipe \dec_sub16_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \sgl_pipe \dec_sub18_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \sgl_pipe \dec_sub8_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \sgl_pipe \dec_sub24_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \sgl_pipe \dec_sub4_sgl_pipe
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \asmcode$1
process $group_43
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
switch \opc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01010
assign \asmcode \dec_sub10_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11100
assign \asmcode \dec_sub28_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00000
assign \asmcode \dec_sub0_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11010
assign \asmcode \dec_sub26_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10011
assign \asmcode \dec_sub19_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10110
assign \asmcode \dec_sub22_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01001
assign \asmcode \dec_sub9_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01011
assign \asmcode \dec_sub11_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11011
assign \asmcode \dec_sub27_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01111
assign \asmcode \dec_sub15_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10100
assign \asmcode \dec_sub20_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10111
assign \asmcode \dec_sub23_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10101
assign \asmcode \dec_sub21_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10000
assign \asmcode \dec_sub16_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'10010
assign \asmcode \asmcode$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'01000
assign \asmcode \dec_sub8_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'11000
assign \asmcode \dec_sub24_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
case 5'00100
assign \asmcode \dec_sub4_asmcode
end
connect \asmcode$1 8'00000000
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec58"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec58"
module \dec58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 2 \opcode_switch
process $group_0
assign \opcode_switch 2'00
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \function_unit 10'0000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \form 5'00101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \form 5'00101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \form 5'00101
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \internal_op 7'0100101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in2_sel 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in2_sel 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \in2_sel 4'1000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \ldst_len 4'0100
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \asmcode 8'01010001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \asmcode 8'01010100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \asmcode 8'01100001
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \sgn_ext 1'1
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \upd 1'0
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'10
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec.dec62"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec62"
module \dec62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 1 \function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 4 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 5 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 6 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 7 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 12 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 15 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 20 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 2 \opcode_switch
process $group_0
assign \opcode_switch 2'00
end
process $group_1
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \function_unit 10'0000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \form 5'00101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \form 5'00101
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in2_sel 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in2_sel 4'1000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \ldst_len 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \ldst_len 4'1000
end
end
process $group_11
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \rc_sel 2'00
end
end
process $group_12
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cry_in 2'00
end
end
process $group_13
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \asmcode 8'10100111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \asmcode 8'10101010
end
end
process $group_14
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \inv_a 1'0
end
end
process $group_15
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \inv_out 1'0
end
end
process $group_16
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \cry_out 1'0
end
end
process $group_17
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \br 1'0
end
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgn_ext 1'0
end
end
process $group_19
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \upd 1'1
end
end
process $group_20
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'00
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 2'01
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec"
module \dec
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:319"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
wire width 1 input 0 \bigendian
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
wire width 32 input 1 \raw_opcode_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
wire width 32 output 2 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
wire width 3 output 3 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
wire width 4 output 4 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
wire width 2 output 5 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
wire width 2 output 6 \out_sel
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
wire width 2 output 7 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
wire width 3 output 8 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
wire width 10 output 10 \function_unit
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 11 \internal_op
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 12 \ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 13 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 14 \inv_out
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 15 \cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 16 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 17 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 18 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 19 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 1 output 20 \LK
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 21 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 22 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 23 \upd
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 24 \form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 25 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 output 26 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 27 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 output 28 \RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 output 29 \RT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 output 30 \RA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 output 31 \RB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 16 output 32 \SI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 16 output 33 \UI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 output 34 \SH32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 6 output 35 \sh
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wire width 1 output 37 \Rc
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wire width 1 output 38 \OE
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wire width 14 output 39 \BD
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wire width 5 output 40 \BB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 output 41 \BA
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wire width 5 output 42 \BT
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wire width 5 output 43 \BO
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wire width 14 output 45 \DS
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wire width 5 output 46 \BC
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wire width 10 output 47 \SPR
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wire width 3 output 49 \X_BFA
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wire width 32 \dec19_opcode_in
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wire width 10 \dec19_function_unit
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attribute \enum_value_11100 "Z23"
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wire width 5 \dec19_form
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wire width 3 \dec19_in1_sel
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wire width 4 \dec19_in2_sel
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attribute \enum_value_00 "NONE"
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wire width 2 \dec19_in3_sel
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wire width 3 \dec19_cr_in
attribute \enum_base_type "CROutSel"
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wire width 3 \dec19_cr_out
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wire width 4 \dec19_ldst_len
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wire width 2 \dec19_cry_in
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wire width 8 \dec19_asmcode
cell \dec19 \dec19
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end
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wire width 10 \dec30_function_unit
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wire width 3 \dec30_cr_out
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wire width 4 \dec30_ldst_len
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wire width 2 \dec30_cry_in
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wire width 1 \dec30_inv_out
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wire width 1 \dec30_rsrv
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wire width 1 \dec30_is_32b
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wire width 1 \dec30_sgn
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wire width 1 \dec30_lk
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wire width 1 \dec30_sgl_pipe
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wire width 8 \dec30_asmcode
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connect \asmcode \dec30_asmcode
end
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wire width 32 \dec31_opcode_in
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wire width 10 \dec31_function_unit
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wire width 5 \dec31_form
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wire width 3 \dec31_in1_sel
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wire width 4 \dec31_in2_sel
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wire width 2 \dec31_in3_sel
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end
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 \dec62_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec62_asmcode
cell \dec62 \dec62
connect \opcode_in \dec62_opcode_in
connect \sgl_pipe \dec62_sgl_pipe
connect \asmcode \dec62_asmcode
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 6 \opcode_switch
process $group_0
assign \opcode_switch 6'000000
assign \dec62_opcode_in \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
wire width 32 \opcode_switch$1
process $group_6
assign \function_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \function_unit \dec19_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \function_unit \dec30_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \function_unit \dec31_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \function_unit \dec58_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \function_unit \dec62_function_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \function_unit 10'0010000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \function_unit 10'0000100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \function_unit 10'0000100000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \function_unit 10'0100000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \function_unit 10'0000001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \function_unit 10'0000000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \function_unit 10'0010000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \function_unit 10'0010000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \function_unit 10'0000010000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \function_unit 10'0000010000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \function_unit 10'0000000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \function_unit 10'0000000010
end
end
process $group_7
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \form \dec19_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \form \dec30_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \form \dec31_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \form \dec58_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \form \dec62_form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \form 5'00011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \form 5'00010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \form 5'00010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \form 5'00001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \form 5'00010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \form 5'10011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \form 5'10011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \form 5'10011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \form 5'00100
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \form 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \form 5'00100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \form 5'00000
end
end
process $group_8
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \internal_op \dec19_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \internal_op \dec30_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \internal_op \dec31_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \internal_op \dec58_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \internal_op \dec62_internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \internal_op 7'1001001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \internal_op 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \internal_op 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \internal_op 7'0000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \internal_op 7'0000111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \internal_op 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \internal_op 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \internal_op 7'0100101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \internal_op 7'0110010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \internal_op 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \internal_op 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \internal_op 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \internal_op 7'0100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \internal_op 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \internal_op 7'0111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \internal_op 7'0111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \internal_op 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \internal_op 7'1000011
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \internal_op 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \internal_op 7'0000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \internal_op 7'1000100
end
end
process $group_9
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \in1_sel \dec19_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \in1_sel \dec30_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \in1_sel \dec31_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \in1_sel \dec58_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \in1_sel \dec62_in1_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \in1_sel 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \in1_sel 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \in1_sel 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \in1_sel 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \in1_sel 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \in1_sel 3'100
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \in1_sel 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \in1_sel 3'000
end
end
process $group_10
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \in2_sel \dec19_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \in2_sel \dec30_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \in2_sel \dec31_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \in2_sel \dec58_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \in2_sel \dec62_in2_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \in2_sel 4'0101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \in2_sel 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \in2_sel 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \in2_sel 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \in2_sel 4'0110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \in2_sel 4'0111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \in2_sel 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \in2_sel 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \in2_sel 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \in2_sel 4'1011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \in2_sel 4'1011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \in2_sel 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \in2_sel 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \in2_sel 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \in2_sel 4'0100
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \in2_sel 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \in2_sel 4'0000
end
end
process $group_11
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \in3_sel \dec19_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \in3_sel \dec30_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \in3_sel \dec31_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \in3_sel \dec58_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \in3_sel \dec62_in3_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \in3_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \in3_sel 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \in3_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \in3_sel 2'00
end
end
process $group_12
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \out_sel \dec19_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \out_sel \dec30_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \out_sel \dec31_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \out_sel \dec58_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \out_sel \dec62_out_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \out_sel 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \out_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \out_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \out_sel 2'10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \out_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \out_sel 2'01
end
end
process $group_13
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \cr_in \dec19_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \cr_in \dec30_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \cr_in \dec31_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \cr_in \dec58_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \cr_in \dec62_cr_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \cr_in 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \cr_in 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \cr_in 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \cr_in 3'000
end
end
process $group_14
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \cr_out \dec19_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \cr_out \dec30_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \cr_out \dec31_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \cr_out \dec58_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \cr_out \dec62_cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \cr_out 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \cr_out 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \cr_out 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \cr_out 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \cr_out 3'000
end
end
process $group_15
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \rc_sel \dec19_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \rc_sel \dec30_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \rc_sel \dec31_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \rc_sel \dec58_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \rc_sel \dec62_rc_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \rc_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \rc_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \rc_sel 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \rc_sel 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \rc_sel 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \rc_sel 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \rc_sel 2'00
end
end
process $group_16
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \ldst_len \dec19_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \ldst_len \dec30_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \ldst_len \dec31_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \ldst_len \dec58_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \ldst_len \dec62_ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \ldst_len 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \ldst_len 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \ldst_len 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \ldst_len 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \ldst_len 4'0000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \ldst_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \ldst_len 4'0000
end
end
process $group_17
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \cry_in \dec19_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \cry_in \dec30_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \cry_in \dec31_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \cry_in \dec58_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \cry_in \dec62_cry_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \cry_in 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \cry_in 2'00
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \cry_in 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \cry_in 2'00
end
end
process $group_18
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \inv_a \dec19_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \inv_a \dec30_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \inv_a \dec31_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \inv_a \dec58_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \inv_a \dec62_inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \inv_a 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \inv_a 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \inv_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \inv_a 1'0
end
end
process $group_19
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \inv_out \dec19_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \inv_out \dec30_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \inv_out \dec31_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \inv_out \dec58_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \inv_out \dec62_inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \inv_out 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \inv_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \inv_out 1'0
end
end
process $group_20
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \cry_out \dec19_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \cry_out \dec30_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \cry_out \dec31_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \cry_out \dec58_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \cry_out \dec62_cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \cry_out 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \cry_out 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \cry_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \cry_out 1'0
end
end
process $group_21
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \br \dec19_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \br \dec30_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \br \dec31_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \br \dec58_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \br \dec62_br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \br 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \br 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \br 1'0
end
end
process $group_22
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \sgn_ext \dec19_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \sgn_ext \dec30_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \sgn_ext \dec31_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \sgn_ext \dec58_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \sgn_ext \dec62_sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \sgn_ext 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \sgn_ext 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \sgn_ext 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \sgn_ext 1'0
end
end
process $group_23
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \upd \dec19_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \upd \dec30_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \upd \dec31_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \upd \dec58_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \upd \dec62_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \upd 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \upd 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \upd 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \upd 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \upd 1'0
end
end
process $group_24
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \rsrv \dec19_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \rsrv \dec30_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \rsrv \dec31_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \rsrv \dec58_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \rsrv \dec62_rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \rsrv 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \rsrv 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \rsrv 1'0
end
end
process $group_25
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \is_32b \dec19_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \is_32b \dec30_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \is_32b \dec31_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \is_32b \dec58_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \is_32b \dec62_is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \is_32b 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \is_32b 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \is_32b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \is_32b 1'0
end
end
process $group_26
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \sgn \dec19_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \sgn \dec30_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \sgn \dec31_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \sgn \dec58_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \sgn \dec62_sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \sgn 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \sgn 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \sgn 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \sgn 1'0
end
end
process $group_27
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \lk \dec19_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \lk \dec30_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \lk \dec31_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \lk \dec58_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \lk \dec62_lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \lk 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \lk 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \lk 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \lk 1'0
end
end
process $group_28
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \sgl_pipe \dec19_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \sgl_pipe \dec30_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \sgl_pipe \dec31_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \sgl_pipe \dec58_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \sgl_pipe \dec62_sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \sgl_pipe 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \sgl_pipe 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \sgl_pipe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \sgl_pipe 1'1
end
end
process $group_29
assign \asmcode 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'010011
assign \asmcode \dec19_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011110
assign \asmcode \dec30_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'011111
assign \asmcode \dec31_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111010
assign \asmcode \dec58_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
case 6'111110
assign \asmcode \dec62_asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001100
assign \asmcode 8'00000111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001101
assign \asmcode 8'00001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001110
assign \asmcode 8'00000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001111
assign \asmcode 8'00001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ case 6'010001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011100
assign \asmcode 8'00010001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011101
assign \asmcode 8'00010010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010010
assign \asmcode 8'00010100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010000
assign \asmcode 8'00010101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001011
assign \asmcode 8'00011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001010
assign \asmcode 8'00011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100010
assign \asmcode 8'01001101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100011
assign \asmcode 8'01001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101010
assign \asmcode 8'01010111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101011
assign \asmcode 8'01011001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101000
assign \asmcode 8'01011101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101001
assign \asmcode 8'01011110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100000
assign \asmcode 8'01100110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100001
assign \asmcode 8'01100111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000111
assign \asmcode 8'01111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011000
assign \asmcode 8'10000111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011001
assign \asmcode 8'10001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010100
assign \asmcode 8'10010101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010101
assign \asmcode 8'10010110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'010111
assign \asmcode 8'10010111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100110
assign \asmcode 8'10100010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100111
assign \asmcode 8'10100100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101100
assign \asmcode 8'10101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'101101
assign \asmcode 8'10110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100100
assign \asmcode 8'10110011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'100101
assign \asmcode 8'10110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'001000
assign \asmcode 8'10111110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000010
assign \asmcode 8'11000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'000011
assign \asmcode 8'11001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011010
assign \asmcode 8'11001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 6'011011
assign \asmcode 8'11001011
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
switch \opcode_switch$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000000---------------0100000000-
assign \asmcode 8'00010011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'01100000000000000000000000000000
assign \asmcode 8'10000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
case 32'000001---------------0000000011-
assign \asmcode 8'10011001
end
assign \opcode_switch$1 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350"
wire width 32 $2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350"
cell $mux $3
parameter \WIDTH 32
connect \A { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 1 \L
process $group_38
assign \L 1'0
assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \MB32
process $group_41
assign \MB32 5'00000
assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \ME32
process $group_42
assign \ME32 5'00000
assign \LK { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 1 \AA
process $group_45
assign \AA 1'0
assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 3 \BF
process $group_49
assign \BF 3'000
assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 10 \CR
process $group_50
assign \CR 10'0000000000
assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 8 \FXM
process $group_54
assign \FXM 8'00000000
assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 2 \BH
process $group_57
assign \BH 2'00
assign \BH { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 16 \D
process $group_58
assign \D 16'0000000000000000
assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \TO
process $group_60
assign \TO 5'00000
assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \SH
process $group_62
assign \SH 5'00000
assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \ME
process $group_63
assign \ME 5'00000
assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 \MB
process $group_64
assign \MB 5'00000
assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_A
process $group_66
assign \X_A 1'0
assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_BO
process $group_69
assign \X_BO 5'00000
assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \X_CT
process $group_70
assign \X_CT 4'0000
assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 7 \X_DCMX
process $group_71
assign \X_DCMX 7'0000000
assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \X_DRM
process $group_72
assign \X_DRM 3'000
assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_E
process $group_73
assign \X_E 1'0
assign \X_E { \opcode_in [15] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \X_E_1
process $group_74
assign \X_E_1 4'0000
assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_EO
process $group_75
assign \X_EO 2'00
assign \X_EO { \opcode_in [20] \opcode_in [19] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_EO_1
process $group_76
assign \X_EO_1 5'00000
assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_EX
process $group_77
assign \X_EX 1'0
assign \X_EX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FC
process $group_78
assign \X_FC 5'00000
assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRA
process $group_79
assign \X_FRA 5'00000
assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRAp
process $group_80
assign \X_FRAp 5'00000
assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRB
process $group_81
assign \X_FRB 5'00000
assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRBp
process $group_82
assign \X_FRBp 5'00000
assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRS
process $group_83
assign \X_FRS 5'00000
assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRSp
process $group_84
assign \X_FRSp 5'00000
assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRT
process $group_85
assign \X_FRT 5'00000
assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_FRTp
process $group_86
assign \X_FRTp 5'00000
assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \X_IH
process $group_87
assign \X_IH 3'000
assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \X_IMM8
process $group_88
assign \X_IMM8 8'00000000
assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_L
process $group_89
assign \X_L 2'00
assign \X_L { \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_L_1
process $group_90
assign \X_L_1 1'0
assign \X_L_1 { \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_L_2
process $group_91
assign \X_L_2 1'0
assign \X_L_2 { \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_L_3
process $group_92
assign \X_L_3 2'00
assign \X_L_3 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_MO
process $group_93
assign \X_MO 5'00000
assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_NB
process $group_94
assign \X_NB 5'00000
assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_PRS
process $group_95
assign \X_PRS 1'0
assign \X_PRS { \opcode_in [17] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_R
process $group_96
assign \X_R 1'0
assign \X_R { \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_R_1
process $group_97
assign \X_R_1 1'0
assign \X_R_1 { \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RA
process $group_98
assign \X_RA 5'00000
assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RB
process $group_99
assign \X_RB 5'00000
assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_Rc
process $group_100
assign \X_Rc 1'0
assign \X_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_RIC
process $group_101
assign \X_RIC 2'00
assign \X_RIC { \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_RM
process $group_102
assign \X_RM 2'00
assign \X_RM { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_RO
process $group_103
assign \X_RO 1'0
assign \X_RO { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RS
process $group_104
assign \X_RS 5'00000
assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RSp
process $group_105
assign \X_RSp 5'00000
assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RT
process $group_106
assign \X_RT 5'00000
assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_RTp
process $group_107
assign \X_RTp 5'00000
assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_S
process $group_108
assign \X_S 5'00000
assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_SH
process $group_109
assign \X_SH 5'00000
assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_SI
process $group_110
assign \X_SI 5'00000
assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_SP
process $group_111
assign \X_SP 2'00
assign \X_SP { \opcode_in [20] \opcode_in [19] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \X_SR
process $group_112
assign \X_SR 4'0000
assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_SX
process $group_113
assign \X_SX 1'0
assign \X_SX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \X_SX_S
process $group_114
assign \X_SX_S 6'000000
assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_T
process $group_115
assign \X_T 5'00000
assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \X_TBR
process $group_116
assign \X_TBR 10'0000000000
assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_TH
process $group_117
assign \X_TH 5'00000
assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_TO
process $group_118
assign \X_TO 5'00000
assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_TX
process $group_119
assign \X_TX 1'0
assign \X_TX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \X_TX_T
process $group_120
assign \X_TX_T 6'000000
assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \X_U
process $group_121
assign \X_U 4'0000
assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_UIM
process $group_122
assign \X_UIM 5'00000
assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_VRS
process $group_123
assign \X_VRS 5'00000
assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \X_VRT
process $group_124
assign \X_VRT 5'00000
assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \X_W
process $group_125
assign \X_W 1'0
assign \X_W { \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \X_WC
process $group_126
assign \X_WC 2'00
assign \X_WC { \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \X_XO
process $group_127
assign \X_XO 10'0000000000
assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \X_XO_1
process $group_128
assign \X_XO_1 8'00000000
assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \B_AA
process $group_129
assign \B_AA 1'0
assign \B_AA { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 14 \B_BD
process $group_130
assign \B_BD 14'00000000000000
assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \B_BI
process $group_131
assign \B_BI 5'00000
assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \B_BO
process $group_132
assign \B_BO 5'00000
assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \B_LK
process $group_133
assign \B_LK 1'0
assign \B_LK { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \I_AA
process $group_134
assign \I_AA 1'0
assign \I_AA { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 24 \I_LI
process $group_135
assign \I_LI 24'000000000000000000000000
assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \I_LK
process $group_136
assign \I_LK 1'0
assign \I_LK { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX3_AX
process $group_137
assign \XX3_AX 1'0
assign \XX3_AX { \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX3_A
process $group_138
assign \XX3_A 5'00000
assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX3_AX_A
process $group_139
assign \XX3_AX_A 6'000000
assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \XX3_BF
process $group_140
assign \XX3_BF 3'000
assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX3_BX
process $group_141
assign \XX3_BX 1'0
assign \XX3_BX { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX3_B
process $group_142
assign \XX3_B 5'00000
assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX3_BX_B
process $group_143
assign \XX3_BX_B 6'000000
assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \XX3_DM
process $group_144
assign \XX3_DM 2'00
assign \XX3_DM { \opcode_in [9] \opcode_in [8] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX3_Rc
process $group_145
assign \XX3_Rc 1'0
assign \XX3_Rc { \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \XX3_SHW
process $group_146
assign \XX3_SHW 2'00
assign \XX3_SHW { \opcode_in [9] \opcode_in [8] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX3_TX
process $group_147
assign \XX3_TX 1'0
assign \XX3_TX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX3_T
process $group_148
assign \XX3_T 5'00000
assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX3_TX_T
process $group_149
assign \XX3_TX_T 6'000000
assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \XX3_XO
process $group_150
assign \XX3_XO 4'0000
assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \XX3_XO_1
process $group_151
assign \XX3_XO_1 8'00000000
assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 9 \XX3_XO_2
process $group_152
assign \XX3_XO_2 9'000000000
assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX4_AX
process $group_153
assign \XX4_AX 1'0
assign \XX4_AX { \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX4_A
process $group_154
assign \XX4_A 5'00000
assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX4_AX_A
process $group_155
assign \XX4_AX_A 6'000000
assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX4_BX
process $group_156
assign \XX4_BX 1'0
assign \XX4_BX { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX4_B
process $group_157
assign \XX4_B 5'00000
assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX4_BX_B
process $group_158
assign \XX4_BX_B 6'000000
assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX4_CX
process $group_159
assign \XX4_CX 1'0
assign \XX4_CX { \opcode_in [3] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX4_C
process $group_160
assign \XX4_C 5'00000
assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX4_CX_C
process $group_161
assign \XX4_CX_C 6'000000
assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX4_TX
process $group_162
assign \XX4_TX 1'0
assign \XX4_TX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX4_T
process $group_163
assign \XX4_T 5'00000
assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX4_TX_T
process $group_164
assign \XX4_TX_T 6'000000
assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \XX4_XO
process $group_165
assign \XX4_XO 2'00
assign \XX4_XO { \opcode_in [5] \opcode_in [4] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XL_BA
process $group_166
assign \XL_BA 5'00000
assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XL_BB
process $group_167
assign \XL_BB 5'00000
assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \XL_BF
process $group_168
assign \XL_BF 3'000
assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \XL_BFA
process $group_169
assign \XL_BFA 3'000
assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \XL_BH
process $group_170
assign \XL_BH 2'00
assign \XL_BH { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XL_BI
process $group_171
assign \XL_BI 5'00000
assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XL_BO
process $group_172
assign \XL_BO 5'00000
assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XL_BO_1
process $group_173
assign \XL_BO_1 5'00000
assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XL_LK
process $group_175
assign \XL_LK 1'0
assign \XL_LK { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 15 \XL_OC
process $group_176
assign \XL_OC 15'000000000000000
assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XL_S
process $group_177
assign \XL_S 1'0
assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_BC
process $group_179
assign \A_BC 5'00000
assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_FRA
process $group_180
assign \A_FRA 5'00000
assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_FRB
process $group_181
assign \A_FRB 5'00000
assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_FRC
process $group_182
assign \A_FRC 5'00000
assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_FRT
process $group_183
assign \A_FRT 5'00000
assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_RA
process $group_184
assign \A_RA 5'00000
assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_RB
process $group_185
assign \A_RB 5'00000
assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \A_Rc
process $group_186
assign \A_Rc 1'0
assign \A_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_RT
process $group_187
assign \A_RT 5'00000
assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \A_XO
process $group_188
assign \A_XO 5'00000
assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \D_BF
process $group_189
assign \D_BF 3'000
assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 16 \D_D
process $group_190
assign \D_D 16'0000000000000000
assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \D_FRS
process $group_191
assign \D_FRS 5'00000
assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \D_FRT
process $group_192
assign \D_FRT 5'00000
assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \D_L
process $group_193
assign \D_L 1'0
assign \D_L { \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \D_RA
process $group_194
assign \D_RA 5'00000
assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \D_RS
process $group_195
assign \D_RS 5'00000
assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \D_RT
process $group_196
assign \D_RT 5'00000
assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 16 \D_SI
process $group_197
assign \D_SI 16'0000000000000000
assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
- wire width 16 \D_UI
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ wire width 5 \D_TO
process $group_198
+ assign \D_TO 5'00000
+ assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ wire width 16 \D_UI
+ process $group_199
assign \D_UI 16'0000000000000000
assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \XX2_BF
- process $group_199
+ process $group_200
assign \XX2_BF 3'000
assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX2_BX
- process $group_200
+ process $group_201
assign \XX2_BX 1'0
assign \XX2_BX { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX2_B
- process $group_201
+ process $group_202
assign \XX2_B 5'00000
assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX2_BX_B
- process $group_202
+ process $group_203
assign \XX2_BX_B 6'000000
assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX2_dc
- process $group_203
+ process $group_204
assign \XX2_dc 1'0
assign \XX2_dc { \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX2_dm
- process $group_204
+ process $group_205
assign \XX2_dm 1'0
assign \XX2_dm { \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX2_dx
- process $group_205
+ process $group_206
assign \XX2_dx 5'00000
assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 7 \XX2_dc_dm_dx
- process $group_206
+ process $group_207
assign \XX2_dc_dm_dx 7'0000000
assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 7 \XX2_DCMX
- process $group_207
+ process $group_208
assign \XX2_DCMX 7'0000000
assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX2_EO
- process $group_208
+ process $group_209
assign \XX2_EO 5'00000
assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX2_RT
- process $group_209
+ process $group_210
assign \XX2_RT 5'00000
assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XX2_TX
- process $group_210
+ process $group_211
assign \XX2_TX 1'0
assign \XX2_TX { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XX2_T
- process $group_211
+ process $group_212
assign \XX2_T 5'00000
assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XX2_TX_T
- process $group_212
+ process $group_213
assign \XX2_TX_T 6'000000
assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \XX2_UIM
- process $group_213
+ process $group_214
assign \XX2_UIM 4'0000
assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \XX2_UIM_1
- process $group_214
+ process $group_215
assign \XX2_UIM_1 2'00
assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 7 \XX2_XO
- process $group_215
+ process $group_216
assign \XX2_XO 7'0000000
assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 9 \XX2_XO_1
- process $group_216
+ process $group_217
assign \XX2_XO_1 9'000000000
assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \Z22_BF
- process $group_217
+ process $group_218
assign \Z22_BF 3'000
assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \Z22_DCM
- process $group_218
+ process $group_219
assign \Z22_DCM 6'000000
assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \Z22_DGM
- process $group_219
+ process $group_220
assign \Z22_DGM 6'000000
assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z22_FRA
- process $group_220
+ process $group_221
assign \Z22_FRA 5'00000
assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z22_FRAp
- process $group_221
+ process $group_222
assign \Z22_FRAp 5'00000
assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z22_FRT
- process $group_222
+ process $group_223
assign \Z22_FRT 5'00000
assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z22_FRTp
- process $group_223
+ process $group_224
assign \Z22_FRTp 5'00000
assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \Z22_Rc
- process $group_224
+ process $group_225
assign \Z22_Rc 1'0
assign \Z22_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \Z22_SH
- process $group_225
+ process $group_226
assign \Z22_SH 6'000000
assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 9 \Z22_XO
- process $group_226
+ process $group_227
assign \Z22_XO 9'000000000
assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \EVS_BFA
- process $group_227
+ process $group_228
assign \EVS_BFA 3'000
assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \XFX_BHRBE
- process $group_228
+ process $group_229
assign \XFX_BHRBE 10'0000000000
assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XFX_DUI
- process $group_229
+ process $group_230
assign \XFX_DUI 5'00000
assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \XFX_DUIS
- process $group_230
+ process $group_231
assign \XFX_DUIS 10'0000000000
assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \XFX_FXM
- process $group_231
+ process $group_232
assign \XFX_FXM 8'00000000
assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XFX_RS
- process $group_232
+ process $group_233
assign \XFX_RS 5'00000
assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XFX_RT
- process $group_233
+ process $group_234
assign \XFX_RT 5'00000
assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \XFX_SPR
- process $group_234
+ process $group_235
assign \XFX_SPR 10'0000000000
assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \XFX_XO
- process $group_235
+ process $group_236
assign \XFX_XO 10'0000000000
assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \DX_d0
- process $group_236
+ process $group_237
assign \DX_d0 10'0000000000
assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DX_d1
- process $group_237
+ process $group_238
assign \DX_d1 5'00000
assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \DX_d2
- process $group_238
+ process $group_239
assign \DX_d2 1'0
assign \DX_d2 { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 16 \DX_d0_d1_d2
- process $group_239
+ process $group_240
assign \DX_d0_d1_d2 16'0000000000000000
assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DX_RT
- process $group_240
+ process $group_241
assign \DX_RT 5'00000
assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DX_XO
- process $group_241
+ process $group_242
assign \DX_XO 5'00000
assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 12 \DQ_DQ
- process $group_242
+ process $group_243
assign \DQ_DQ 12'000000000000
assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \DQ_PT
- process $group_243
+ process $group_244
assign \DQ_PT 4'0000
assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQ_RA
- process $group_244
+ process $group_245
assign \DQ_RA 5'00000
assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQ_RTp
- process $group_245
+ process $group_246
assign \DQ_RTp 5'00000
assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \DQ_SX
- process $group_246
+ process $group_247
assign \DQ_SX 1'0
assign \DQ_SX { \opcode_in [3] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQ_S
- process $group_247
+ process $group_248
assign \DQ_S 5'00000
assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \DQ_SX_S
- process $group_248
+ process $group_249
assign \DQ_SX_S 6'000000
assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \DQ_TX
- process $group_249
+ process $group_250
assign \DQ_TX 1'0
assign \DQ_TX { \opcode_in [3] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQ_T
- process $group_250
+ process $group_251
assign \DQ_T 5'00000
assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \DQ_TX_T
- process $group_251
+ process $group_252
assign \DQ_TX_T 6'000000
assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \DQ_XO
- process $group_252
+ process $group_253
assign \DQ_XO 3'000
assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 14 \DS_DS
- process $group_253
+ process $group_254
assign \DS_DS 14'00000000000000
assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_FRSp
- process $group_254
+ process $group_255
assign \DS_FRSp 5'00000
assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_FRTp
- process $group_255
+ process $group_256
assign \DS_FRTp 5'00000
assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_RA
- process $group_256
+ process $group_257
assign \DS_RA 5'00000
assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_RS
- process $group_257
+ process $group_258
assign \DS_RS 5'00000
assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_RSp
- process $group_258
+ process $group_259
assign \DS_RSp 5'00000
assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_RT
- process $group_259
+ process $group_260
assign \DS_RT 5'00000
assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_VRS
- process $group_260
+ process $group_261
assign \DS_VRS 5'00000
assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DS_VRT
- process $group_261
+ process $group_262
assign \DS_VRT 5'00000
assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \DS_XO
- process $group_262
+ process $group_263
assign \DS_XO 2'00
assign \DS_XO { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_EO
- process $group_263
+ process $group_264
assign \VX_EO 5'00000
assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \VX_PS
- process $group_264
+ process $group_265
assign \VX_PS 1'0
assign \VX_PS { \opcode_in [9] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_RA
- process $group_265
+ process $group_266
assign \VX_RA 5'00000
assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_RT
- process $group_266
+ process $group_267
assign \VX_RT 5'00000
assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_SIM
- process $group_267
+ process $group_268
assign \VX_SIM 5'00000
assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_UIM
- process $group_268
+ process $group_269
assign \VX_UIM 5'00000
assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \VX_UIM_1
- process $group_269
+ process $group_270
assign \VX_UIM_1 4'0000
assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \VX_UIM_2
- process $group_270
+ process $group_271
assign \VX_UIM_2 3'000
assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \VX_UIM_3
- process $group_271
+ process $group_272
assign \VX_UIM_3 2'00
assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_VRA
- process $group_272
+ process $group_273
assign \VX_VRA 5'00000
assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_VRB
- process $group_273
+ process $group_274
assign \VX_VRB 5'00000
assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VX_VRT
- process $group_274
+ process $group_275
assign \VX_VRT 5'00000
assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \VX_XO
- process $group_275
+ process $group_276
assign \VX_XO 10'0000000000
assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 11 \VX_XO_1
- process $group_276
+ process $group_277
assign \VX_XO_1 11'00000000000
assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \XFL_FLM
- process $group_277
+ process $group_278
assign \XFL_FLM 8'00000000
assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XFL_FRB
- process $group_278
+ process $group_279
assign \XFL_FRB 5'00000
assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XFL_L
- process $group_279
+ process $group_280
assign \XFL_L 1'0
assign \XFL_L { \opcode_in [25] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XFL_Rc
- process $group_280
+ process $group_281
assign \XFL_Rc 1'0
assign \XFL_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XFL_W
- process $group_281
+ process $group_282
assign \XFL_W 1'0
assign \XFL_W { \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \XFL_XO
- process $group_282
+ process $group_283
assign \XFL_XO 10'0000000000
assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRA
- process $group_283
+ process $group_284
assign \Z23_FRA 5'00000
assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRAp
- process $group_284
+ process $group_285
assign \Z23_FRAp 5'00000
assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRB
- process $group_285
+ process $group_286
assign \Z23_FRB 5'00000
assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRBp
- process $group_286
+ process $group_287
assign \Z23_FRBp 5'00000
assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRT
- process $group_287
+ process $group_288
assign \Z23_FRT 5'00000
assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_FRTp
- process $group_288
+ process $group_289
assign \Z23_FRTp 5'00000
assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \Z23_R
- process $group_289
+ process $group_290
assign \Z23_R 1'0
assign \Z23_R { \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \Z23_Rc
- process $group_290
+ process $group_291
assign \Z23_Rc 1'0
assign \Z23_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \Z23_RMC
- process $group_291
+ process $group_292
assign \Z23_RMC 2'00
assign \Z23_RMC { \opcode_in [10] \opcode_in [9] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \Z23_TE
- process $group_292
+ process $group_293
assign \Z23_TE 5'00000
assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 8 \Z23_XO
- process $group_293
+ process $group_294
assign \Z23_XO 8'00000000
assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MDS_IB
- process $group_294
+ process $group_295
assign \MDS_IB 5'00000
assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MDS_IS
- process $group_295
+ process $group_296
assign \MDS_IS 5'00000
assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \MDS_mb
- process $group_296
+ process $group_297
assign \MDS_mb 6'000000
assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \MDS_me
- process $group_297
+ process $group_298
assign \MDS_me 6'000000
assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MDS_RA
- process $group_298
+ process $group_299
assign \MDS_RA 5'00000
assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MDS_RB
- process $group_299
+ process $group_300
assign \MDS_RB 5'00000
assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \MDS_Rc
- process $group_300
+ process $group_301
assign \MDS_Rc 1'0
assign \MDS_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MDS_RS
- process $group_301
+ process $group_302
assign \MDS_RS 5'00000
assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \MDS_XBI
- process $group_302
+ process $group_303
assign \MDS_XBI 4'0000
assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \MDS_XBI_1
- process $group_303
+ process $group_304
assign \MDS_XBI_1 4'0000
assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \MDS_XO
- process $group_304
+ process $group_305
assign \MDS_XO 4'0000
assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 7 \SC_LEV
- process $group_305
+ process $group_306
assign \SC_LEV 7'0000000
assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \SC_XO
- process $group_306
+ process $group_307
assign \SC_XO 1'0
assign \SC_XO { \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \SC_XO_1
- process $group_307
+ process $group_308
assign \SC_XO_1 2'00
assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_MB
- process $group_308
+ process $group_309
assign \M_MB 5'00000
assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_ME
- process $group_309
+ process $group_310
assign \M_ME 5'00000
assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_RA
- process $group_310
+ process $group_311
assign \M_RA 5'00000
assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_RB
- process $group_311
+ process $group_312
assign \M_RB 5'00000
assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \M_Rc
- process $group_312
+ process $group_313
assign \M_Rc 1'0
assign \M_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_RS
- process $group_313
+ process $group_314
assign \M_RS 5'00000
assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \M_SH
- process $group_314
+ process $group_315
assign \M_SH 5'00000
assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \MD_mb
- process $group_315
+ process $group_316
assign \MD_mb 6'000000
assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \MD_me
- process $group_316
+ process $group_317
assign \MD_me 6'000000
assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MD_RA
- process $group_317
+ process $group_318
assign \MD_RA 5'00000
assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \MD_Rc
- process $group_318
+ process $group_319
assign \MD_Rc 1'0
assign \MD_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \MD_RS
- process $group_319
+ process $group_320
assign \MD_RS 5'00000
assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \MD_sh
- process $group_320
+ process $group_321
assign \MD_sh 6'000000
assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 \MD_XO
- process $group_321
+ process $group_322
assign \MD_XO 3'000
assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \all_OPCD
- process $group_322
+ process $group_323
assign \all_OPCD 6'000000
assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \all_PO
- process $group_323
+ process $group_324
assign \all_PO 6'000000
assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XO_OE
- process $group_324
+ process $group_325
assign \XO_OE 1'0
assign \XO_OE { \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XO_RA
- process $group_325
+ process $group_326
assign \XO_RA 5'00000
assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XO_RB
- process $group_326
+ process $group_327
assign \XO_RB 5'00000
assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XO_Rc
- process $group_327
+ process $group_328
assign \XO_Rc 1'0
assign \XO_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XO_RT
- process $group_328
+ process $group_329
assign \XO_RT 5'00000
assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 9 \XO_XO
- process $group_329
+ process $group_330
assign \XO_XO 9'000000000
assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQE_RA
- process $group_330
+ process $group_331
assign \DQE_RA 5'00000
assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \DQE_RT
- process $group_331
+ process $group_332
assign \DQE_RT 5'00000
assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 2 \DQE_XO
- process $group_332
+ process $group_333
assign \DQE_XO 2'00
assign \DQE_XO { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \TX_RA
- process $group_333
+ process $group_334
assign \TX_RA 5'00000
assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
- wire width 5 \TX_TO
- process $group_334
- assign \TX_TO 5'00000
- assign \TX_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \TX_UI
process $group_335
assign \TX_UI 5'00000
assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \TX_XBI
process $group_336
assign \TX_XBI 4'0000
assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \TX_XO
process $group_337
assign \TX_XO 6'000000
assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_RA
process $group_338
assign \VA_RA 5'00000
assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_RB
process $group_339
assign \VA_RB 5'00000
assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_RC
process $group_340
assign \VA_RC 5'00000
assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_RT
process $group_341
assign \VA_RT 5'00000
assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 4 \VA_SHB
process $group_342
assign \VA_SHB 4'0000
assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_VRA
process $group_343
assign \VA_VRA 5'00000
assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_VRB
process $group_344
assign \VA_VRB 5'00000
assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_VRC
process $group_345
assign \VA_VRC 5'00000
assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VA_VRT
process $group_346
assign \VA_VRT 5'00000
assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \VA_XO
process $group_347
assign \VA_XO 6'000000
assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XS_RA
process $group_348
assign \XS_RA 5'00000
assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \XS_Rc
process $group_349
assign \XS_Rc 1'0
assign \XS_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \XS_RS
process $group_350
assign \XS_RS 5'00000
assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 6 \XS_sh
process $group_351
assign \XS_sh 6'000000
assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 9 \XS_XO
process $group_352
assign \XS_XO 9'000000000
assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 1 \VC_Rc
process $group_353
assign \VC_Rc 1'0
assign \VC_Rc { \opcode_in [10] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VC_VRA
process $group_354
assign \VC_VRA 5'00000
assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VC_VRB
process $group_355
assign \VC_VRB 5'00000
assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 \VC_VRT
process $group_356
assign \VC_VRT 5'00000
assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 \VC_XO
process $group_357
assign \VC_XO 10'0000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_a"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a"
module \dec_a
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57"
wire width 3 input 0 \sel_in
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 2 \reg_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \reg_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
wire width 1 output 4 \immz_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 10 output 5 \spr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \spr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 7 \fast_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 8 \fast_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 9 \RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 10 \RA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 11 \BO
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 10 input 12 \SPR
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 input 13 \XL_XO
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69"
wire width 5 \ra
process $group_0
assign \ra 5'00000
assign \ra \RA
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $ne $6
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $5
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_1
assign \reg_a 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
switch { $9 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
case 1'1
assign \reg_a \ra
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
switch { $11 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
case 1'1
assign \reg_a \RS
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71"
cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $ne $18
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $17
connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $19
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
wire width 1 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
cell $eq $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_2
assign \reg_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
switch { $21 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73"
case 1'1
assign \reg_a_ok 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
switch { $23 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
case 1'1
assign \reg_a_ok 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:78"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
wire width 1 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:78"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
cell $eq $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
wire width 1 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
cell $eq $28
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $27
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \immz_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
case 1'1
assign \immz_out 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
cell $eq $34
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
cell $not $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \BO [2]
connect \Y $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \XL_XO [5]
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \fast_a 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
switch { $33 $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
case 2'-1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
switch { $35 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
case 1'1
assign \fast_a 3'010
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
case 2'1-
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
switch { $39 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
case 1'1
assign \fast_a 3'010
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
cell $eq $42
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
cell $not $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \BO [2]
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
cell $not $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \XL_XO [5]
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \fast_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
switch { $43 $41 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
case 2'-1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
switch { $45 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
case 1'1
assign \fast_a_ok 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
case 2'1-
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
switch { $49 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
case 1'1
assign \fast_a_ok 1'1
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
cell $eq $52
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_6
assign \spr_a 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
switch { $51 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
case 1'1
assign \spr_a \SPR
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
cell $eq $54
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_7
assign \spr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
case 1'1
assign \spr_a_ok 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_b"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_b"
module \dec_b
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
wire width 4 input 0 \sel_in
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 2 \reg_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \reg_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 4 \imm_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 5 \imm_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 6 \fast_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 7 \fast_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 8 \RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 9 \RB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 16 input 10 \SI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 16 input 11 \UI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 12 \SH32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 6 input 13 \sh
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 24 input 14 \LI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 14 input 15 \BD
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 14 input 16 \DS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 10 input 17 \XL_XO
process $group_0
assign \reg_b 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:133"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133"
attribute \nmigen.decoding "RB/1"
case 4'0001
assign \reg_b \RB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:136"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
attribute \nmigen.decoding "RS/13"
case 4'1101
assign \reg_b \RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:160"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:166"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:169"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
end
end
process $group_1
assign \reg_b_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:133"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133"
attribute \nmigen.decoding "RB/1"
case 4'0001
assign \reg_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:136"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
attribute \nmigen.decoding "RS/13"
case 4'1101
assign \reg_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:160"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:166"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:169"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 64 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
cell $pos $2
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \A \UI
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
wire width 64 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
wire width 47 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
cell $sshl $5
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
cell $pos $6
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $4
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
wire width 64 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
wire width 47 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
cell $sshl $9
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \B 5'10000
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
cell $pos $10
parameter \A_SIGNED 0
parameter \A_WIDTH 47
connect \A $8
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $13
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $12
end
connect $11 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $16
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $15
end
connect $14 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $19
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $18
end
connect $17 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $22
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $21
end
connect $20 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $25
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $24
end
connect $23 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $28
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $27
end
connect $26 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
wire width 47 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152"
cell $sshl $31
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $30
end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155"
cell $sshl $112
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $111
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:155"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155"
cell $pos $113
parameter \A_SIGNED 0
parameter \A_WIDTH 27
connect \A $111
connect \Y $110
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158"
wire width 64 $114
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158"
wire width 17 $115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158"
cell $sshl $116
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $115
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158"
cell $pos $117
parameter \A_SIGNED 0
parameter \A_WIDTH 17
connect \A $115
connect \Y $114
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 64 $118
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
wire width 17 $119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
cell $sshl $120
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $119
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161"
cell $pos $121
parameter \A_SIGNED 0
parameter \A_WIDTH 17
connect \A $119
connect \Y $118
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
wire width 64 $122
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:164"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164"
cell $not $123
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A 64'0000000000000000000000000000000000000000000000000000000000000000
connect \Y $122
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 64 $124
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
cell $pos $125
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \sh
connect \Y $124
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 64 $126
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
cell $pos $127
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
process $group_2
assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:133"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133"
attribute \nmigen.decoding "RB/1"
case 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:136"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
attribute \nmigen.decoding "RS/13"
case 4'1101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
assign \imm_b $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
assign \imm_b { { \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] } \SI }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
assign \imm_b $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
assign \imm_b $7
assign \imm_b { { $14 [31:0] [31] $17 [31:0] [31] $20 [31:0] [31] $23 [31:0] [31] $26 [31:0] [31] $29 [31:0] [31] $32 [31:0] [31] $35 [31:0] [31] $38 [31:0] [31] $41 [31:0] [31] $44 [31:0] [31] $47 [31:0] [31] $50 [31:0] [31] $53 [31:0] [31] $56 [31:0] [31] $59 [31:0] [31] $62 [31:0] [31] $65 [31:0] [31] $68 [31:0] [31] $71 [31:0] [31] $74 [31:0] [31] $77 [31:0] [31] $80 [31:0] [31] $83 [31:0] [31] $86 [31:0] [31] $89 [31:0] [31] $92 [31:0] [31] $95 [31:0] [31] $98 [31:0] [31] $101 [31:0] [31] $104 [31:0] [31] $107 [31:0] [31] } $11 [31:0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
assign \imm_b $110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
assign \imm_b $114
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:160"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
assign \imm_b $118
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
assign \imm_b $122
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:166"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
assign \imm_b $124
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:169"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
assign \imm_b $126
end
process $group_3
assign \imm_b_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:133"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133"
attribute \nmigen.decoding "RB/1"
case 4'0001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:136"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136"
attribute \nmigen.decoding "RS/13"
case 4'1101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:160"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:166"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
assign \imm_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:169"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
assign \imm_b_ok 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
wire width 1 $128
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
cell $eq $129
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $128
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire width 1 $130
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
cell $not $131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \fast_b 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch { $128 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
switch { \XL_XO [5] $130 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
case 2'-1
assign \fast_b 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:183"
case 2'1-
assign \fast_b 3'100
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
wire width 1 $132
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
cell $eq $133
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $132
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
wire width 1 $134
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
cell $not $135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \fast_b_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch { $132 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
switch { \XL_XO [5] $134 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:180"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
case 2'-1
assign \fast_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:183"
case 2'1-
assign \fast_b_ok 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_c"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_c"
module \dec_c
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
wire width 2 input 0 \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 1 \reg_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \reg_c_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 3 \RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 4 \RB
process $group_0
assign \reg_c 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
attribute \nmigen.decoding "RB/2"
case 2'10
assign \reg_c \RB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
attribute \nmigen.decoding "RS/1"
case 2'01
assign \reg_c \RS
end
process $group_1
assign \reg_c_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
attribute \nmigen.decoding "RB/2"
case 2'10
assign \reg_c_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
attribute \nmigen.decoding "RS/1"
case 2'01
assign \reg_c_ok 1'1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_o"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o"
module \dec_o
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
wire width 2 input 0 \sel_in
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 2 \reg_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \reg_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 10 output 4 \spr_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 5 \spr_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 6 \fast_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 7 \fast_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 8 \RT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 9 \RA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 10 \BO
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 10 input 11 \SPR
process $group_0
assign \reg_o 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:238"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:239"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
attribute \nmigen.decoding "RT/1"
case 2'01
assign \reg_o \RT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:242"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
attribute \nmigen.decoding "RA/2"
case 2'10
assign \reg_o \RA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:245"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245"
attribute \nmigen.decoding "SPR/3"
case 2'11
end
end
process $group_1
assign \reg_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:238"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:239"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
attribute \nmigen.decoding "RT/1"
case 2'01
assign \reg_o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:242"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
attribute \nmigen.decoding "RA/2"
case 2'10
assign \reg_o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:245"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245"
attribute \nmigen.decoding "SPR/3"
case 2'11
end
end
process $group_2
assign \spr_o 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:238"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:239"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:242"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:245"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245"
attribute \nmigen.decoding "SPR/3"
case 2'11
assign \spr_o \SPR
end
process $group_3
assign \spr_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:238"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:239"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:242"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:245"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245"
attribute \nmigen.decoding "SPR/3"
case 2'11
assign \spr_o_ok 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $3
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \BO [2]
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
cell $eq $10
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_4
assign \fast_o 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
switch { $7 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
case 1'1
assign \fast_o 3'010
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
switch { $9 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
case 1'1
assign \fast_o 3'101
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269"
cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $13
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \BO [2]
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
cell $eq $20
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_5
assign \fast_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
case 1'1
assign \fast_o_ok 1'1
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:276"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
case 1'1
assign \fast_o_ok 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_o2"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2"
module \dec_o2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
wire width 1 input 0 \lk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 2 \reg_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \reg_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 4 \fast_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 5 \fast_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
wire width 1 input 6 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 7 \RA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 6 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
cell $pos $2
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_0
assign \reg_o 5'00000
assign \reg_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
switch { \upd }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
case 1'1
assign { \reg_o_ok \reg_o } $1
assign \reg_o_ok 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
cell $eq $6
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $5
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
cell $eq $10
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_2
assign \fast_o 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
switch { $7 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
switch { \lk }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 1'1
assign \fast_o 3'011
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
switch { $9 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
case 1'1
assign \fast_o 3'110
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000111
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $13
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_3
assign \fast_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:309"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
switch { \lk }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:310"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 1'1
assign \fast_o_ok 1'1
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:315"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
case 1'1
assign \fast_o_ok 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_rc"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_rc"
module \dec_rc
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:329"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
wire width 2 input 0 \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 1 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 1 input 3 \Rc
process $group_0
assign \rc 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:338"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:338"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:339"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \rc \Rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:342"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:342"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \rc 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:345"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:345"
attribute \nmigen.decoding "NONE/0"
case 2'00
assign \rc 1'0
end
process $group_1
assign \rc_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:338"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:338"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:339"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \rc_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:342"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:342"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \rc_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:345"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:345"
attribute \nmigen.decoding "NONE/0"
case 2'00
assign \rc_ok 1'1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_oe"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_oe"
module \dec_oe
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:365"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365"
wire width 2 input 0 \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 1 \oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 1 input 3 \OE
process $group_0
assign \oe 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:374"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:375"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:375"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \oe \OE
end
process $group_1
assign \oe_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:374"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:375"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:375"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \oe_ok 1'1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_cr_in"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_cr_in"
module \dec_cr_in
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:390"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390"
wire width 3 input 0 \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 1 \cr_bitfield
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \cr_bitfield_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 3 \cr_bitfield_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \cr_bitfield_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 5 \cr_bitfield_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \cr_bitfield_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
wire width 1 output 7 \whole_reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 8 \BB
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 9 \BA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 10 \BT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 11 \BI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
wire width 5 input 12 \BC
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 input 13 \X_BFA
process $group_0
assign \cr_bitfield_ok 1'0
assign \cr_bitfield_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
process $group_1
assign \cr_bitfield_b_ok 1'0
assign \cr_bitfield_b_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_b_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
process $group_2
assign \whole_reg 1'0
assign \whole_reg 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
assign \whole_reg 1'1
end
process $group_3
assign \cr_bitfield 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
assign \cr_bitfield \BI [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
assign \cr_bitfield \X_BFA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield \BA [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
assign \cr_bitfield \BC [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_4
assign \cr_bitfield_b 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_b \BB [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_5
assign \cr_bitfield_o 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_o \BT [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_6
assign \cr_bitfield_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:405"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:407"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:423"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:426"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2.dec_cr_out"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_cr_out"
module \dec_cr_out
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
wire width 3 input 0 \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:441"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
wire width 1 input 1 \rc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 2 \cr_bitfield
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \cr_bitfield_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:445"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445"
wire width 1 output 4 \whole_reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 3 input 5 \X_BF
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
wire width 5 input 6 \XL_BT
process $group_0
assign \cr_bitfield_ok 1'0
assign \cr_bitfield_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:453"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield_ok \rc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459"
attribute \nmigen.decoding "BF/2"
case 3'010
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:462"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
attribute \nmigen.decoding "BT/3"
case 3'011
assign \cr_bitfield_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:465"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
end
process $group_1
assign \whole_reg 1'0
assign \whole_reg 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:453"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459"
attribute \nmigen.decoding "BF/2"
case 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:462"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
attribute \nmigen.decoding "BT/3"
case 3'011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:465"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
assign \whole_reg 1'1
end
process $group_2
assign \cr_bitfield 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:453"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453"
switch \sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:459"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459"
attribute \nmigen.decoding "BF/2"
case 3'010
assign \cr_bitfield \X_BF
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:462"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
attribute \nmigen.decoding "BT/3"
case 3'011
assign \cr_bitfield \XL_BT [4:2]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:465"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.pdecode2"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2"
module \pdecode2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:319"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
wire width 1 input 0 \bigendian
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
wire width 32 input 1 \raw_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:34"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
wire width 10 output 2 \fn_unit
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:33"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
wire width 7 output 3 \insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 4 \imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 5 \imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
wire width 1 output 6 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 7 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 8 \rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 9 \oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 10 \oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
wire width 1 output 11 \invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
wire width 1 output 12 \zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
wire width 1 output 13 \invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 14 \cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 15 \cr_out_ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:65"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
wire width 2 output 16 \input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
wire width 1 output 17 \output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
wire width 1 output 18 \input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
wire width 1 output 19 \output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
wire width 1 output 20 \is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
wire width 1 output 21 \is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
wire width 4 output 22 \data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
wire width 32 output 23 \insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
wire width 1 output 24 \byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:74"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
wire width 1 output 25 \sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 26 \reg1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 27 \reg2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
wire width 1 output 28 \read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
wire width 1 output 29 \write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 30 \cr_in1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 31 \cr_in2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 32 \cr_in2_ok$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 33 \fast1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 34 \fast2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 35 \reg3_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:75"
- wire width 1 output 36 \update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 37 \reg1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 38 \reg2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 39 \reg3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 40 \cr_in1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 41 \cr_in2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 42 \cr_in2$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 43 \fast1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 44 \fast2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 45 \rego
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 46 \ea
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 47 \fasto1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 48 \fasto2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 49 \opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77"
+ wire width 13 output 35 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 36 \reg3_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
+ wire width 1 output 37 \update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 38 \reg1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 39 \reg2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 40 \reg3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 41 \cr_in1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 42 \cr_in2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 43 \cr_in2$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 44 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 45 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 46 \rego
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 47 \ea
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 48 \fasto1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 49 \fasto2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ wire width 32 output 50 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 50 \in1_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+ wire width 3 output 51 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 51 \in2_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+ wire width 4 output 52 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 52 \in3_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+ wire width 2 output 53 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 53 \out_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+ wire width 2 output 54 \out_sel
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 54 \rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 55 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 55 \cr_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+ wire width 3 output 56 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 56 \cr_out$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:37"
- wire width 64 output 57 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+ wire width 3 output 57 \cr_out$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 64 output 58 \nia
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 10 output 58 \function_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 10 output 59 \function_unit
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 59 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 60 \rego_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 61 \ea_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 62 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 63 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 64 \spro
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 65 \spro_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 66 \fasto1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 67 \fasto2_ok
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+ wire width 7 output 60 \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 61 \rego_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 62 \ea_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 63 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 64 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 65 \spro
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 66 \spro_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 67 \fasto1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 68 \fasto2_ok
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 68 \ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 69 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 70 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 71 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 72 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 73 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 74 \lk$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 75 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 76 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 77 \upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+ wire width 4 output 69 \ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 70 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 71 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 72 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 73 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 74 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 75 \lk$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 76 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 77 \sgn_ext
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attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
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+ wire width 1 output 80 \rsrv
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec_cry_in
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wire width 1 \dec_LK
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wire width 5 \dec_RS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_RT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_RA
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wire width 5 \dec_RB
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wire width 16 \dec_SI
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wire width 16 \dec_UI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_SH32
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wire width 6 \dec_sh
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 24 \dec_LI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 1 \dec_Rc
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wire width 1 \dec_OE
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wire width 14 \dec_BD
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wire width 5 \dec_BB
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wire width 5 \dec_BA
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wire width 5 \dec_BT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_BO
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_BI
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 14 \dec_DS
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 5 \dec_BC
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:322"
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wire width 10 \dec_SPR
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
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wire width 3 \dec_X_BF
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wire width 3 \dec_X_BFA
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
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wire width 5 \dec_XL_BT
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:335"
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wire width 10 \dec_XL_XO
cell \dec \dec
connect \bigendian \bigendian
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:57"
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wire width 3 \dec_a_sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 5 \dec_a_reg_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_a_reg_a_ok
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wire width 1 \dec_a_immz_out
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wire width 10 \dec_a_spr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_a_spr_a_ok
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wire width 3 \dec_a_fast_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_a_fast_a_ok
cell \dec_a \dec_a
connect \sel_in \dec_a_sel_in
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:121"
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wire width 4 \dec_b_sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 5 \dec_b_reg_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_b_reg_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 64 \dec_b_imm_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_b_imm_b_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 3 \dec_b_fast_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_b_fast_b_ok
cell \dec_b \dec_b
connect \sel_in \dec_b_sel_in
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
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wire width 2 \dec_c_sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 5 \dec_c_reg_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_c_reg_c_ok
cell \dec_c \dec_c
connect \sel_in \dec_c_sel_in
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
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wire width 2 \dec_o_sel_in
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wire width 5 \dec_o_reg_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_o_reg_o_ok
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wire width 10 \dec_o_spr_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_o_spr_o_ok
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wire width 3 \dec_o_fast_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_o_fast_o_ok
cell \dec_o \dec_o
connect \sel_in \dec_o_sel_in
connect \BO \dec_BO
connect \SPR \dec_SPR
end
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wire width 1 \dec_o2_lk
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wire width 5 \dec_o2_reg_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_o2_reg_o_ok
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wire width 3 \dec_o2_fast_o
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wire width 1 \dec_o2_fast_o_ok
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attribute \enum_value_00 "NONE"
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attribute \enum_value_10 "RC"
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wire width 2 \dec_rc_sel_in
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wire width 1 \dec_rc_rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_rc_rc_ok
cell \dec_rc \dec_rc
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attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:365"
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wire width 2 \dec_oe_sel_in
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wire width 1 \dec_oe_oe
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wire width 1 \dec_oe_oe_ok
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attribute \enum_value_100 "BA_BB"
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attribute \enum_value_110 "WHOLE_REG"
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wire width 3 \dec_cr_in_sel_in
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wire width 3 \dec_cr_in_cr_bitfield
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_cr_in_cr_bitfield_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 3 \dec_cr_in_cr_bitfield_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_cr_in_cr_bitfield_b_ok
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wire width 3 \dec_cr_in_cr_bitfield_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \dec_cr_in_cr_bitfield_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:395"
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wire width 1 \dec_cr_in_whole_reg
cell \dec_cr_in \dec_cr_in
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attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
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wire width 3 \dec_cr_out_sel_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:441"
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wire width 1 \dec_cr_out_rc_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 3 \dec_cr_out_cr_bitfield
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_cr_out_cr_bitfield_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:445"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445"
wire width 1 \dec_cr_out_whole_reg
cell \dec_cr_out \dec_cr_out
connect \sel_in \dec_cr_out_sel_in
assign \insn \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58"
wire width 32 \insn_in
process $group_1
assign \insn_in 32'00000000000000000000000000000000
assign \insn_in \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122"
wire width 32 \insn_in$5
process $group_2
assign \insn_in$5 32'00000000000000000000000000000000
assign \insn_in$5 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:199"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
wire width 32 \insn_in$6
process $group_3
assign \insn_in$6 32'00000000000000000000000000000000
assign \insn_in$6 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227"
wire width 32 \insn_in$7
process $group_4
assign \insn_in$7 32'00000000000000000000000000000000
assign \insn_in$7 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:293"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
wire width 32 \insn_in$8
process $group_5
assign \insn_in$8 32'00000000000000000000000000000000
assign \insn_in$8 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
wire width 32 \insn_in$9
process $group_6
assign \insn_in$9 32'00000000000000000000000000000000
assign \insn_in$9 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:366"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366"
wire width 32 \insn_in$10
process $group_7
assign \insn_in$10 32'00000000000000000000000000000000
assign \insn_in$10 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:391"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:391"
wire width 32 \insn_in$11
process $group_8
assign \insn_in$11 32'00000000000000000000000000000000
assign \insn_in$11 \opcode_in
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:443"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443"
wire width 32 \insn_in$12
process $group_9
assign \insn_in$12 32'00000000000000000000000000000000
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
wire width 2 \sel_in
process $group_14
assign \sel_in 2'00
sync init
update $verilog_initial_trigger 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
wire width 7 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
wire width 1 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
cell $eq $15
parameter \A_SIGNED 0
parameter \A_WIDTH 10
connect \B 10'0000000000
connect \Y $14
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:530"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
cell $mux $16
parameter \WIDTH 7
connect \A \internal_op
end
process $group_70
assign \lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:573"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573"
switch { \lk$4 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder2.py:573"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573"
case 1'1
assign \lk \dec_LK
end
assign \output_cr \cr_out$3 [0]
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586"
+ cell $eq $18
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \internal_op
+ connect \B 7'0111111
+ connect \Y $17
+ end
+ process $group_76
+ assign \trapaddr 13'0000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586"
+ switch { $17 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586"
+ case 1'1
+ assign \trapaddr 13'0000001110000
+ end
+ sync init
+ end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.p"
module \p
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.n"
module \n
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.p"
module \p$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.n"
module \n$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe.input"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.input"
module \input
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 13 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 14 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 15 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 input 21 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 input 22 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \op__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \op__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 25 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 26 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 1 input 27 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 28 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 29 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 output 30 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 output 31 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 34 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 35 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 37 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 39 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 40 \op__zero_a$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 41 \op__invert_out$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 output 42 \op__write_cr__data$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 43 \op__write_cr__ok$15
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 output 44 \op__input_carry$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 45 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 46 \op__input_cr$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 47 \op__output_cr$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 48 \op__is_32bit$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 49 \op__is_signed$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 output 50 \op__data_len$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 output 51 \op__insn$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 52 \op__byte_reverse$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 53 \op__sign_extend$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 output 54 \ra$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 output 55 \rb$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 1 output 56 \xer_so$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 output 57 \xer_ca$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
wire width 64 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
cell $not $31
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
process $group_0
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
switch { \op__invert_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
case 1'1
assign \a $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:25"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
case
assign \a \ra
end
end
process $group_2
assign \xer_ca$29 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:36"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
switch \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:37"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
attribute \nmigen.decoding "ZERO/0"
case 2'00
assign \xer_ca$29 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:39"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \xer_ca$29 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
attribute \nmigen.decoding "CA/2"
case 2'10
assign \xer_ca$29 \xer_ca
end
process $group_3
assign \xer_so$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
switch { \op__oe__oe_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
case 1'1
assign \xer_so$28 \xer_so
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe.main"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.main"
module \main
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 13 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 14 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 15 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 input 21 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 input 22 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \op__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \op__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 25 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 26 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 1 input 27 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 28 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 29 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 output 30 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 output 31 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 34 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 35 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 37 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 39 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 40 \op__zero_a$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 41 \op__invert_out$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 output 42 \op__write_cr__data$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 43 \op__write_cr__ok$15
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 output 44 \op__input_carry$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 45 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 46 \op__input_cr$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 47 \op__output_cr$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 48 \op__is_32bit$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 49 \op__is_signed$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 output 50 \op__data_len$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 output 51 \op__insn$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 52 \op__byte_reverse$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 53 \op__sign_extend$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 54 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 55 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 56 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 57 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 58 \xer_ca$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 59 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 60 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 61 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 62 \xer_so$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:39"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:39"
wire width 1 \is_32bit
process $group_0
assign \is_32bit 1'0
assign \is_32bit \op__is_32bit
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:40"
wire width 1 \sign_bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42"
wire width 1 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42"
cell $mux $29
parameter \WIDTH 1
connect \A \ra [63]
assign \sign_bit $28
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:46"
wire width 66 \add_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
wire width 1 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
cell $eq $31
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000010
connect \Y $30
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $eq $33
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001010
connect \Y $32
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $or $35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
switch { $34 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
assign \add_a { 1'0 \ra \xer_ca [0] }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:47"
wire width 66 \add_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
wire width 1 $36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
cell $eq $37
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000010
connect \Y $36
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $eq $39
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001010
connect \Y $38
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $or $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
switch { $40 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
assign \add_b { 1'0 \rb 1'1 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:48"
wire width 66 \add_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
wire width 1 $42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
cell $eq $43
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0000010
connect \Y $42
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $eq $45
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001010
connect \Y $44
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
wire width 1 $46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
cell $or $47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $44
connect \Y $46
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
wire width 67 $48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
wire width 67 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
cell $add $50
parameter \A_SIGNED 0
parameter \A_WIDTH 66
connect $48 $49
process $group_4
assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
switch { $46 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
assign \add_o $48 [65:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
cell $eq $52
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B 1'1
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
cell $eq $54
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B 2'10
connect \Y $53
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
cell $eq $56
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B 3'100
connect \Y $55
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:101"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101"
wire width 8 \eqs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
cell $reduce_or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 8
end
process $group_5
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
assign \o \add_o [64:1]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \o \add_o [64:1]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
switch { $51 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
case 1'1
assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
case 1'1
assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
switch { $55 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
case 1'1
assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \o [0] $57
end
process $group_6
assign \o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
assign \o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
assign \o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \o_ok 1'0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77"
wire width 2 \ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
wire width 1 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
cell $xor $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rb [32]
connect \Y $59
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
wire width 1 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
cell $xor $62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \ca 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \ca [0] \add_o [65]
assign \ca [1] $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
end
process $group_8
assign \xer_ca$26 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \xer_ca$26 \ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
end
process $group_9
assign \xer_ca_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \xer_ca_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:83"
wire width 2 \ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $xor $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \add_o [64]
connect \Y $63
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $xor $67
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rb [63]
connect \Y $66
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $not $68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $66
connect \Y $65
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $and $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $65
connect \Y $69
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $xor $72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \add_o [32]
connect \Y $71
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $xor $75
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rb [31]
connect \Y $74
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $not $76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $74
connect \Y $73
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
cell $and $78
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_10
assign \ov 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \ov [0] $69
assign \ov [1] $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
end
process $group_11
assign \xer_ov 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \xer_ov \ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
end
process $group_12
assign \xer_ov_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \xer_ov_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
wire width 8 \src1
process $group_13
assign \src1 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \src1 \ra [7:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $80
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [7:0]
connect \Y $79
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $82
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [15:8]
connect \Y $81
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $84
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [23:16]
connect \Y $83
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $86
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [31:24]
connect \Y $85
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $88
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [39:32]
connect \Y $87
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $90
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [47:40]
connect \Y $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $92
parameter \A_SIGNED 0
parameter \A_WIDTH 8
connect \B \rb [55:48]
connect \Y $91
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
wire width 1 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
cell $eq $94
parameter \A_SIGNED 0
parameter \A_WIDTH 8
end
process $group_14
assign \eqs 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \eqs [0] $79
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
wire width 1 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
cell $reduce_or $96
parameter \A_SIGNED 0
parameter \A_WIDTH 8
end
process $group_15
assign \cr_a 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \cr_a { 1'0 $95 2'00 }
end
process $group_16
assign \cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \nmigen.decoding "OP_CMP/10"
case 7'0001010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
assign \cr_a_ok 1'1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe.output"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe.output"
module \output
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 13 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 14 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 15 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 input 21 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 input 22 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \op__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \op__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 25 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 26 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 input 27 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 input 28 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 input 29 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 30 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 31 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 output 32 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 output 33 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 output 34 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 35 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 36 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 37 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 38 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 39 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 40 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 41 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 42 \op__zero_a$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 43 \op__invert_out$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 output 44 \op__write_cr__data$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 45 \op__write_cr__ok$15
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 output 46 \op__input_carry$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 47 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 48 \op__input_cr$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 49 \op__output_cr$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 50 \op__is_32bit$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 51 \op__is_signed$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 output 52 \op__data_len$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 output 53 \op__insn$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 54 \op__byte_reverse$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 55 \op__sign_extend$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 56 \o$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 57 \o_ok$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 58 \cr_a$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 59 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 60 \xer_ca$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 61 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 62 \xer_ov$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 63 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 64 \xer_so$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 65 \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
wire width 65 \o$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
wire width 65 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
wire width 64 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
cell $not $35
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A \o
connect \Y $34
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
cell $pos $36
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $34
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 65 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
cell $pos $38
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
process $group_0
assign \o$32 65'00000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
switch { \op__invert_out }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
case 1'1
assign \o$32 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
case
assign \o$32 $37
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire width 64 \target
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
wire width 64 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
cell $pos $40
parameter \A_SIGNED 0
parameter \A_WIDTH 32
end
process $group_1
assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
switch { \op__is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
case 1'1
assign \target $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
case
assign \target \o$32 [63:0]
end
assign \xer_ca_ok \op__output_carry
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
wire width 1 \is_cmp
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
cell $eq $42
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmp $41
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
wire width 1 \is_cmpeqb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmpeqb $43
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
wire width 1 \msb_test
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
cell $xor $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \msb_test $45
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
wire width 1 \is_nzero
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
cell $reduce_bool $48
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \is_nzero $47
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 1 \is_positive
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $not $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \msb_test
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_positive $51
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
wire width 1 \is_negative
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_negative $53
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
wire width 4 \cr0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
wire width 1 \so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
cell $not $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_10
assign \cr0 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
switch { \is_cmpeqb }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
case 1'1
assign \cr0 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
case
assign \cr0 { \is_negative \is_positive $55 \so }
end
assign { \op__sign_extend$25 \op__byte_reverse$24 \op__insn$23 \op__data_len$22 \op__is_signed$21 \op__is_32bit$20 \op__output_cr$19 \op__input_cr$18 \op__output_carry$17 \op__input_carry$16 { \op__write_cr__ok$15 \op__write_cr__data$14 } \op__invert_out$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \xer_so$31 \so
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
wire width 1 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
cell $and $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \xer_ov$30 \xer_ov
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
wire width 1 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/output_stage.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
cell $and $62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu.pipe"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu.pipe"
module \pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 2 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 3 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 4 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 6 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 13 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 14 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 15 \op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 16 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 17 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 19 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 21 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 22 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 input 25 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 input 26 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 27 \op__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 28 \op__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 29 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 30 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 1 input 31 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 32 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 33 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 34 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 35 \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$1$next
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 output 36 \op__insn_type$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 output 37 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 \op__fn_unit$3$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 output 38 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 39 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 40 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__lk$6$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 41 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__rc__rc$7$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 42 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__rc__rc_ok$8$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 43 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__oe__oe$9$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 44 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__oe__oe_ok$10$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 45 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__invert_a$11$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 46 \op__zero_a$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__zero_a$12$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 47 \op__invert_out$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__invert_out$13$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 output 48 \op__write_cr__data$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 \op__write_cr__data$14$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 49 \op__write_cr__ok$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__write_cr__ok$15$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 output 50 \op__input_carry$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 \op__input_carry$16$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 51 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__output_carry$17$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 52 \op__input_cr$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__input_cr$18$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 53 \op__output_cr$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__output_cr$19$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 54 \op__is_32bit$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__is_32bit$20$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 55 \op__is_signed$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__is_signed$21$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 output 56 \op__data_len$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 \op__data_len$22$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 output 57 \op__insn$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 \op__insn$23$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 58 \op__byte_reverse$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__byte_reverse$24$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 59 \op__sign_extend$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__sign_extend$25$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 60 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 61 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 62 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 63 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 64 \xer_ca$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ca$26$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 65 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 66 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ov$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 67 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ov_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 68 \xer_so$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so$27$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 69 \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so_ok$next
cell \p$1 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \input_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 \input_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 \input_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 \input_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 \input_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 \input_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \input_op__is_signed
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cell \input \input
connect \muxid \input_muxid
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end
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wire width 1 \output_op__write_cr__ok$98
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
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attribute \enum_value_10 "CA"
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wire width 2 \output_op__input_carry$99
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wire width 1 \output_op__output_carry$100
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wire width 1 \output_op__input_cr$101
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wire width 1 \output_op__output_cr$102
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wire width 1 \output_op__is_32bit$103
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wire width 1 \output_op__is_signed$104
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wire width 4 \output_op__data_len$105
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wire width 32 \output_op__insn$106
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wire width 1 \output_op__byte_reverse$107
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wire width 1 \output_op__sign_extend$108
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wire width 1 \output_o_ok$110
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wire width 4 \output_cr_a$111
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wire width 1 \output_cr_a_ok
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wire width 2 \output_xer_ca$112
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wire width 1 \output_xer_ca_ok
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wire width 2 \output_xer_ov$113
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wire width 1 \output_xer_ov_ok
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wire width 1 \output_xer_so$114
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_so_ok
cell \output \output
connect \muxid \output_muxid
assign { \output_o_ok \output_o } { \main_o_ok \main_o }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$115
process $group_85
assign \output_cr_a 4'0000
assign { \cr_a_ok$115 \output_cr_a } { \main_cr_a_ok \main_cr_a }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$116
process $group_87
assign \output_xer_ca 2'00
assign { \xer_ca_ok$116 \output_xer_ca } { \main_xer_ca_ok \main_xer_ca$82 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ov_ok$117
process $group_89
assign \output_xer_ov 2'00
assign { \xer_ov_ok$117 \output_xer_ov } { \main_xer_ov_ok \main_xer_ov }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \xer_so_ok$118
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so_ok$119
process $group_91
assign \output_xer_so 1'0
assign { \xer_so_ok$118 \output_xer_so } { \xer_so_ok$119 \main_xer_so$83 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:621"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
wire width 1 \p_valid_i$120
process $group_93
assign \p_valid_i$120 1'0
assign \p_valid_i$120 \p_valid_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:619"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
process $group_94
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
wire width 1 $121
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \p_valid_i_p_ready_o $121
sync init
end
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+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$123
process $group_96
assign \muxid$123 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
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wire width 7 \op__insn_type$124
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
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attribute \enum_value_1000000000 "DIV"
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wire width 10 \op__fn_unit$125
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wire width 1 \op__zero_a$134
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wire width 1 \op__invert_out$135
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wire width 3 \op__write_cr__data$136
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__write_cr__ok$137
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \op__input_carry$138
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wire width 1 \op__output_carry$139
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wire width 1 \op__input_cr$140
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__sign_extend$147
process $group_97
assign \op__insn_type$124 7'0000000
assign { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 } { \output_op__sign_extend$108 \output_op__byte_reverse$107 \output_op__insn$106 \output_op__data_len$105 \output_op__is_signed$104 \output_op__is_32bit$103 \output_op__output_cr$102 \output_op__input_cr$101 \output_op__output_carry$100 \output_op__input_carry$99 { \output_op__write_cr__ok$98 \output_op__write_cr__data$97 } \output_op__invert_out$96 \output_op__zero_a$95 \output_op__invert_a$94 { \output_op__oe__oe_ok$93 \output_op__oe__oe$92 } { \output_op__rc__rc_ok$91 \output_op__rc__rc$90 } \output_op__lk$89 { \output_op__imm_data__imm_ok$88 \output_op__imm_data__imm$87 } \output_op__fn_unit$86 \output_op__insn_type$85 }
sync init
end
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wire width 64 \o$148
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wire width 1 \o_ok$149
process $group_121
assign \o$148 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \o_ok$149 \o$148 } { \output_o_ok$110 \output_o$109 }
sync init
end
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wire width 4 \cr_a$150
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$151
process $group_123
assign \cr_a$150 4'0000
assign { \cr_a_ok$151 \cr_a$150 } { \output_cr_a_ok \output_cr_a$111 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 2 \xer_ca$152
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$153
process $group_125
assign \xer_ca$152 2'00
assign { \xer_ca_ok$153 \xer_ca$152 } { \output_xer_ca_ok \output_xer_ca$112 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 2 \xer_ov$154
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ov_ok$155
process $group_127
assign \xer_ov$154 2'00
assign { \xer_ov_ok$155 \xer_ov$154 } { \output_xer_ov_ok \output_xer_ov$113 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so$156
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so_ok$157
process $group_129
assign \xer_so$156 1'0
assign { \xer_so_ok$157 \xer_so$156 } { \output_xer_so_ok \output_xer_so$114 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
process $group_131
assign \r_busy$next \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \r_busy$next 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \r_busy$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \r_busy$next 1'0
end
process $group_132
assign \muxid$1$next \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \muxid$1$next \muxid$123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \muxid$1$next \muxid$123
end
assign \op__insn$23$next \op__insn$23
assign \op__byte_reverse$24$next \op__byte_reverse$24
assign \op__sign_extend$25$next \op__sign_extend$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \op__sign_extend$25$next \op__byte_reverse$24$next \op__insn$23$next \op__data_len$22$next \op__is_signed$21$next \op__is_32bit$20$next \op__output_cr$19$next \op__input_cr$18$next \op__output_carry$17$next \op__input_carry$16$next { \op__write_cr__ok$15$next \op__write_cr__data$14$next } \op__invert_out$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \op__sign_extend$25$next \op__byte_reverse$24$next \op__insn$23$next \op__data_len$22$next \op__is_signed$21$next \op__is_32bit$20$next \op__output_cr$19$next \op__input_cr$18$next \op__output_carry$17$next \op__input_carry$16$next { \op__write_cr__ok$15$next \op__write_cr__data$14$next } \op__invert_out$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
process $group_157
assign \o$next \o
assign \o_ok$next \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \o_ok$next \o$next } { \o_ok$149 \o$148 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \o_ok$next \o$next } { \o_ok$149 \o$148 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \o_ok$next 1'0
process $group_159
assign \cr_a$next \cr_a
assign \cr_a_ok$next \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$151 \cr_a$150 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$151 \cr_a$150 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_a_ok$next 1'0
process $group_161
assign \xer_ca$26$next \xer_ca$26
assign \xer_ca_ok$next \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \xer_ca_ok$next \xer_ca$26$next } { \xer_ca_ok$153 \xer_ca$152 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \xer_ca_ok$next \xer_ca$26$next } { \xer_ca_ok$153 \xer_ca$152 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_ca_ok$next 1'0
process $group_163
assign \xer_ov$next \xer_ov
assign \xer_ov_ok$next \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$155 \xer_ov$154 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$155 \xer_ov$154 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_ov_ok$next 1'0
process $group_165
assign \xer_so$27$next \xer_so$27
assign \xer_so_ok$next \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \xer_so_ok$next \xer_so$27$next } { \xer_so_ok$157 \xer_so$156 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \xer_so_ok$next \xer_so$27$next } { \xer_so_ok$157 \xer_so$156 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_so_ok$next 1'0
connect \xer_so_ok$119 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu"
module \alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 3 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 5 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 7 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 8 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 9 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 10 \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 11 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 12 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 13 \n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 14 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 15 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 16 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 21 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 22 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 25 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 26 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 27 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 input 28 \op__input_carry
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wire width 1 input 29 \op__output_carry
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wire width 1 input 30 \op__input_cr
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wire width 1 input 31 \op__output_cr
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wire width 1 input 33 \op__is_signed
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wire width 32 input 35 \op__insn
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wire width 1 input 36 \op__byte_reverse
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wire width 1 input 37 \op__sign_extend
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wire width 64 input 38 \ra
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wire width 64 input 39 \rb
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wire width 1 input 40 \xer_so$1
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wire width 2 input 41 \xer_ca$2
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wire width 1 input 42 \p_valid_i
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wire width 1 output 43 \p_ready_o
cell \p \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
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attribute \enum_base_type "Function"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \pipe_op__byte_reverse$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \pipe_op__sign_extend$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 64 \pipe_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \pipe_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \pipe_cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 2 \pipe_xer_ca$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \pipe_xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \pipe_xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \pipe_xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 \pipe_xer_so$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_so_ok
cell \pipe \pipe
connect \rst \rst
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$30
process $group_33
assign \muxid$30 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 \op__insn_type$31
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 10 \op__fn_unit$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 64 \op__imm_data__imm$33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__imm_data__imm_ok$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__lk$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__rc__rc$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__rc__rc_ok$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__oe__oe$38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__oe__oe_ok$39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__invert_a$40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__zero_a$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__invert_out$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 3 \op__write_cr__data$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__write_cr__ok$44
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 2 \op__input_carry$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__output_carry$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__input_cr$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__output_cr$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__is_32bit$49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \op__is_signed$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 4 \op__data_len$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 32 \op__insn$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__byte_reverse$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \op__sign_extend$54
process $group_34
assign \op__insn_type$31 7'0000000
connect \muxid 2'00
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.src_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l"
module \src_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 4'0000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 4 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 4 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 4 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.opc_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l"
module \opc_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.req_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l"
module \req_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 5 output 2 \q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 5 input 3 \s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 5 input 4 \r_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 5 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 5 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \r_req
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 5 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 5 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 5'00000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 5 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \r_req
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 5 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 5 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \q_req $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 5 \qn_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 5 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \qn_req $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 5 \qlq_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 5 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.rst_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l"
module \rst_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.rok_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l"
module \rok_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 3 \s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 4 \r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rdok $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rdok $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alui_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l"
module \alui_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alui $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alui $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0.alu_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l"
module \alu_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.alu0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.alu0"
module \alu0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 3 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 6 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 7 \oper_i__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 8 \oper_i__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \oper_i__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \oper_i__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \oper_i__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 input 13 \oper_i__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 3 input 14 \oper_i__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 15 \oper_i__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 16 \oper_i__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 18 \oper_i__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \oper_i__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 20 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 21 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 4 input 22 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 32 input 23 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \oper_i__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 input 25 \oper_i__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
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wire width 1 input 26 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
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wire width 1 output 27 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
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wire width 4 input 28 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
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wire width 4 output 29 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
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wire width 4 input 30 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 31 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 32 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 1 input 33 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
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wire width 2 input 34 \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 output 35 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
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wire width 5 output 36 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
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wire width 5 input 37 \wr__go
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wire width 64 output 38 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 output 39 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 4 output 40 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 output 41 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 2 output 42 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 43 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 44 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 45 \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 46 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
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wire width 1 input 47 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
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wire width 1 input 48 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
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wire width 64 output 49 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
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wire width 1 \alu_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \alu_n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 7 \alu_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 \alu_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 \alu_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 3 \alu_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 2 \alu_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 \alu_op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 32 \alu_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \alu_op__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \alu_op__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
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wire width 64 \alu_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 1 \alu_xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 \alu_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \alu_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \alu_p_ready_o
cell \alu \alu
connect \rst \rst
connect \p_valid_i \alu_p_valid_i
connect \p_ready_o \alu_p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
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wire width 4 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 \src_l_q_src
cell \src_l \src_l
connect \rst \rst
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
cell \opc_l \opc_l
connect \rst \rst
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 5 \req_l_q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 5 \req_l_s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 5 \req_l_r_req
cell \req_l \req_l
connect \rst \rst
connect \s_req \req_l_s_req
connect \r_req \req_l_r_req
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
cell \rst_l \rst_l
connect \rst \rst
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rok_l_s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok$next
cell \rok_l \rok_l
connect \rst \rst
connect \s_rdok \rok_l_s_rdok
connect \r_rdok \rok_l_r_rdok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alui_l_q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alui_l_s_alui
cell \alui_l \alui_l
connect \rst \rst
connect \r_alui \alui_l_r_alui
connect \s_alui \alui_l_s_alui
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
cell \alu_l \alu_l
connect \rst \rst
connect \r_alu \alu_l_r_alu
connect \s_alu \alu_l_s_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
wire width 1 \all_rd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rok_l_q_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rd__rel
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $or $7
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \rd__go
connect \Y $6
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $reduce_and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A $6
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly$next
process $group_1
assign \all_rd_dly$next \all_rd_dly
sync posedge \clk
update \all_rd_dly \all_rd_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
wire width 1 \all_rd_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \all_rd_dly
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd_pulse $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire width 1 \alu_done
process $group_3
assign \alu_done 1'0
assign \alu_done \alu_n_valid_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly$next
process $group_4
assign \alu_done_dly$next \alu_done_dly
sync posedge \clk
update \alu_done_dly \alu_done_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
wire width 1 \alu_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_done_dly
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_pulse $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 5 \alu_pulsem
process $group_6
assign \alu_pulsem 5'00000
assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 5 \prev_wr_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 5 \prev_wr_go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
wire width 5 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_7
assign \prev_wr_go$next \prev_wr_go
assign \prev_wr_go$next $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \prev_wr_go$next 5'00000
sync posedge \clk
update \prev_wr_go \prev_wr_go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 5 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 5 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $24
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \wrmask
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 5 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $26
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $reduce_bool $27
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A $25
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $22
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o $29
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \wr__go
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \prev_wr_go
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_n_ready_i
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 5 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B \wrmask
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 1'0
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $43
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 1'0
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_ready_i
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_valid_o
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_10
assign \req_done 1'0
assign \req_done $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
case 1'1
assign \req_done 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
wire width 1 \reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
cell $or $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset $55
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \rst_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_r $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 5 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
wire width 5 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \reset_w $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 4 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire width 4 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rok_l_s_rdok \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
assign \rok_l_r_rdok$next $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \rok_l_r_rdok$next 1'1
process $group_19
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_20
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_21
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 4'0000
process $group_22
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 4'1111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
wire width 5 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \req_l_s_req $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
wire width 5 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \req_l_r_req $67
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok$next
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_out
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_out$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok$next
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry$next
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__input_cr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_cr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__byte_reverse$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__sign_extend$next
process $group_25
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__insn$next \oper_l__insn
assign \oper_l__byte_reverse$next \oper_l__byte_reverse
assign \oper_l__sign_extend$next \oper_l__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 \oper_r__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 \oper_r__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 \oper_r__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 \oper_r__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 \oper_r__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \oper_r__sign_extend
process $group_49
assign \oper_r__insn_type 7'0000000
assign \oper_r__insn 32'00000000000000000000000000000000
assign \oper_r__byte_reverse 1'0
assign \oper_r__sign_extend 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__sign_extend \oper_l__byte_reverse \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $70
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_73
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r0_l__o_ok$next 1'0
update \data_r0_l__o \data_r0_l__o$next
update \data_r0_l__o_ok \data_r0_l__o_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r0__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r0__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $72
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_75
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $71 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0__o_ok \data_r0__o } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_77
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r1_l__cr_a_ok$next 1'0
update \data_r1_l__cr_a \data_r1_l__cr_a$next
update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 4 \data_r1__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r1__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_79
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_81
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $77 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r2_l__xer_ca_ok$next 1'0
update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 2 \data_r2__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r2__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_83
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r3_l__xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r3_l__xer_ov$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r3_l__xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r3_l__xer_ov_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $82
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_85
assign \data_r3_l__xer_ov$next \data_r3_l__xer_ov
assign \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $81 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \xer_ov }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r3_l__xer_ov_ok$next 1'0
update \data_r3_l__xer_ov \data_r3_l__xer_ov$next
update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 2 \data_r3__xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r3__xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_87
assign \data_r3__xer_ov 2'00
assign \data_r3__xer_ov_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $83 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \xer_ov_ok \xer_ov }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r4_l__xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r4_l__xer_so$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r4_l__xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r4_l__xer_so_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $86
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_89
assign \data_r4_l__xer_so$next \data_r4_l__xer_so
assign \data_r4_l__xer_so_ok$next \data_r4_l__xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $85 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \xer_so }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r4_l__xer_so_ok$next 1'0
update \data_r4_l__xer_so \data_r4_l__xer_so$next
update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r4__xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r4__xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $88
parameter \A_SIGNED 0
parameter \A_WIDTH 5
process $group_91
assign \data_r4__xer_so 1'0
assign \data_r4__xer_so_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $87 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r4__xer_so_ok \data_r4__xer_so } { \xer_so_ok \xer_so }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r4__xer_so_ok \data_r4__xer_so } { \data_r4_l__xer_so_ok \data_r4_l__xer_so }
end
assign { \alu_op__sign_extend \alu_op__byte_reverse \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_cr \alu_op__input_cr \alu_op__output_carry \alu_op__input_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $90
parameter \WIDTH 1
connect \A \src_l_q_src [0]
assign \src_sel $89
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $92
parameter \WIDTH 64
connect \A \src1_i
assign \src_or_imm $91
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel$93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $94
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $95
parameter \WIDTH 1
connect \A \src_l_q_src [1]
assign \src_sel$93 $94
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm$96
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $98
parameter \WIDTH 64
connect \A \src2_i
assign \src_or_imm$96 $97
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0$next
process $group_122
assign \src_r0$next \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0$next \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_123
assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_ra \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_ra \src_r0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1$next
process $group_124
assign \src_r1$next \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel$93 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1$next \src_or_imm$96
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_125
assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel$93 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_rb \src_or_imm$96
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_rb \src_r1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 1 \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 1 \src_r2$next
process $group_126
assign \src_r2$next \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2$next \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_127
assign \alu_xer_so 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_xer_so \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_xer_so \src_r2
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 2 \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 2 \src_r3$next
process $group_128
assign \src_r3$next \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r3$next \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_129
assign \alu_xer_ca 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_xer_ca \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_xer_ca \src_r3
end
assign \alu_p_valid_i \alui_l_q_alui
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
cell $and $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_131
assign \alui_l_r_alui$next \alui_l_r_alui
assign \alui_l_r_alui$next $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alui_l_r_alui$next 1'1
assign \alu_n_ready_i \alu_l_q_alu
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
wire width 1 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_134
assign \alu_l_r_alu$next \alu_l_r_alu
assign \alu_l_r_alu$next $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alu_l_r_alu$next 1'1
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $104
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { \busy_o \busy_o \busy_o \busy_o }
connect \Y $103
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__zero_a
connect \Y $105
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
connect \Y $107
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $110
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { 1'1 1'1 $107 $105 }
connect \Y $109
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $not $112
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rdmaskn
connect \Y $111
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $114
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rd__rel $113
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $115
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $117
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $119
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $121
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $121
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $123
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 5 $125
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $126
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B { $115 $117 $119 $121 $123 }
connect \Y $125
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 5 $127
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $128
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
process $group_139
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 4 \dest2_o
process $group_140
assign \dest2_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 2 \dest3_o
process $group_141
assign \dest3_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 2 \dest4_o
process $group_142
assign \dest4_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 1 \dest5_o
process $group_143
assign \dest5_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [4] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0]
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.p"
module \p$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.n"
module \n$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.pipe.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.p"
module \p$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.pipe.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.n"
module \n$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.pipe.main"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe.main"
module \main$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 input 3 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 4 \op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 5 \op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 6 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 7 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 input 8 \full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 9 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 10 \cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 11 \cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 12 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 output 13 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 output 14 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 output 15 \op__insn$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 16 \op__read_cr_whole$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 17 \op__write_cr_whole$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 18 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 19 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 output 20 \full_cr$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 21 \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 22 \cr_a$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 23 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:47"
wire width 32 \mask
process $group_0
assign \mask 32'00000000000000000000000000000000
assign \mask { { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] } }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 5 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
cell $pos $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \cr_a
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100"
wire width 1 \bit_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:84"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:84"
wire width 2 \bt
process $group_1
assign \cr_a$8 4'0000
assign \cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
assign { \cr_a_ok \cr_a$8 } $9
assign \cr_a_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \cr_a$8 \cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:108"
switch \bt
case 2'00
assign { \cr_a_ok \cr_a$8 } [0] \bit_o
case
assign \cr_a_ok 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:73"
wire width 4 \lut
process $group_3
assign \lut 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \lut \op__insn [9:6]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89"
wire width 3 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89"
cell $sub $13
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect $11 $12
process $group_4
assign \bt 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \bt $11 [1:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:85"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:85"
wire width 2 \ba
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90"
wire width 3 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90"
cell $sub $16
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect $14 $15
process $group_5
assign \ba 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \ba $14 [1:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86"
wire width 2 \bb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91"
wire width 3 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91"
wire width 3 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91"
cell $sub $19
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect $17 $18
process $group_6
assign \bb 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \bb $17 [1:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94"
wire width 1 \bit_a
process $group_7
assign \bit_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:96"
switch \ba
case 2'00
assign \bit_a \cr_a [0]
case 2'--
assign \bit_a \cr_a [3]
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95"
wire width 1 \bit_b
process $group_8
assign \bit_b 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97"
switch \bb
case 2'00
assign \bit_b \cr_b [0]
case 2'--
assign \bit_b \cr_b [3]
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:102"
wire width 1 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:102"
cell $mux $21
parameter \WIDTH 1
connect \A \lut [1]
connect \S \bit_a
connect \Y $20
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103"
cell $mux $23
parameter \WIDTH 1
connect \A \lut [0]
connect \S \bit_a
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103"
cell $mux $25
parameter \WIDTH 1
connect \A $22
end
process $group_9
assign \bit_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
assign \bit_o $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
wire width 32 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
cell $and $27
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \B \mask
connect \Y $26
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
wire width 32 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \A \mask
connect \Y $28
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
wire width 32 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
cell $and $31
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \B $28
connect \Y $30
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
wire width 32 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116"
cell $or $33
parameter \A_SIGNED 0
parameter \A_WIDTH 32
end
process $group_10
assign \full_cr$7 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
assign \full_cr$7 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
end
process $group_11
assign \full_cr_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
assign \full_cr_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124"
wire width 1 \move_one
process $group_12
assign \move_one 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
assign \move_one \op__insn [20]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130"
wire width 64 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130"
wire width 32 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130"
cell $and $36
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \B \mask
connect \Y $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:130"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130"
cell $pos $37
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \A $35
connect \Y $34
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 $38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
cell $pos $39
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \A \full_cr
connect \Y $38
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150"
wire width 65 $40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150"
wire width 64 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:146"
wire width 1 \cr_bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150"
cell $mux $42
parameter \WIDTH 64
connect \A \rb
connect \S \cr_bit
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150"
cell $pos $43
parameter \A_SIGNED 0
parameter \A_WIDTH 64
process $group_13
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128"
switch { \move_one }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128"
case 1'1
assign \o $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132"
case
assign \o $38
end
case
assign \o_ok 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
assign { \o_ok \o } $40
assign \o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154"
switch { \cr_a [2] \cr_a [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154"
case 2'-1
assign \o 64'1111111111111111111111111111111111111111111111111111111111111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:156"
case 2'1-
assign \o 64'0000000000000000000000000000000000000000000000000000000000000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158"
case
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_15
assign \cr_bit 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
attribute \nmigen.decoding "OP_MCRF/42"
case 7'0101010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
attribute \nmigen.decoding "OP_CROP/69"
case 7'1000101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
attribute \nmigen.decoding "OP_MTCRF/48"
case 7'0110000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:120"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
attribute \nmigen.decoding "OP_MFCR/45"
case 7'0101101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
attribute \nmigen.decoding "OP_ISEL/35"
case 7'0100011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:147"
switch { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] } [1:0]
case 2'00
assign \cr_bit \cr_a [3]
case 2'--
assign \cr_bit \cr_a [0]
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/main_stage.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153"
attribute \nmigen.decoding "OP_SETB/59"
case 7'0111011
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu.pipe"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu.pipe"
module \pipe$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 2 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 3 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 4 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 input 6 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 input 7 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 8 \op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 9 \op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 10 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 11 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 input 12 \full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 13 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 14 \cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 15 \cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 16 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 17 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 18 \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$1$next
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 output 19 \op__insn_type$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 output 20 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \op__fn_unit$3$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 output 21 \op__insn$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \op__insn$4$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 22 \op__read_cr_whole$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__read_cr_whole$5$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 23 \op__write_cr_whole$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__write_cr_whole$6$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 24 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 25 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 output 26 \full_cr$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 \full_cr$7$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 27 \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \full_cr_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 28 \cr_a$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$8$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 29 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$next
cell \p$7 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \main_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \main_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \main_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \main_op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \main_op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \main_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \main_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 \main_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \main_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \main_cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \main_cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \main_muxid$9
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \main_op__insn_type$10
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \main_op__fn_unit$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \main_op__insn$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \main_op__read_cr_whole$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \main_op__write_cr_whole$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 \main_full_cr$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \main_cr_a$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_cr_a_ok
cell \main$9 \main
connect \muxid \main_muxid
assign \main_cr_c \cr_c
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:621"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
wire width 1 \p_valid_i$17
process $group_12
assign \p_valid_i$17 1'0
assign \p_valid_i$17 \p_valid_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:619"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
process $group_13
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:620"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
wire width 1 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
cell $and $19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \p_valid_i_p_ready_o $18
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$20
process $group_15
assign \muxid$20 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \op__insn_type$21
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \op__fn_unit$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \op__insn$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__read_cr_whole$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__write_cr_whole$25
process $group_16
assign \op__insn_type$21 7'0000000
assign { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 } { \main_op__write_cr_whole$14 \main_op__read_cr_whole$13 \main_op__insn$12 \main_op__fn_unit$11 \main_op__insn_type$10 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$27
process $group_21
assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \o_ok$27 \o$26 } { \main_o_ok \main_o }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 \full_cr$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \full_cr_ok$29
process $group_23
assign \full_cr$28 32'00000000000000000000000000000000
assign { \full_cr_ok$29 \full_cr$28 } { \main_full_cr_ok \main_full_cr$15 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$31
process $group_25
assign \cr_a$30 4'0000
assign { \cr_a_ok$31 \cr_a$30 } { \main_cr_a_ok \main_cr_a$16 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
process $group_27
assign \r_busy$next \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \r_busy$next 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \r_busy$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \r_busy$next 1'0
end
process $group_28
assign \muxid$1$next \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \muxid$1$next \muxid$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \muxid$1$next \muxid$20
end
assign \op__insn$4$next \op__insn$4
assign \op__read_cr_whole$5$next \op__read_cr_whole$5
assign \op__write_cr_whole$6$next \op__write_cr_whole$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \op__write_cr_whole$6$next \op__read_cr_whole$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \op__write_cr_whole$6$next \op__read_cr_whole$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 }
end
process $group_34
assign \o$next \o
assign \o_ok$next \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \o_ok$next \o$next } { \o_ok$27 \o$26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \o_ok$next \o$next } { \o_ok$27 \o$26 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \o_ok$next 1'0
process $group_36
assign \full_cr$7$next \full_cr$7
assign \full_cr_ok$next \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \full_cr_ok$next 1'0
process $group_38
assign \cr_a$8$next \cr_a$8
assign \cr_a_ok$next \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_a_ok$next 1'0
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu"
module \alu$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 3 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 output 5 \full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 7 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 8 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 9 \n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 input 11 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 input 12 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 13 \op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 14 \op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 15 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 16 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 input 17 \full_cr$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 18 \cr_a$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 19 \cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 20 \cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 21 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 22 \p_ready_o
cell \p$4 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \pipe_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \pipe_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \pipe_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \pipe_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \pipe_op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \pipe_op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 \pipe_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \pipe_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \pipe_cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \pipe_cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \pipe_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \pipe_n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid$3
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \pipe_op__insn_type$4
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \pipe_op__fn_unit$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \pipe_op__insn$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \pipe_op__read_cr_whole$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \pipe_op__write_cr_whole$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 \pipe_full_cr$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \pipe_cr_a$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_cr_a_ok
cell \pipe$6 \pipe
connect \rst \rst
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$11
process $group_16
assign \muxid$11 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \op__insn_type$12
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \op__fn_unit$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \op__insn$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__read_cr_whole$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \op__write_cr_whole$16
process $group_17
assign \op__insn_type$12 7'0000000
connect \muxid 2'00
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.src_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l"
module \src_l$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 6 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 6 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 6 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 6 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 6 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 6 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 6 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 6
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 6'000000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 6 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 6 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 6 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 6 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 6 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 6 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 6 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 6
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.opc_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l"
module \opc_l$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.req_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l"
module \req_l$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 output 2 \q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 input 3 \s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 input 4 \r_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 3'000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \q_req $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \qn_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \qn_req $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 3 \qlq_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.rst_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l"
module \rst_l$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.rok_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l"
module \rok_l$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 3 \s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 4 \r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rdok $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rdok $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alui_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l"
module \alui_l$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alui $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alui $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0.alu_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l"
module \alu_l$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.cr0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.cr0"
module \cr0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 input 3 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 input 4 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 5 \oper_i__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 6 \oper_i__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 7 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 8 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 6 input 9 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 output 10 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 input 11 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 12 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 13 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 32 input 14 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 4 input 15 \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 4 input 16 \src5_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 4 input 17 \src6_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 1 output 18 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 19 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
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wire width 64 output 21 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 22 \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 32 output 23 \full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 24 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 25 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 26 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 27 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 28 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \alu_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \alu_n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \alu_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \alu_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \alu_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \alu_op__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \alu_op__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 32 \alu_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \alu_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \alu_cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \alu_cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \alu_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \alu_p_ready_o
cell \alu$3 \alu
connect \rst \rst
connect \p_valid_i \alu_p_valid_i
connect \p_ready_o \alu_p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 6 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 6 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 6 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 6 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 6 \src_l_q_src
cell \src_l$10 \src_l
connect \rst \rst
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
cell \opc_l$11 \opc_l
connect \rst \rst
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \req_l_q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \req_l_s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \req_l_r_req
cell \req_l$12 \req_l
connect \rst \rst
connect \s_req \req_l_s_req
connect \r_req \req_l_r_req
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
cell \rst_l$13 \rst_l
connect \rst \rst
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rok_l_s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok$next
cell \rok_l$14 \rok_l
connect \rst \rst
connect \s_rdok \rok_l_s_rdok
connect \r_rdok \rok_l_r_rdok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alui_l_q_alui
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui$next
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alui_l_s_alui
cell \alui_l$15 \alui_l
connect \rst \rst
connect \r_alui \alui_l_r_alui
connect \s_alui \alui_l_s_alui
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
cell \alu_l$16 \alu_l
connect \rst \rst
connect \r_alu \alu_l_r_alu
connect \s_alu \alu_l_s_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
wire width 1 \all_rd
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wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rok_l_q_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 6 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \rd__rel
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 6 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $or $7
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B \rd__go
connect \Y $6
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $reduce_and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A $6
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly$next
process $group_1
assign \all_rd_dly$next \all_rd_dly
sync posedge \clk
update \all_rd_dly \all_rd_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
wire width 1 \all_rd_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \all_rd_dly
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd_pulse $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire width 1 \alu_done
process $group_3
assign \alu_done 1'0
assign \alu_done \alu_n_valid_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly$next
process $group_4
assign \alu_done_dly$next \alu_done_dly
sync posedge \clk
update \alu_done_dly \alu_done_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
wire width 1 \alu_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_done_dly
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_pulse $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 3 \alu_pulsem
process $group_6
assign \alu_pulsem 3'000
assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
wire width 3 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_7
assign \prev_wr_go$next \prev_wr_go
assign \prev_wr_go$next $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \prev_wr_go$next 3'000
sync posedge \clk
update \prev_wr_go \prev_wr_go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wrmask
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $reduce_bool $27
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A $25
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $22
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o $29
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wr__go
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \prev_wr_go
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_n_ready_i
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 3 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B \wrmask
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $43
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_ready_i
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_valid_o
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_10
assign \req_done 1'0
assign \req_done $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
case 1'1
assign \req_done 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
wire width 1 \reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
cell $or $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset $55
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \rst_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_r $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 3 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
wire width 3 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \reset_w $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 6 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire width 6 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \rok_l_s_rdok \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
assign \rok_l_r_rdok$next $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \rok_l_r_rdok$next 1'1
process $group_19
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_20
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_21
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 6'000000
process $group_22
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 6'111111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
wire width 3 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_s_req $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
wire width 3 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_r_req $67
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__read_cr_whole$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr_whole$next
process $group_25
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__insn$next \oper_l__insn
assign \oper_l__read_cr_whole$next \oper_l__read_cr_whole
assign \oper_l__write_cr_whole$next \oper_l__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 \oper_r__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 \oper_r__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \oper_r__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 \oper_r__write_cr_whole
process $group_30
assign \oper_r__insn_type 7'0000000
assign \oper_r__insn 32'00000000000000000000000000000000
assign \oper_r__read_cr_whole 1'0
assign \oper_r__write_cr_whole 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_35
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r0_l__o_ok$next 1'0
update \data_r0_l__o \data_r0_l__o$next
update \data_r0_l__o_ok \data_r0_l__o_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r0__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r0__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $72
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_37
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $71 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0__o_ok \data_r0__o } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \data_r1_l__full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \data_r1_l__full_cr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__full_cr_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_39
assign \data_r1_l__full_cr$next \data_r1_l__full_cr
assign \data_r1_l__full_cr_ok$next \data_r1_l__full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \full_cr }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r1_l__full_cr_ok$next 1'0
update \data_r1_l__full_cr \data_r1_l__full_cr$next
update \data_r1_l__full_cr_ok \data_r1_l__full_cr_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 32 \data_r1__full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r1__full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_41
assign \data_r1__full_cr 32'00000000000000000000000000000000
assign \data_r1__full_cr_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1__full_cr_ok \data_r1__full_cr } { \full_cr_ok \full_cr }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r1__full_cr_ok \data_r1__full_cr } { \data_r1_l__full_cr_ok \data_r1_l__full_cr }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r2_l__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r2_l__cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_43
assign \data_r2_l__cr_a$next \data_r2_l__cr_a
assign \data_r2_l__cr_a_ok$next \data_r2_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $77 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r2_l__cr_a_ok$next 1'0
update \data_r2_l__cr_a \data_r2_l__cr_a$next
update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 4 \data_r2__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r2__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_45
assign \data_r2__cr_a 4'0000
assign \data_r2__cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2__cr_a_ok \data_r2__cr_a } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r2__cr_a_ok \data_r2__cr_a } { \data_r2_l__cr_a_ok \data_r2_l__cr_a }
end
assign { \alu_op__write_cr_whole \alu_op__read_cr_whole \alu_op__insn \alu_op__fn_unit \alu_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0$next
process $group_53
assign \src_r0$next \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0$next \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_54
assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_ra \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_ra \src_r0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1$next
process $group_55
assign \src_r1$next \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1$next \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_56
assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_rb \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_rb \src_r1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 32 \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 32 \src_r2$next
process $group_57
assign \src_r2$next \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2$next \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_58
assign \alu_full_cr 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_full_cr \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_full_cr \src_r2
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r3$next
process $group_59
assign \src_r3$next \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r3$next \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_60
assign \alu_cr_a 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_cr_a \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_cr_a \src_r3
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r4$next
process $group_61
assign \src_r4$next \src_r4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [4] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r4$next \src5_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_62
assign \alu_cr_b 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [4] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_cr_b \src5_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_cr_b \src_r4
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r5$next
process $group_63
assign \src_r5$next \src_r5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [5] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r5$next \src6_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_64
assign \alu_cr_c 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [5] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_cr_c \src6_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_cr_c \src_r5
end
assign \alu_p_valid_i \alui_l_q_alui
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
cell $and $82
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_66
assign \alui_l_r_alui$next \alui_l_r_alui
assign \alui_l_r_alui$next $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alui_l_r_alui$next 1'1
assign \alu_n_ready_i \alu_l_q_alu
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
wire width 1 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $84
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_69
assign \alu_l_r_alu$next \alu_l_r_alu
assign \alu_l_r_alu$next $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alu_l_r_alu$next 1'1
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 6 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
connect \Y $85
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 6 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $88
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
connect \Y $87
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 6 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $not $90
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \rdmaskn
connect \Y $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 6 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $92
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \rd__rel $91
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $93
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $96
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $97
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $100
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { $93 $95 $97 }
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_74
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 32 \dest2_o
process $group_75
assign \dest2_o 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 4 \dest3_o
process $group_76
assign \dest3_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0]
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.p"
module \p$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.n"
module \n$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.pipe.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.p"
module \p$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.pipe.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.n"
module \n$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.pipe.main"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe.main"
module \main$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 6 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 input 7 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 8 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 9 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 10 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 11 \cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 12 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 output 13 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 output 14 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 output 15 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 16 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 17 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 18 \op__is_32bit$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 output 19 \op__insn$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 20 \spr1$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 21 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 22 \spr2$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 23 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 24 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 25 \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:69"
wire width 64 \br_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $11
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:68"
wire width 64 \br_imm_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
wire width 65 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
wire width 65 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
cell $add $17
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect $15 $16
process $group_0
assign \br_addr 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
switch { $13 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
case 1'1
assign \br_addr \br_imm_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:75"
case
assign \br_addr $15 [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:86"
wire width 2 \bi
process $group_1
assign \bi 2'00
assign \bi { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:87"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87"
wire width 1 \cr_bit
process $group_2
assign \cr_bit 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89"
switch \bi
case 2'00
assign \cr_bit \cr_a [3]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
wire width 1 \ctr_write
process $group_3
assign \ctr_write 1'0
assign \ctr_write 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
assign \ctr_write 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:96"
wire width 1 \bc_taken
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
wire width 1 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
cell $eq $19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [3]
connect \Y $18
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
wire width 1 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
cell $or $21
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4]
connect \Y $20
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B 1'0
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:118"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:118"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
cell $eq $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $26
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
wire width 1 \ctr_zero_bo1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
wire width 1 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \cr_bit
connect \Y $28
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
wire width 1 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
cell $and $31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $28
connect \Y $30
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
wire width 1 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
cell $and $33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \bc_taken 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
assign \bc_taken $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
switch { $26 $24 $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case 3'--1
assign \bc_taken $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
case 3'-1-
assign \bc_taken $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:118"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
case 3'1--
assign \bc_taken \ctr_zero_bo1
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:101"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:101"
wire width 64 \ctr_n
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
wire width 65 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
wire width 65 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
cell $sub $36
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect $34 $35
process $group_5
assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
assign \ctr_n $34 [63:0]
end
end
process $group_6
assign \spr1$9 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
assign \spr1$9 \ctr_n
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:106"
wire width 64 \ctr_m
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
wire width 64 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
cell $pos $38
parameter \A_SIGNED 0
parameter \A_WIDTH 32
end
process $group_7
assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107"
switch { \op__is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107"
case 1'1
assign \ctr_m $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:109"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109"
case
assign \ctr_m \spr1
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
cell $reduce_or $40
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A \ctr_m
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
cell $xor $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \ctr_zero_bo1 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
case
assign \ctr_zero_bo1 $41
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
cell $not $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [5]
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
assign \br_imm_addr { { { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] } { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \br_imm_addr { { { { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] } { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
switch { $45 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
case 1'1
assign \br_imm_addr { \spr1 [63:2] 2'00 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
case
assign \br_imm_addr { \spr2 [63:2] 2'00 }
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:70"
wire width 1 \br_taken
process $group_10
assign \br_taken 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
assign \br_taken 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \br_taken \bc_taken
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
assign \br_taken \bc_taken
end
process $group_11
assign \spr1_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \spr1_ok \ctr_write
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
assign \spr1_ok \ctr_write
assign \nia_ok \br_taken
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
wire width 65 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
wire width 65 $48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
cell $add $49
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect $47 $48
process $group_14
assign \spr2$10 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
switch { \op__lk }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
case 1'1
assign \spr2$10 $47 [63:0]
end
end
process $group_15
assign \spr2_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
switch { \op__lk }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
case 1'1
assign \spr2_ok 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu.pipe"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu.pipe"
module \pipe$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 2 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 3 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 4 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 input 6 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 9 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 10 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 input 11 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 12 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 13 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 14 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 15 \cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 16 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 17 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 18 \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$1$next
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 output 19 \op__insn_type$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 output 20 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \op__fn_unit$3$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 output 21 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 22 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 23 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__lk$6$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 24 \op__is_32bit$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__is_32bit$7$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 output 25 \op__insn$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \op__insn$8$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 26 \spr1$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \spr1$9$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 27 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \spr1_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 28 \spr2$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \spr2$10$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 29 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \spr2_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 30 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \nia$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 31 \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \nia_ok$next
cell \p$21 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \main_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \main_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \main_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \main_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \main_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \main_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \main_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \main_cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \main_muxid$11
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \main_op__insn_type$12
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \main_op__fn_unit$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \main_op__imm_data__imm$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__imm_data__imm_ok$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__lk$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \main_op__is_32bit$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \main_op__insn$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_spr1$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_spr2$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_nia_ok
cell \main$23 \main
connect \muxid \main_muxid
assign \main_cia \cia
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:621"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
wire width 1 \p_valid_i$21
process $group_12
assign \p_valid_i$21 1'0
assign \p_valid_i$21 \p_valid_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:619"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
process $group_13
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:620"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
cell $and $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \p_valid_i_p_ready_o $22
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$24
process $group_15
assign \muxid$24 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \op__insn_type$25
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \op__fn_unit$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \op__imm_data__imm$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__imm_data__imm_ok$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__lk$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__is_32bit$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \op__insn$31
process $group_16
assign \op__insn_type$25 7'0000000
assign { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 } { \main_op__insn$18 \main_op__is_32bit$17 \main_op__lk$16 { \main_op__imm_data__imm_ok$15 \main_op__imm_data__imm$14 } \main_op__fn_unit$13 \main_op__insn_type$12 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \spr1$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \spr1_ok$33
process $group_23
assign \spr1$32 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \spr1_ok$33 \spr1$32 } { \main_spr1_ok \main_spr1$19 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \spr2$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \spr2_ok$35
process $group_25
assign \spr2$34 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \spr2_ok$35 \spr2$34 } { \main_spr2_ok \main_spr2$20 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \nia$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \nia_ok$37
process $group_27
assign \nia$36 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \nia_ok$37 \nia$36 } { \main_nia_ok \main_nia }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
process $group_29
assign \r_busy$next \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \r_busy$next 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \r_busy$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \r_busy$next 1'0
end
process $group_30
assign \muxid$1$next \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \muxid$1$next \muxid$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \muxid$1$next \muxid$24
end
assign \op__lk$6$next \op__lk$6
assign \op__is_32bit$7$next \op__is_32bit$7
assign \op__insn$8$next \op__insn$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \op__insn$8$next \op__is_32bit$7$next \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \op__insn$8$next \op__is_32bit$7$next \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
process $group_38
assign \spr1$9$next \spr1$9
assign \spr1_ok$next \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \spr1_ok$next \spr1$9$next } { \spr1_ok$33 \spr1$32 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \spr1_ok$next \spr1$9$next } { \spr1_ok$33 \spr1$32 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \spr1_ok$next 1'0
process $group_40
assign \spr2$10$next \spr2$10
assign \spr2_ok$next \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \spr2_ok$next \spr2$10$next } { \spr2_ok$35 \spr2$34 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \spr2_ok$next \spr2$10$next } { \spr2_ok$35 \spr2$34 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \spr2_ok$next 1'0
process $group_42
assign \nia$next \nia
assign \nia_ok$next \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \nia_ok$next \nia$next } { \nia_ok$37 \nia$36 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \nia_ok$next \nia$next } { \nia_ok$37 \nia$36 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \nia_ok$next 1'0
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu"
module \alu$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 3 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 5 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 7 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 8 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 9 \n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 input 11 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 input 12 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 14 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 15 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 input 16 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 17 \spr1$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 18 \spr2$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 input 19 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 20 \cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 21 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 22 \p_ready_o
cell \p$18 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \pipe_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \pipe_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \pipe_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \pipe_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \pipe_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \pipe_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \pipe_n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid$3
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \pipe_op__insn_type$4
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \pipe_op__fn_unit$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \pipe_op__imm_data__imm$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__imm_data__imm_ok$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__lk$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \pipe_op__is_32bit$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \pipe_op__insn$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_spr1$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_spr2$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_nia_ok
cell \pipe$20 \pipe
connect \rst \rst
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$13
process $group_16
assign \muxid$13 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \op__insn_type$14
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \op__fn_unit$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \op__imm_data__imm$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__imm_data__imm_ok$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__lk$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \op__is_32bit$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \op__insn$20
process $group_17
assign \op__insn_type$14 7'0000000
connect \muxid 2'00
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.src_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l"
module \src_l$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 4'0000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 4 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 4 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 4 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.opc_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l"
module \opc_l$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.req_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l"
module \req_l$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 output 2 \q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 input 3 \s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 input 4 \r_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 3'000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \q_req $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \qn_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \qn_req $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 3 \qlq_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.rst_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l"
module \rst_l$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.rok_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l"
module \rok_l$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 3 \s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 4 \r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rdok $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rdok $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alui_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l"
module \alui_l$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alui $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alui $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0.alu_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l"
module \alu_l$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.branch0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.branch0"
module \branch0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 input 3 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 6 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 input 7 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 input 8 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 9 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 10 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 4 input 11 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 12 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 13 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 4 input 14 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 15 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 16 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 17 \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 18 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 19 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 21 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 22 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 23 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 24 \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 25 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 26 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 27 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 28 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \alu_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \alu_n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \alu_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \alu_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \alu_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \alu_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \alu_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \alu_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \alu_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 4 \alu_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \alu_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \alu_p_ready_o
cell \alu$17 \alu
connect \rst \rst
connect \p_valid_i \alu_p_valid_i
connect \p_ready_o \alu_p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 \src_l_q_src
cell \src_l$24 \src_l
connect \rst \rst
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
cell \opc_l$25 \opc_l
connect \rst \rst
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \req_l_q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \req_l_s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \req_l_r_req
cell \req_l$26 \req_l
connect \rst \rst
connect \s_req \req_l_s_req
connect \r_req \req_l_r_req
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
cell \rst_l$27 \rst_l
connect \rst \rst
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rok_l_s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok$next
cell \rok_l$28 \rok_l
connect \rst \rst
connect \s_rdok \rok_l_s_rdok
connect \r_rdok \rok_l_r_rdok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alui_l_q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alui_l_s_alui
cell \alui_l$29 \alui_l
connect \rst \rst
connect \r_alui \alui_l_r_alui
connect \s_alui \alui_l_s_alui
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
cell \alu_l$30 \alu_l
connect \rst \rst
connect \r_alu \alu_l_r_alu
connect \s_alu \alu_l_s_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
wire width 1 \all_rd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rok_l_q_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rd__rel
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $or $7
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \rd__go
connect \Y $6
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $reduce_and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A $6
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly$next
process $group_1
assign \all_rd_dly$next \all_rd_dly
sync posedge \clk
update \all_rd_dly \all_rd_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
wire width 1 \all_rd_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \all_rd_dly
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd_pulse $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire width 1 \alu_done
process $group_3
assign \alu_done 1'0
assign \alu_done \alu_n_valid_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly$next
process $group_4
assign \alu_done_dly$next \alu_done_dly
sync posedge \clk
update \alu_done_dly \alu_done_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
wire width 1 \alu_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_done_dly
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_pulse $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 3 \alu_pulsem
process $group_6
assign \alu_pulsem 3'000
assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
wire width 3 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_7
assign \prev_wr_go$next \prev_wr_go
assign \prev_wr_go$next $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \prev_wr_go$next 3'000
sync posedge \clk
update \prev_wr_go \prev_wr_go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wrmask
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $reduce_bool $27
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A $25
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $22
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o $29
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wr__go
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \prev_wr_go
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_n_ready_i
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 3 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B \wrmask
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $43
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_ready_i
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_valid_o
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_10
assign \req_done 1'0
assign \req_done $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
case 1'1
assign \req_done 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
wire width 1 \reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
cell $or $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset $55
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \rst_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_r $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 3 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
wire width 3 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \reset_w $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 4 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire width 4 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rok_l_s_rdok \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
assign \rok_l_r_rdok$next $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \rok_l_r_rdok$next 1'1
process $group_19
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_20
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_21
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 4'0000
process $group_22
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 4'1111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
wire width 3 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_s_req $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
wire width 3 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_r_req $67
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn$next
process $group_25
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__lk$next \oper_l__lk
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__insn$next \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__insn$next \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 \oper_r__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \oper_r__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 \oper_r__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 \oper_r__insn
process $group_32
assign \oper_r__insn_type 7'0000000
assign \oper_r__lk 1'0
assign \oper_r__is_32bit 1'0
assign \oper_r__insn 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__spr1$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__spr1_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_39
assign \data_r0_l__spr1$next \data_r0_l__spr1
assign \data_r0_l__spr1_ok$next \data_r0_l__spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0_l__spr1_ok$next \data_r0_l__spr1$next } { \spr1_ok \spr1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r0_l__spr1_ok$next 1'0
update \data_r0_l__spr1 \data_r0_l__spr1$next
update \data_r0_l__spr1_ok \data_r0_l__spr1_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r0__spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r0__spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $72
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_41
assign \data_r0__spr1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__spr1_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $71 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0__spr1_ok \data_r0__spr1 } { \spr1_ok \spr1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r0__spr1_ok \data_r0__spr1 } { \data_r0_l__spr1_ok \data_r0_l__spr1 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r1_l__spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r1_l__spr2$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__spr2_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_43
assign \data_r1_l__spr2$next \data_r1_l__spr2
assign \data_r1_l__spr2_ok$next \data_r1_l__spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1_l__spr2_ok$next \data_r1_l__spr2$next } { \spr2_ok \spr2 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r1_l__spr2_ok$next 1'0
update \data_r1_l__spr2 \data_r1_l__spr2$next
update \data_r1_l__spr2_ok \data_r1_l__spr2_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r1__spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r1__spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_45
assign \data_r1__spr2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r1__spr2_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1__spr2_ok \data_r1__spr2 } { \spr2_ok \spr2 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r1__spr2_ok \data_r1__spr2 } { \data_r1_l__spr2_ok \data_r1_l__spr2 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r2_l__nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r2_l__nia$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__nia_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_47
assign \data_r2_l__nia$next \data_r2_l__nia
assign \data_r2_l__nia_ok$next \data_r2_l__nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $77 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \nia }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r2_l__nia_ok$next 1'0
update \data_r2_l__nia \data_r2_l__nia$next
update \data_r2_l__nia_ok \data_r2_l__nia_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r2__nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r2__nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_49
assign \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r2__nia_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2__nia_ok \data_r2__nia } { \nia_ok \nia }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r2__nia_ok \data_r2__nia } { \data_r2_l__nia_ok \data_r2_l__nia }
end
assign { \alu_op__insn \alu_op__is_32bit \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $82
parameter \WIDTH 1
connect \A \src_l_q_src [1]
assign \src_sel $81
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $84
parameter \WIDTH 64
connect \A \src2_i
assign \src_or_imm $83
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0$next
process $group_61
assign \src_r0$next \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0$next \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_62
assign \alu_spr1 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_spr1 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_spr1 \src_r0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1$next
process $group_63
assign \src_r1$next \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1$next \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_64
assign \alu_spr2 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_spr2 \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_spr2 \src_r1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 4 \src_r2$next
process $group_65
assign \src_r2$next \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2$next \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_66
assign \alu_cr_a 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_cr_a \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_cr_a \src_r2
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r3$next
process $group_67
assign \src_r3$next \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r3$next \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_68
assign \alu_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_cia \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_cia \src_r3
end
assign \alu_p_valid_i \alui_l_q_alui
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_70
assign \alui_l_r_alui$next \alui_l_r_alui
assign \alui_l_r_alui$next $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alui_l_r_alui$next 1'1
assign \alu_n_ready_i \alu_l_q_alu
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_73
assign \alu_l_r_alu$next \alu_l_r_alu
assign \alu_l_r_alu$next $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alu_l_r_alu$next 1'1
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $90
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { \busy_o \busy_o \busy_o \busy_o }
connect \Y $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
connect \Y $91
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { 1'1 1'1 $91 1'1 }
connect \Y $93
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $not $96
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rdmaskn
connect \Y $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rd__rel $97
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $101
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $103
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $106
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { $99 $101 $103 }
connect \Y $105
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $108
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_78
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest1_o { \data_r0__spr1_ok \data_r0__spr1 } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest2_o
process $group_79
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest2_o { \data_r1__spr2_ok \data_r1__spr2 } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest3_o
process $group_80
assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0]
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.p"
module \p$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.n"
module \n$33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.p"
module \p$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.n"
module \n$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.input"
-module \input$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe.main"
+module \main$37
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \op__zero_a
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 12 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 13 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 14 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 19 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 20 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 21 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 22 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 23 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 input 3 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 input 4 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 input 5 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 input 6 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 7 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 8 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 9 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 10 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 11 \cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 12 \msr
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 output 13 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 24 \op__insn_type$2
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 output 14 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 10 output 25 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 output 26 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 27 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 28 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 29 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 30 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 31 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 32 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 33 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 34 \op__zero_a$12
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 35 \op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 36 \op__invert_out$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 output 37 \op__write_cr__data$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 38 \op__write_cr__ok$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 39 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 40 \op__is_32bit$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 41 \op__is_signed$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 42 \op__data_len$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 output 43 \op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 44 \ra$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 45 \rb$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:20"
- wire width 64 \a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:24"
- wire width 64 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:24"
- cell $not $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \ra
- connect \Y $24
- end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 output 15 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 output 16 \op__insn$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 output 17 \op__is_32bit$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 output 18 \op__traptype$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 output 19 \op__trapaddr$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 20 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 21 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 22 \spr1$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 23 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 24 \spr2$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 25 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 26 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 27 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 28 \msr$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125"
+ wire width 5 \to
process $group_0
- assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:23"
- switch { \op__invert_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:23"
- case 1'1
- assign \a $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:25"
- case
- assign \a \ra
- end
+ assign \to 5'00000
+ assign \to { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] }
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:129"
+ wire width 64 \a_s
process $group_1
- assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ra$22 \a
+ assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ switch { \op__is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ case 1'1
+ assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141"
+ case
+ assign \a_s \ra
+ end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130"
+ wire width 64 \b_s
process $group_2
- assign \muxid$1 2'00
- assign \muxid$1 \muxid
- sync init
- end
- process $group_3
- assign \op__insn_type$2 7'0000000
- assign \op__fn_unit$3 10'0000000000
- assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__input_carry$13 2'00
- assign \op__invert_out$14 1'0
- assign \op__write_cr__data$15 3'000
- assign \op__write_cr__ok$16 1'0
- assign \op__output_carry$17 1'0
- assign \op__is_32bit$18 1'0
- assign \op__is_signed$19 1'0
- assign \op__data_len$20 4'0000
- assign \op__insn$21 32'00000000000000000000000000000000
- assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
- end
- process $group_23
- assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rb$23 \rb
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.main.bpermd"
-module \bpermd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:54"
- wire width 64 input 0 \rs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:56"
- wire width 64 input 1 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:55"
- wire width 64 output 2 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_0
- process $group_0
- assign \rb64_0 1'0
- assign \rb64_0 \rb [63]
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_1
- process $group_1
- assign \rb64_1 1'0
- assign \rb64_1 \rb [62]
+ assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ switch { \op__is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ case 1'1
+ assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141"
+ case
+ assign \b_s \rb
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_2
- process $group_2
- assign \rb64_2 1'0
- assign \rb64_2 \rb [61]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
+ wire width 64 \a
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ wire width 64 $11
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ cell $pos $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 32
+ parameter \Y_WIDTH 64
+ connect \A \ra [31:0]
+ connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_3
process $group_3
- assign \rb64_3 1'0
- assign \rb64_3 \rb [60]
+ assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ switch { \op__is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ case 1'1
+ assign \a $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141"
+ case
+ assign \a \ra
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133"
+ wire width 64 \b
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ wire width 64 $13
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ cell $pos $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 32
+ parameter \Y_WIDTH 64
+ connect \A \rb [31:0]
+ connect \Y $13
+ end
process $group_4
- assign \rb64_4 1'0
- assign \rb64_4 \rb [59]
+ assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ switch { \op__is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136"
+ case 1'1
+ assign \b $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141"
+ case
+ assign \b \rb
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:148"
+ wire width 1 \lt_s
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+ cell $lt $16
+ parameter \A_SIGNED 1
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 1
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \a_s
+ connect \B \b_s
+ connect \Y $15
+ end
process $group_5
- assign \rb64_5 1'0
- assign \rb64_5 \rb [58]
+ assign \lt_s 1'0
+ assign \lt_s $15
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ wire width 1 \gt_s
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:155"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:155"
+ cell $gt $18
+ parameter \A_SIGNED 1
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 1
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \a_s
+ connect \B \b_s
+ connect \Y $17
+ end
process $group_6
- assign \rb64_6 1'0
- assign \rb64_6 \rb [57]
+ assign \gt_s 1'0
+ assign \gt_s $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150"
+ wire width 1 \lt_u
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156"
+ cell $lt $20
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \a
+ connect \B \b
+ connect \Y $19
+ end
process $group_7
- assign \rb64_7 1'0
- assign \rb64_7 \rb [56]
+ assign \lt_u 1'0
+ assign \lt_u $19
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ wire width 1 \gt_u
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
+ cell $gt $22
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \a
+ connect \B \b
+ connect \Y $21
+ end
process $group_8
- assign \rb64_8 1'0
- assign \rb64_8 \rb [55]
+ assign \gt_u 1'0
+ assign \gt_u $21
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152"
+ wire width 1 \equal
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
+ cell $eq $24
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \a
+ connect \B \b
+ connect \Y $23
+ end
process $group_9
- assign \rb64_9 1'0
- assign \rb64_9 \rb [54]
+ assign \equal 1'0
+ assign \equal $23
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162"
+ wire width 5 \trap_bits
process $group_10
- assign \rb64_10 1'0
- assign \rb64_10 \rb [53]
+ assign \trap_bits 5'00000
+ assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
+ wire width 1 \should_trap
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ wire width 1 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ wire width 5 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ cell $and $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \trap_bits
+ connect \B \to
+ connect \Y $26
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ cell $reduce_or $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A $26
+ connect \Y $25
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ cell $reduce_or $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \op__traptype
+ connect \Y $29
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168"
+ cell $or $32
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $25
+ connect \B $29
+ connect \Y $31
+ end
process $group_11
- assign \rb64_11 1'0
- assign \rb64_11 \rb [52]
+ assign \should_trap 1'0
+ assign \should_trap $31
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ wire width 64 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ wire width 20 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ cell $sshl $35
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 13
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 20
+ connect \A \op__trapaddr
+ connect \B 3'100
+ connect \Y $34
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ cell $pos $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 20
+ parameter \Y_WIDTH 64
+ connect \A $34
+ connect \Y $33
+ end
process $group_12
- assign \rb64_12 1'0
- assign \rb64_12 \rb [51]
+ assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \nia $33
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ assign \nia { { { } \spr1 [63:2] } 2'00 }
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_13
process $group_13
- assign \rb64_13 1'0
- assign \rb64_13 \rb [50]
+ assign \nia_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \nia_ok 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ assign \nia_ok 1'1
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_14
process $group_14
- assign \rb64_14 1'0
- assign \rb64_14 \rb [49]
+ assign \spr1$8 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \spr1$8 \cia
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_15
process $group_15
- assign \rb64_15 1'0
- assign \rb64_15 \rb [48]
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_16
- process $group_16
- assign \rb64_16 1'0
- assign \rb64_16 \rb [47]
+ assign \spr1_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \spr1_ok 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_17
- process $group_17
- assign \rb64_17 1'0
- assign \rb64_17 \rb [46]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178"
+ cell $eq $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \op__traptype
+ connect \B 1'0
+ connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_18
- process $group_18
- assign \rb64_18 1'0
- assign \rb64_18 \rb [45]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ wire width 4 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ cell $and $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 4
+ connect \A \op__traptype
+ connect \B 2'10
+ connect \Y $40
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_19
- process $group_19
- assign \rb64_19 1'0
- assign \rb64_19 \rb [44]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A $40
+ connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_20
- process $group_20
- assign \rb64_20 1'0
- assign \rb64_20 \rb [43]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ wire width 4 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ cell $and $45
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 4
+ connect \A \op__traptype
+ connect \B 1'1
+ connect \Y $44
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_21
- process $group_21
- assign \rb64_21 1'0
- assign \rb64_21 \rb [42]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $46
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A $44
+ connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_22
- process $group_22
- assign \rb64_22 1'0
- assign \rb64_22 \rb [41]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185"
+ wire width 4 $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185"
+ cell $and $49
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \op__traptype
+ connect \B 4'1000
+ connect \Y $48
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_23
- process $group_23
- assign \rb64_23 1'0
- assign \rb64_23 \rb [40]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $50
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A $48
+ connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_24
- process $group_24
- assign \rb64_24 1'0
- assign \rb64_24 \rb [39]
+ process $group_16
+ assign \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr2$9 [15:0] \msr [15:0]
+ assign \spr2$9 [26:22] \msr [26:22]
+ assign \spr2$9 [63:31] \msr [63:31]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178"
+ switch { $37 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178"
+ case 1'1
+ assign \spr2$9 [17] 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ switch { $39 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ case 1'1
+ assign \spr2$9 [18] 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ switch { $43 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ case 1'1
+ assign \spr2$9 [20] 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185"
+ switch { $47 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185"
+ case 1'1
+ assign \spr2$9 [16] 1'1
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_25
- process $group_25
- assign \rb64_25 1'0
- assign \rb64_25 \rb [38]
+ process $group_17
+ assign \spr2_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
+ case 1'1
+ assign \spr2_ok 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_26
- process $group_26
- assign \rb64_26 1'0
- assign \rb64_26 \rb [37]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $52
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \op__insn [22] \op__insn [21] }
+ connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_27
- process $group_27
- assign \rb64_27 1'0
- assign \rb64_27 \rb [36]
+ process $group_18
+ assign \msr$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ switch { $51 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ case 1'1
+ assign \msr$10 [15] \ra [15]
+ assign \msr$10 [1] \ra [1]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
+ case
+ assign \msr$10 [11:1] \ra [11:1]
+ assign \msr$10 [59:13] \ra [59:13]
+ assign \msr$10 [63:61] \ra [63:61]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75"
+ switch { \msr$10 [14] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75"
+ case 1'1
+ assign \msr$10 [15] 1'1
+ assign \msr$10 [5] 1'1
+ assign \msr$10 [4] 1'1
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ assign \msr$10 [15:0] \spr2 [15:0]
+ assign \msr$10 [26:22] \spr2 [26:22]
+ assign \msr$10 [63:31] \spr2 [63:31]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75"
+ switch { \msr$10 [14] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75"
+ case 1'1
+ assign \msr$10 [15] 1'1
+ assign \msr$10 [5] 1'1
+ assign \msr$10 [4] 1'1
+ end
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_28
- process $group_28
- assign \rb64_28 1'0
- assign \rb64_28 \rb [35]
+ process $group_19
+ assign \msr_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ assign \msr_ok 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ assign \msr_ok 1'1
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_29
- process $group_29
- assign \rb64_29 1'0
- assign \rb64_29 \rb [34]
+ process $group_20
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ assign \o \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_30
- process $group_30
- assign \rb64_30 1'0
- assign \rb64_30 \rb [33]
+ process $group_21
+ assign \o_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \nmigen.decoding "OP_TRAP/63"
+ case 7'0111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
+ attribute \nmigen.decoding "OP_MTMSRD/72"
+ case 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204"
+ attribute \nmigen.decoding "OP_MFMSR/71"
+ case 7'1000111
+ assign \o_ok 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_31
- process $group_31
- assign \rb64_31 1'0
- assign \rb64_31 \rb [32]
+ process $group_22
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_32
- process $group_32
- assign \rb64_32 1'0
- assign \rb64_32 \rb [31]
+ process $group_23
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 10'0000000000
+ assign \op__insn$4 32'00000000000000000000000000000000
+ assign \op__is_32bit$5 1'0
+ assign \op__traptype$6 4'0000
+ assign \op__trapaddr$7 13'0000000000000
+ assign { \op__trapaddr$7 \op__traptype$6 \op__is_32bit$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_33
- process $group_33
- assign \rb64_33 1'0
- assign \rb64_33 \rb [30]
- sync init
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu.pipe"
+module \pipe$34
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 input 2 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 output 3 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 input 4 \muxid
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 input 5 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 input 6 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 input 7 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 input 8 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 input 9 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 input 10 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 11 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 12 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 13 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 14 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 15 \cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 16 \msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 output 17 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 input 18 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 output 19 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \muxid$1$next
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 output 20 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \op__insn_type$2$next
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 output 21 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \op__fn_unit$3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 output 22 \op__insn$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \op__insn$4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 output 23 \op__is_32bit$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \op__is_32bit$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 output 24 \op__traptype$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \op__traptype$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 output 25 \op__trapaddr$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \op__trapaddr$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 26 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 27 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 28 \spr1$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \spr1$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \spr1_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 30 \spr2$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \spr2$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 31 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \spr2_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 32 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \nia$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 33 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \nia_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 34 \msr$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \msr$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 35 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \msr_ok$next
+ cell \p$35 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_34
- process $group_34
- assign \rb64_34 1'0
- assign \rb64_34 \rb [29]
- sync init
+ cell \n$36 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_35
- process $group_35
- assign \rb64_35 1'0
- assign \rb64_35 \rb [28]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \main_muxid
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \main_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \main_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \main_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \main_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \main_op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \main_op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \main_msr
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \main_muxid$11
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \main_op__insn_type$12
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \main_op__fn_unit$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \main_op__insn$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \main_op__is_32bit$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \main_op__traptype$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \main_op__trapaddr$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_spr1$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_spr2$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_msr$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_msr_ok
+ cell \main$37 \main
+ connect \muxid \main_muxid
+ connect \op__insn_type \main_op__insn_type
+ connect \op__fn_unit \main_op__fn_unit
+ connect \op__insn \main_op__insn
+ connect \op__is_32bit \main_op__is_32bit
+ connect \op__traptype \main_op__traptype
+ connect \op__trapaddr \main_op__trapaddr
+ connect \ra \main_ra
+ connect \rb \main_rb
+ connect \spr1 \main_spr1
+ connect \spr2 \main_spr2
+ connect \cia \main_cia
+ connect \msr \main_msr
+ connect \muxid$1 \main_muxid$11
+ connect \op__insn_type$2 \main_op__insn_type$12
+ connect \op__fn_unit$3 \main_op__fn_unit$13
+ connect \op__insn$4 \main_op__insn$14
+ connect \op__is_32bit$5 \main_op__is_32bit$15
+ connect \op__traptype$6 \main_op__traptype$16
+ connect \op__trapaddr$7 \main_op__trapaddr$17
+ connect \o \main_o
+ connect \o_ok \main_o_ok
+ connect \spr1$8 \main_spr1$18
+ connect \spr1_ok \main_spr1_ok
+ connect \spr2$9 \main_spr2$19
+ connect \spr2_ok \main_spr2_ok
+ connect \nia \main_nia
+ connect \nia_ok \main_nia_ok
+ connect \msr$10 \main_msr$20
+ connect \msr_ok \main_msr_ok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_36
- process $group_36
- assign \rb64_36 1'0
- assign \rb64_36 \rb [27]
+ process $group_0
+ assign \main_muxid 2'00
+ assign \main_muxid \muxid
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_37
- process $group_37
- assign \rb64_37 1'0
- assign \rb64_37 \rb [26]
+ process $group_1
+ assign \main_op__insn_type 7'0000000
+ assign \main_op__fn_unit 10'0000000000
+ assign \main_op__insn 32'00000000000000000000000000000000
+ assign \main_op__is_32bit 1'0
+ assign \main_op__traptype 4'0000
+ assign \main_op__trapaddr 13'0000000000000
+ assign { \main_op__trapaddr \main_op__traptype \main_op__is_32bit \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_38
- process $group_38
- assign \rb64_38 1'0
- assign \rb64_38 \rb [25]
+ process $group_7
+ assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_ra \ra
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_39
- process $group_39
- assign \rb64_39 1'0
- assign \rb64_39 \rb [24]
+ process $group_8
+ assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_rb \rb
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_40
- process $group_40
- assign \rb64_40 1'0
- assign \rb64_40 \rb [23]
+ process $group_9
+ assign \main_spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_spr1 \spr1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_41
- process $group_41
- assign \rb64_41 1'0
- assign \rb64_41 \rb [22]
+ process $group_10
+ assign \main_spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_spr2 \spr2
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_42
- process $group_42
- assign \rb64_42 1'0
- assign \rb64_42 \rb [21]
+ process $group_11
+ assign \main_cia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_cia \cia
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_43
- process $group_43
- assign \rb64_43 1'0
- assign \rb64_43 \rb [20]
+ process $group_12
+ assign \main_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_msr \msr
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_44
- process $group_44
- assign \rb64_44 1'0
- assign \rb64_44 \rb [19]
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+ wire width 1 \p_valid_i$21
+ process $group_13
+ assign \p_valid_i$21 1'0
+ assign \p_valid_i$21 \p_valid_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_45
- process $group_45
- assign \rb64_45 1'0
- assign \rb64_45 \rb [18]
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+ wire width 1 \n_i_rdy_data
+ process $group_14
+ assign \n_i_rdy_data 1'0
+ assign \n_i_rdy_data \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_46
- process $group_46
- assign \rb64_46 1'0
- assign \rb64_46 \rb [17]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+ wire width 1 \p_valid_i_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ cell $and $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i$21
+ connect \B \p_ready_o
+ connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_47
- process $group_47
- assign \rb64_47 1'0
- assign \rb64_47 \rb [16]
+ process $group_15
+ assign \p_valid_i_p_ready_o 1'0
+ assign \p_valid_i_p_ready_o $22
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_48
- process $group_48
- assign \rb64_48 1'0
- assign \rb64_48 \rb [15]
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \muxid$24
+ process $group_16
+ assign \muxid$24 2'00
+ assign \muxid$24 \main_muxid$11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_49
- process $group_49
- assign \rb64_49 1'0
- assign \rb64_49 \rb [14]
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \op__insn_type$25
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \op__fn_unit$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \op__insn$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \op__is_32bit$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \op__traptype$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \op__trapaddr$30
+ process $group_17
+ assign \op__insn_type$25 7'0000000
+ assign \op__fn_unit$26 10'0000000000
+ assign \op__insn$27 32'00000000000000000000000000000000
+ assign \op__is_32bit$28 1'0
+ assign \op__traptype$29 4'0000
+ assign \op__trapaddr$30 13'0000000000000
+ assign { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } { \main_op__trapaddr$17 \main_op__traptype$16 \main_op__is_32bit$15 \main_op__insn$14 \main_op__fn_unit$13 \main_op__insn_type$12 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_50
- process $group_50
- assign \rb64_50 1'0
- assign \rb64_50 \rb [13]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$32
+ process $group_23
+ assign \o$31 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$32 1'0
+ assign { \o_ok$32 \o$31 } { \main_o_ok \main_o }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_51
- process $group_51
- assign \rb64_51 1'0
- assign \rb64_51 \rb [12]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \spr1$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \spr1_ok$34
+ process $group_25
+ assign \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr1_ok$34 1'0
+ assign { \spr1_ok$34 \spr1$33 } { \main_spr1_ok \main_spr1$18 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_52
- process $group_52
- assign \rb64_52 1'0
- assign \rb64_52 \rb [11]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \spr2$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \spr2_ok$36
+ process $group_27
+ assign \spr2$35 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr2_ok$36 1'0
+ assign { \spr2_ok$36 \spr2$35 } { \main_spr2_ok \main_spr2$19 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_53
- process $group_53
- assign \rb64_53 1'0
- assign \rb64_53 \rb [10]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \nia$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \nia_ok$38
+ process $group_29
+ assign \nia$37 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia_ok$38 1'0
+ assign { \nia_ok$38 \nia$37 } { \main_nia_ok \main_nia }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_54
- process $group_54
- assign \rb64_54 1'0
- assign \rb64_54 \rb [9]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \msr$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \msr_ok$40
+ process $group_31
+ assign \msr$39 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr_ok$40 1'0
+ assign { \msr_ok$40 \msr$39 } { \main_msr_ok \main_msr$20 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_55
- process $group_55
- assign \rb64_55 1'0
- assign \rb64_55 \rb [8]
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy$next
+ process $group_33
+ assign \r_busy$next \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \r_busy$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \r_busy$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \r_busy$next 1'0
+ end
sync init
+ update \r_busy 1'0
+ sync posedge \clk
+ update \r_busy \r_busy$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_56
- process $group_56
- assign \rb64_56 1'0
- assign \rb64_56 \rb [7]
+ process $group_34
+ assign \muxid$1$next \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \muxid$1$next \muxid$24
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \muxid$1$next \muxid$24
+ end
sync init
+ update \muxid$1 2'00
+ sync posedge \clk
+ update \muxid$1 \muxid$1$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_57
- process $group_57
- assign \rb64_57 1'0
- assign \rb64_57 \rb [6]
+ process $group_35
+ assign \op__insn_type$2$next \op__insn_type$2
+ assign \op__fn_unit$3$next \op__fn_unit$3
+ assign \op__insn$4$next \op__insn$4
+ assign \op__is_32bit$5$next \op__is_32bit$5
+ assign \op__traptype$6$next \op__traptype$6
+ assign \op__trapaddr$7$next \op__trapaddr$7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \op__trapaddr$7$next \op__traptype$6$next \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \op__trapaddr$7$next \op__traptype$6$next \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+ end
sync init
+ update \op__insn_type$2 7'0000000
+ update \op__fn_unit$3 10'0000000000
+ update \op__insn$4 32'00000000000000000000000000000000
+ update \op__is_32bit$5 1'0
+ update \op__traptype$6 4'0000
+ update \op__trapaddr$7 13'0000000000000
+ sync posedge \clk
+ update \op__insn_type$2 \op__insn_type$2$next
+ update \op__fn_unit$3 \op__fn_unit$3$next
+ update \op__insn$4 \op__insn$4$next
+ update \op__is_32bit$5 \op__is_32bit$5$next
+ update \op__traptype$6 \op__traptype$6$next
+ update \op__trapaddr$7 \op__trapaddr$7$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_58
- process $group_58
- assign \rb64_58 1'0
- assign \rb64_58 \rb [5]
+ process $group_41
+ assign \o$next \o
+ assign \o_ok$next \o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \o_ok$next \o$next } { \o_ok$32 \o$31 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \o_ok$next \o$next } { \o_ok$32 \o$31 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \o_ok$next 1'0
+ end
sync init
+ update \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \o_ok 1'0
+ sync posedge \clk
+ update \o \o$next
+ update \o_ok \o_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_59
- process $group_59
- assign \rb64_59 1'0
- assign \rb64_59 \rb [4]
+ process $group_43
+ assign \spr1$8$next \spr1$8
+ assign \spr1_ok$next \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \spr1_ok$next \spr1$8$next } { \spr1_ok$34 \spr1$33 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \spr1_ok$next \spr1$8$next } { \spr1_ok$34 \spr1$33 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \spr1_ok$next 1'0
+ end
sync init
+ update \spr1$8 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \spr1_ok 1'0
+ sync posedge \clk
+ update \spr1$8 \spr1$8$next
+ update \spr1_ok \spr1_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_60
- process $group_60
- assign \rb64_60 1'0
- assign \rb64_60 \rb [3]
+ process $group_45
+ assign \spr2$9$next \spr2$9
+ assign \spr2_ok$next \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \spr2_ok$next \spr2$9$next } { \spr2_ok$36 \spr2$35 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \spr2_ok$next \spr2$9$next } { \spr2_ok$36 \spr2$35 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \spr2_ok$next 1'0
+ end
sync init
+ update \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \spr2_ok 1'0
+ sync posedge \clk
+ update \spr2$9 \spr2$9$next
+ update \spr2_ok \spr2_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_61
- process $group_61
- assign \rb64_61 1'0
- assign \rb64_61 \rb [2]
+ process $group_47
+ assign \nia$next \nia
+ assign \nia_ok$next \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \nia_ok$next \nia$next } { \nia_ok$38 \nia$37 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \nia_ok$next \nia$next } { \nia_ok$38 \nia$37 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \nia_ok$next 1'0
+ end
sync init
+ update \nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \nia_ok 1'0
+ sync posedge \clk
+ update \nia \nia$next
+ update \nia_ok \nia_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_62
- process $group_62
- assign \rb64_62 1'0
- assign \rb64_62 \rb [1]
+ process $group_49
+ assign \msr$10$next \msr$10
+ assign \msr_ok$next \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \msr_ok$next \msr$10$next } { \msr_ok$40 \msr$39 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \msr_ok$next \msr$10$next } { \msr_ok$40 \msr$39 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \msr_ok$next 1'0
+ end
sync init
+ update \msr$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \msr_ok 1'0
+ sync posedge \clk
+ update \msr$10 \msr$10$next
+ update \msr_ok \msr_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:61"
- wire width 1 \rb64_63
- process $group_63
- assign \rb64_63 1'0
- assign \rb64_63 \rb [0]
+ process $group_51
+ assign \n_valid_o 1'0
+ assign \n_valid_o \r_busy
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_0
- process $group_64
- assign \idx_0 8'00000000
- assign \idx_0 \rs [7:0]
+ process $group_52
+ assign \p_ready_o 1'0
+ assign \p_ready_o \n_i_rdy_data
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:60"
- wire width 64 \perm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_0
- connect \B 7'1000000
- connect \Y $1
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_1
- connect \B 7'1000000
- connect \Y $3
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_2
- connect \B 7'1000000
- connect \Y $5
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_3
- connect \B 7'1000000
- connect \Y $7
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_4
- connect \B 7'1000000
- connect \Y $9
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_5
- connect \B 7'1000000
- connect \Y $11
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_6
- connect \B 7'1000000
- connect \Y $13
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu"
+module \alu$31
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 2 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 3 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 4 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 5 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 6 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 7 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 8 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 9 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 10 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 11 \msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 output 12 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 input 13 \n_ready_i
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 input 14 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 input 15 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 input 16 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 input 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 input 18 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 input 19 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 20 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 21 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 22 \spr1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 23 \spr2$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 24 \cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 25 \msr$3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 input 26 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 output 27 \p_ready_o
+ cell \p$32 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:67"
- wire width 8 \idx_7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- cell $lt $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \idx_7
- connect \B 7'1000000
- connect \Y $15
+ cell \n$33 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
end
- process $group_65
- assign \perm 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
- switch \idx_0
- case 8'00000000
- assign \perm [0] \rb64_0
- case 8'00000001
- assign \perm [0] \rb64_1
- case 8'00000010
- assign \perm [0] \rb64_2
- case 8'00000011
- assign \perm [0] \rb64_3
- case 8'00000100
- assign \perm [0] \rb64_4
- case 8'00000101
- assign \perm [0] \rb64_5
- case 8'00000110
- assign \perm [0] \rb64_6
- case 8'00000111
- assign \perm [0] \rb64_7
- case 8'00001000
- assign \perm [0] \rb64_8
- case 8'00001001
- assign \perm [0] \rb64_9
- case 8'00001010
- assign \perm [0] \rb64_10
- case 8'00001011
- assign \perm [0] \rb64_11
- case 8'00001100
- assign \perm [0] \rb64_12
- case 8'00001101
- assign \perm [0] \rb64_13
- case 8'00001110
- assign \perm [0] \rb64_14
- case 8'00001111
- assign \perm [0] \rb64_15
- case 8'00010000
- assign \perm [0] \rb64_16
- case 8'00010001
- assign \perm [0] \rb64_17
- case 8'00010010
- assign \perm [0] \rb64_18
- case 8'00010011
- assign \perm [0] \rb64_19
- case 8'00010100
- assign \perm [0] \rb64_20
- case 8'00010101
- assign \perm [0] \rb64_21
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 \pipe_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 \pipe_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \pipe_muxid
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \pipe_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \pipe_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \pipe_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \pipe_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \pipe_op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \pipe_op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \pipe_msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 \pipe_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 \pipe_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \pipe_muxid$4
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \pipe_op__insn_type$5
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \pipe_op__fn_unit$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \pipe_op__insn$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \pipe_op__is_32bit$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \pipe_op__traptype$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \pipe_op__trapaddr$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_spr1$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_spr2$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_msr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_msr_ok
+ cell \pipe$34 \pipe
+ connect \rst \rst
+ connect \clk \clk
+ connect \p_valid_i \pipe_p_valid_i
+ connect \p_ready_o \pipe_p_ready_o
+ connect \muxid \pipe_muxid
+ connect \op__insn_type \pipe_op__insn_type
+ connect \op__fn_unit \pipe_op__fn_unit
+ connect \op__insn \pipe_op__insn
+ connect \op__is_32bit \pipe_op__is_32bit
+ connect \op__traptype \pipe_op__traptype
+ connect \op__trapaddr \pipe_op__trapaddr
+ connect \ra \pipe_ra
+ connect \rb \pipe_rb
+ connect \spr1 \pipe_spr1
+ connect \spr2 \pipe_spr2
+ connect \cia \pipe_cia
+ connect \msr \pipe_msr
+ connect \n_valid_o \pipe_n_valid_o
+ connect \n_ready_i \pipe_n_ready_i
+ connect \muxid$1 \pipe_muxid$4
+ connect \op__insn_type$2 \pipe_op__insn_type$5
+ connect \op__fn_unit$3 \pipe_op__fn_unit$6
+ connect \op__insn$4 \pipe_op__insn$7
+ connect \op__is_32bit$5 \pipe_op__is_32bit$8
+ connect \op__traptype$6 \pipe_op__traptype$9
+ connect \op__trapaddr$7 \pipe_op__trapaddr$10
+ connect \o \pipe_o
+ connect \o_ok \pipe_o_ok
+ connect \spr1$8 \pipe_spr1$11
+ connect \spr1_ok \pipe_spr1_ok
+ connect \spr2$9 \pipe_spr2$12
+ connect \spr2_ok \pipe_spr2_ok
+ connect \nia \pipe_nia
+ connect \nia_ok \pipe_nia_ok
+ connect \msr$10 \pipe_msr$13
+ connect \msr_ok \pipe_msr_ok
+ end
+ process $group_0
+ assign \pipe_p_valid_i 1'0
+ assign \pipe_p_valid_i \p_valid_i
+ sync init
+ end
+ process $group_1
+ assign \p_ready_o 1'0
+ assign \p_ready_o \pipe_p_ready_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \muxid
+ process $group_2
+ assign \pipe_muxid 2'00
+ assign \pipe_muxid \muxid
+ sync init
+ end
+ process $group_3
+ assign \pipe_op__insn_type 7'0000000
+ assign \pipe_op__fn_unit 10'0000000000
+ assign \pipe_op__insn 32'00000000000000000000000000000000
+ assign \pipe_op__is_32bit 1'0
+ assign \pipe_op__traptype 4'0000
+ assign \pipe_op__trapaddr 13'0000000000000
+ assign { \pipe_op__trapaddr \pipe_op__traptype \pipe_op__is_32bit \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_9
+ assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_ra \ra
+ sync init
+ end
+ process $group_10
+ assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_rb \rb
+ sync init
+ end
+ process $group_11
+ assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_spr1 \spr1$1
+ sync init
+ end
+ process $group_12
+ assign \pipe_spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_spr2 \spr2$2
+ sync init
+ end
+ process $group_13
+ assign \pipe_cia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_cia \cia
+ sync init
+ end
+ process $group_14
+ assign \pipe_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_msr \msr$3
+ sync init
+ end
+ process $group_15
+ assign \n_valid_o 1'0
+ assign \n_valid_o \pipe_n_valid_o
+ sync init
+ end
+ process $group_16
+ assign \pipe_n_ready_i 1'0
+ assign \pipe_n_ready_i \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 \muxid$14
+ process $group_17
+ assign \muxid$14 2'00
+ assign \muxid$14 \pipe_muxid$4
+ sync init
+ end
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \op__insn_type$15
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \op__fn_unit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \op__insn$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \op__is_32bit$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \op__traptype$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \op__trapaddr$20
+ process $group_18
+ assign \op__insn_type$15 7'0000000
+ assign \op__fn_unit$16 10'0000000000
+ assign \op__insn$17 32'00000000000000000000000000000000
+ assign \op__is_32bit$18 1'0
+ assign \op__traptype$19 4'0000
+ assign \op__trapaddr$20 13'0000000000000
+ assign { \op__trapaddr$20 \op__traptype$19 \op__is_32bit$18 \op__insn$17 \op__fn_unit$16 \op__insn_type$15 } { \pipe_op__trapaddr$10 \pipe_op__traptype$9 \pipe_op__is_32bit$8 \pipe_op__insn$7 \pipe_op__fn_unit$6 \pipe_op__insn_type$5 }
+ sync init
+ end
+ process $group_24
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok 1'0
+ assign { \o_ok \o } { \pipe_o_ok \pipe_o }
+ sync init
+ end
+ process $group_26
+ assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr1_ok 1'0
+ assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 }
+ sync init
+ end
+ process $group_28
+ assign \spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr2_ok 1'0
+ assign { \spr2_ok \spr2 } { \pipe_spr2_ok \pipe_spr2$12 }
+ sync init
+ end
+ process $group_30
+ assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia_ok 1'0
+ assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia }
+ sync init
+ end
+ process $group_32
+ assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr_ok 1'0
+ assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr$13 }
+ sync init
+ end
+ connect \muxid 2'00
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l"
+module \src_l$38
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 6 input 2 \s_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 6 input 3 \r_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 6 output 4 \q_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 6 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 6 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 6 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \r_src
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 6 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 6 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A $3
+ connect \B \s_src
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 6'000000
+ end
+ sync init
+ update \q_int 6'000000
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 6 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \r_src
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 6 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 6 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A $9
+ connect \B \s_src
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_src 6'000000
+ assign \q_src $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 6 \qn_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 6 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \q_src
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_src 6'000000
+ assign \qn_src $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 6 \qlq_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 6 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \q_src
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_src 6'000000
+ assign \qlq_src $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l"
+module \opc_l$39
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 4 \q_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_opc
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_opc
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_opc
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_opc
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_opc 1'0
+ assign \q_opc $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_opc
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_opc 1'0
+ assign \qn_opc $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_opc
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_opc 1'0
+ assign \qlq_opc $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l"
+module \req_l$40
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 5 output 2 \q_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 5 input 3 \s_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 5 input 4 \r_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 5 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 5 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 5 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \r_req
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 5 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 5 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $3
+ connect \B \s_req
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 5'00000
+ end
+ sync init
+ update \q_int 5'00000
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 5 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \r_req
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 5 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 5 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $9
+ connect \B \s_req
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_req 5'00000
+ assign \q_req $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 5 \qn_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 5 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \q_req
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_req 5'00000
+ assign \qn_req $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 5 \qlq_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 5 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \q_req
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_req 5'00000
+ assign \qlq_req $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l"
+module \rst_l$41
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rst
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_rst
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \q_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rst
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_rst
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_rst 1'0
+ assign \q_rst $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rst
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_rst 1'0
+ assign \qn_rst $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rst
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_rst 1'0
+ assign \qlq_rst $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l"
+module \rok_l$42
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 2 \q_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 3 \s_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \r_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rdok
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_rdok
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rdok
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_rdok
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_rdok 1'0
+ assign \q_rdok $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rdok
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_rdok 1'0
+ assign \qn_rdok $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rdok
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_rdok 1'0
+ assign \qlq_rdok $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l"
+module \alui_l$43
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 2 \q_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 4 \s_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alui
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_alui
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alui
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_alui
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_alui 1'0
+ assign \q_alui $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alui
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_alui 1'0
+ assign \qn_alui $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alui
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_alui 1'0
+ assign \qlq_alui $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l"
+module \alu_l$44
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 2 \q_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 4 \s_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alu
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_alu
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alu
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_alu
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_alu 1'0
+ assign \q_alu $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alu
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_alu 1'0
+ assign \qn_alu $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alu
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_alu 1'0
+ assign \qlq_alu $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.trap0"
+module \trap0
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 input 2 \oper_i__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 input 3 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 input 4 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 input 5 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 input 6 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 input 7 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 input 8 \issue_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 9 \busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
+ wire width 6 input 10 \rdmaskn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 11 \rd__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 input 12 \rd__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 13 \src1_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 14 \src2_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 15 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 16 \src4_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 17 \src5_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 18 \src6_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 19 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 20 \wr__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 input 21 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 22 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 23 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 24 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 25 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 26 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 27 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 28 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 30 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 31 \go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 32 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 33 \dest1_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 \alu_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 \alu_n_ready_i
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \alu_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \alu_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \alu_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \alu_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \alu_op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \alu_op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 \alu_msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 \alu_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 \alu_p_ready_o
+ cell \alu$31 \alu
+ connect \rst \rst
+ connect \clk \clk
+ connect \o_ok \o_ok
+ connect \o \o
+ connect \spr1_ok \spr1_ok
+ connect \spr1 \spr1
+ connect \spr2_ok \spr2_ok
+ connect \spr2 \spr2
+ connect \nia_ok \nia_ok
+ connect \nia \nia
+ connect \msr_ok \msr_ok
+ connect \msr \msr
+ connect \n_valid_o \alu_n_valid_o
+ connect \n_ready_i \alu_n_ready_i
+ connect \op__insn_type \alu_op__insn_type
+ connect \op__fn_unit \alu_op__fn_unit
+ connect \op__insn \alu_op__insn
+ connect \op__is_32bit \alu_op__is_32bit
+ connect \op__traptype \alu_op__traptype
+ connect \op__trapaddr \alu_op__trapaddr
+ connect \ra \alu_ra
+ connect \rb \alu_rb
+ connect \spr1$1 \alu_spr1
+ connect \spr2$2 \alu_spr2
+ connect \cia \alu_cia
+ connect \msr$3 \alu_msr
+ connect \p_valid_i \alu_p_valid_i
+ connect \p_ready_o \alu_p_ready_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 6 \src_l_s_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 6 \src_l_s_src$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 6 \src_l_r_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 6 \src_l_r_src$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 6 \src_l_q_src
+ cell \src_l$38 \src_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_src \src_l_s_src
+ connect \r_src \src_l_r_src
+ connect \q_src \src_l_q_src
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \opc_l_s_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \opc_l_s_opc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \opc_l_r_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \opc_l_r_opc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \opc_l_q_opc
+ cell \opc_l$39 \opc_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_opc \opc_l_s_opc
+ connect \r_opc \opc_l_r_opc
+ connect \q_opc \opc_l_q_opc
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 5 \req_l_q_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 5 \req_l_s_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 5 \req_l_r_req
+ cell \req_l$40 \req_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_req \req_l_q_req
+ connect \s_req \req_l_s_req
+ connect \r_req \req_l_r_req
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \rst_l_s_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \rst_l_r_rst
+ cell \rst_l$41 \rst_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_rst \rst_l_s_rst
+ connect \r_rst \rst_l_r_rst
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \rok_l_q_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \rok_l_s_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \rok_l_r_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \rok_l_r_rdok$next
+ cell \rok_l$42 \rok_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_rdok \rok_l_q_rdok
+ connect \s_rdok \rok_l_s_rdok
+ connect \r_rdok \rok_l_r_rdok
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alui_l_q_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alui_l_r_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alui_l_r_alui$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \alui_l_s_alui
+ cell \alui_l$43 \alui_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_alui \alui_l_q_alui
+ connect \r_alui \alui_l_r_alui
+ connect \s_alui \alui_l_s_alui
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alu_l_q_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alu_l_r_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alu_l_r_alu$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \alu_l_s_alu
+ cell \alu_l$44 \alu_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_alu \alu_l_q_alu
+ connect \r_alu \alu_l_r_alu
+ connect \s_alu \alu_l_s_alu
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
+ wire width 1 \all_rd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \rok_l_q_rdok
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ wire width 6 $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ cell $not $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \rd__rel
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ wire width 6 $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ cell $or $7
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A $4
+ connect \B \rd__go
+ connect \Y $6
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ cell $reduce_and $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 1
+ connect \A $6
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $1
+ connect \B $3
+ connect \Y $9
+ end
+ process $group_0
+ assign \all_rd 1'0
+ assign \all_rd $9
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
+ wire width 1 \all_rd_dly
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
+ wire width 1 \all_rd_dly$next
+ process $group_1
+ assign \all_rd_dly$next \all_rd_dly
+ assign \all_rd_dly$next \all_rd
+ sync init
+ update \all_rd_dly 1'0
+ sync posedge \clk
+ update \all_rd_dly \all_rd_dly$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+ wire width 1 \all_rd_pulse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
+ cell $not $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \all_rd_dly
+ connect \Y $11
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
+ cell $and $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \all_rd
+ connect \B $11
+ connect \Y $13
+ end
+ process $group_2
+ assign \all_rd_pulse 1'0
+ assign \all_rd_pulse $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+ wire width 1 \alu_done
+ process $group_3
+ assign \alu_done 1'0
+ assign \alu_done \alu_n_valid_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+ wire width 1 \alu_done_dly
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+ wire width 1 \alu_done_dly$next
+ process $group_4
+ assign \alu_done_dly$next \alu_done_dly
+ assign \alu_done_dly$next \alu_done
+ sync init
+ update \alu_done_dly 1'0
+ sync posedge \clk
+ update \alu_done_dly \alu_done_dly$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+ wire width 1 \alu_pulse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+ cell $not $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_done_dly
+ connect \Y $15
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+ cell $and $18
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_done
+ connect \B $15
+ connect \Y $17
+ end
+ process $group_5
+ assign \alu_pulse 1'0
+ assign \alu_pulse $17
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+ wire width 5 \alu_pulsem
+ process $group_6
+ assign \alu_pulsem 5'00000
+ assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+ wire width 5 \prev_wr_go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+ wire width 5 \prev_wr_go$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
+ wire width 5 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
+ cell $and $20
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \wr__go
+ connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o }
+ connect \Y $19
+ end
+ process $group_7
+ assign \prev_wr_go$next \prev_wr_go
+ assign \prev_wr_go$next $19
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \prev_wr_go$next 5'00000
+ end
+ sync init
+ update \prev_wr_go 5'00000
+ sync posedge \clk
+ update \prev_wr_go \prev_wr_go$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
+ wire width 1 \done_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ wire width 5 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
+ wire width 5 \wrmask
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ cell $not $24
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \wrmask
+ connect \Y $23
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ wire width 5 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ cell $and $26
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \wr__rel
+ connect \B $23
+ connect \Y $25
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ cell $reduce_bool $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A $25
+ connect \Y $22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ cell $not $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $22
+ connect \Y $21
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
+ cell $and $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B $21
+ connect \Y $29
+ end
+ process $group_8
+ assign \done_o 1'0
+ assign \done_o $29
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
+ wire width 1 \wr_any
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $reduce_bool $32
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \wr__go
+ connect \Y $31
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $reduce_bool $34
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \prev_wr_go
+ connect \Y $33
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $or $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $31
+ connect \B $33
+ connect \Y $35
+ end
+ process $group_9
+ assign \wr_any 1'0
+ assign \wr_any $35
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+ wire width 1 \req_done
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ cell $not $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_n_ready_i
+ connect \Y $37
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ cell $and $40
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_any
+ connect \B $37
+ connect \Y $39
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ wire width 5 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ cell $and $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \req_l_q_req
+ connect \B \wrmask
+ connect \Y $41
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ cell $eq $44
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $41
+ connect \B 1'0
+ connect \Y $43
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ wire width 1 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ cell $and $46
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $39
+ connect \B $43
+ connect \Y $45
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ cell $eq $48
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrmask
+ connect \B 1'0
+ connect \Y $47
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ wire width 1 $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ cell $and $50
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $47
+ connect \B \alu_n_ready_i
+ connect \Y $49
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ cell $and $52
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $49
+ connect \B \alu_n_valid_o
+ connect \Y $51
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ wire width 1 $53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ cell $and $54
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $51
+ connect \B \busy_o
+ connect \Y $53
+ end
+ process $group_10
+ assign \req_done 1'0
+ assign \req_done $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ switch { $53 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
+ case 1'1
+ assign \req_done 1'1
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+ wire width 1 \reset
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+ wire width 1 $55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+ cell $or $56
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \req_done
+ connect \B \go_die_i
+ connect \Y $55
+ end
+ process $group_11
+ assign \reset 1'0
+ assign \reset $55
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+ wire width 1 \rst_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+ wire width 1 $57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+ cell $or $58
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \issue_i
+ connect \B \go_die_i
+ connect \Y $57
+ end
+ process $group_12
+ assign \rst_r 1'0
+ assign \rst_r $57
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+ wire width 5 \reset_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+ wire width 5 $59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+ cell $or $60
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \wr__go
+ connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+ connect \Y $59
+ end
+ process $group_13
+ assign \reset_w 5'00000
+ assign \reset_w $59
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+ wire width 6 \reset_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+ wire width 6 $61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+ cell $or $62
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \rd__go
+ connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+ connect \Y $61
+ end
+ process $group_14
+ assign \reset_r 6'000000
+ assign \reset_r $61
+ sync init
+ end
+ process $group_15
+ assign \rok_l_s_rdok 1'0
+ assign \rok_l_s_rdok \issue_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
+ wire width 1 $63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
+ cell $and $64
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_n_valid_o
+ connect \B \busy_o
+ connect \Y $63
+ end
+ process $group_16
+ assign \rok_l_r_rdok$next \rok_l_r_rdok
+ assign \rok_l_r_rdok$next $63
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \rok_l_r_rdok$next 1'1
+ end
+ sync init
+ update \rok_l_r_rdok 1'1
+ sync posedge \clk
+ update \rok_l_r_rdok \rok_l_r_rdok$next
+ end
+ process $group_17
+ assign \rst_l_s_rst 1'0
+ assign \rst_l_s_rst \all_rd
+ sync init
+ end
+ process $group_18
+ assign \rst_l_r_rst 1'1
+ assign \rst_l_r_rst \rst_r
+ sync init
+ end
+ process $group_19
+ assign \opc_l_s_opc$next \opc_l_s_opc
+ assign \opc_l_s_opc$next \issue_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \opc_l_s_opc$next 1'0
+ end
+ sync init
+ update \opc_l_s_opc 1'0
+ sync posedge \clk
+ update \opc_l_s_opc \opc_l_s_opc$next
+ end
+ process $group_20
+ assign \opc_l_r_opc$next \opc_l_r_opc
+ assign \opc_l_r_opc$next \req_done
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \opc_l_r_opc$next 1'1
+ end
+ sync init
+ update \opc_l_r_opc 1'1
+ sync posedge \clk
+ update \opc_l_r_opc \opc_l_r_opc$next
+ end
+ process $group_21
+ assign \src_l_s_src$next \src_l_s_src
+ assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \src_l_s_src$next 6'000000
+ end
+ sync init
+ update \src_l_s_src 6'000000
+ sync posedge \clk
+ update \src_l_s_src \src_l_s_src$next
+ end
+ process $group_22
+ assign \src_l_r_src$next \src_l_r_src
+ assign \src_l_r_src$next \reset_r
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \src_l_r_src$next 6'111111
+ end
+ sync init
+ update \src_l_r_src 6'111111
+ sync posedge \clk
+ update \src_l_r_src \src_l_r_src$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
+ wire width 5 $65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
+ cell $and $66
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \alu_pulsem
+ connect \B \wrmask
+ connect \Y $65
+ end
+ process $group_23
+ assign \req_l_s_req 5'00000
+ assign \req_l_s_req $65
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+ wire width 5 $67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+ cell $or $68
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \reset_w
+ connect \B \prev_wr_go
+ connect \Y $67
+ end
+ process $group_24
+ assign \req_l_r_req 5'11111
+ assign \req_l_r_req $67
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 7 \oper_l__insn_type
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 7 \oper_l__insn_type$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 10 \oper_l__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 10 \oper_l__fn_unit$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 32 \oper_l__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 32 \oper_l__insn$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \oper_l__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \oper_l__is_32bit$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 4 \oper_l__traptype
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 4 \oper_l__traptype$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 13 \oper_l__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 13 \oper_l__trapaddr$next
+ process $group_25
+ assign \oper_l__insn_type$next \oper_l__insn_type
+ assign \oper_l__fn_unit$next \oper_l__fn_unit
+ assign \oper_l__insn$next \oper_l__insn
+ assign \oper_l__is_32bit$next \oper_l__is_32bit
+ assign \oper_l__traptype$next \oper_l__traptype
+ assign \oper_l__trapaddr$next \oper_l__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \issue_i }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \oper_l__insn_type 7'0000000
+ update \oper_l__fn_unit 10'0000000000
+ update \oper_l__insn 32'00000000000000000000000000000000
+ update \oper_l__is_32bit 1'0
+ update \oper_l__traptype 4'0000
+ update \oper_l__trapaddr 13'0000000000000
+ sync posedge \clk
+ update \oper_l__insn_type \oper_l__insn_type$next
+ update \oper_l__fn_unit \oper_l__fn_unit$next
+ update \oper_l__insn \oper_l__insn$next
+ update \oper_l__is_32bit \oper_l__is_32bit$next
+ update \oper_l__traptype \oper_l__traptype$next
+ update \oper_l__trapaddr \oper_l__trapaddr$next
+ end
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 \oper_r__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 \oper_r__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 \oper_r__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 \oper_r__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 \oper_r__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 \oper_r__trapaddr
+ process $group_31
+ assign \oper_r__insn_type 7'0000000
+ assign \oper_r__fn_unit 10'0000000000
+ assign \oper_r__insn 32'00000000000000000000000000000000
+ assign \oper_r__is_32bit 1'0
+ assign \oper_r__traptype 4'0000
+ assign \oper_r__trapaddr 13'0000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \issue_i }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r0_l__o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r0_l__o$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r0_l__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r0_l__o_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $69
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $70
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $69
+ end
+ process $group_37
+ assign \data_r0_l__o$next \data_r0_l__o
+ assign \data_r0_l__o_ok$next \data_r0_l__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $69 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r0_l__o_ok$next 1'0
+ end
+ sync init
+ update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r0_l__o_ok 1'0
+ sync posedge \clk
+ update \data_r0_l__o \data_r0_l__o$next
+ update \data_r0_l__o_ok \data_r0_l__o_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 64 \data_r0__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 1 \data_r0__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $71
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $72
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $71
+ end
+ process $group_39
+ assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r0__o_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $71 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r0__o_ok \data_r0__o } { \o_ok \o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r1_l__spr1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r1_l__spr1$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r1_l__spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r1_l__spr1_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $74
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $73
+ end
+ process $group_41
+ assign \data_r1_l__spr1$next \data_r1_l__spr1
+ assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $73 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \spr1 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r1_l__spr1_ok$next 1'0
+ end
+ sync init
+ update \data_r1_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r1_l__spr1_ok 1'0
+ sync posedge \clk
+ update \data_r1_l__spr1 \data_r1_l__spr1$next
+ update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 64 \data_r1__spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 1 \data_r1__spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $75
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $76
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $75
+ end
+ process $group_43
+ assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r1__spr1_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $75 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r1__spr1_ok \data_r1__spr1 } { \spr1_ok \spr1 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \data_r1__spr1_ok \data_r1__spr1 } { \data_r1_l__spr1_ok \data_r1_l__spr1 }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r2_l__spr2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r2_l__spr2$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r2_l__spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r2_l__spr2_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $78
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $77
+ end
+ process $group_45
+ assign \data_r2_l__spr2$next \data_r2_l__spr2
+ assign \data_r2_l__spr2_ok$next \data_r2_l__spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $77 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r2_l__spr2_ok$next \data_r2_l__spr2$next } { \spr2_ok \spr2 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r2_l__spr2_ok$next 1'0
+ end
+ sync init
+ update \data_r2_l__spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r2_l__spr2_ok 1'0
+ sync posedge \clk
+ update \data_r2_l__spr2 \data_r2_l__spr2$next
+ update \data_r2_l__spr2_ok \data_r2_l__spr2_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 64 \data_r2__spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 1 \data_r2__spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $80
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $79
+ end
+ process $group_47
+ assign \data_r2__spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r2__spr2_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $79 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r2__spr2_ok \data_r2__spr2 } { \spr2_ok \spr2 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \data_r2__spr2_ok \data_r2__spr2 } { \data_r2_l__spr2_ok \data_r2_l__spr2 }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r3_l__nia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r3_l__nia$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r3_l__nia_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r3_l__nia_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $81
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $82
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $81
+ end
+ process $group_49
+ assign \data_r3_l__nia$next \data_r3_l__nia
+ assign \data_r3_l__nia_ok$next \data_r3_l__nia_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $81 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \nia }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r3_l__nia_ok$next 1'0
+ end
+ sync init
+ update \data_r3_l__nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r3_l__nia_ok 1'0
+ sync posedge \clk
+ update \data_r3_l__nia \data_r3_l__nia$next
+ update \data_r3_l__nia_ok \data_r3_l__nia_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 64 \data_r3__nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 1 \data_r3__nia_ok
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $84
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $83
+ end
+ process $group_51
+ assign \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r3__nia_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $83 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r3__nia_ok \data_r3__nia } { \nia_ok \nia }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \data_r3__nia_ok \data_r3__nia } { \data_r3_l__nia_ok \data_r3_l__nia }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r4_l__msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 64 \data_r4_l__msr$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r4_l__msr_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
+ wire width 1 \data_r4_l__msr_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $86
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $85
+ end
+ process $group_53
+ assign \data_r4_l__msr$next \data_r4_l__msr
+ assign \data_r4_l__msr_ok$next \data_r4_l__msr_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $85 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \msr }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r4_l__msr_ok$next 1'0
+ end
+ sync init
+ update \data_r4_l__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r4_l__msr_ok 1'0
+ sync posedge \clk
+ update \data_r4_l__msr \data_r4_l__msr$next
+ update \data_r4_l__msr_ok \data_r4_l__msr_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 64 \data_r4__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
+ wire width 1 \data_r4__msr_ok
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $87
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $88
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $87
+ end
+ process $group_55
+ assign \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r4__msr_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { $87 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { \data_r4__msr_ok \data_r4__msr } { \msr_ok \msr }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { \data_r4__msr_ok \data_r4__msr } { \data_r4_l__msr_ok \data_r4_l__msr }
+ end
+ sync init
+ end
+ process $group_57
+ assign \wrmask 5'00000
+ assign \wrmask { \data_r4__msr_ok \data_r3__nia_ok \data_r2__spr2_ok \data_r1__spr1_ok \data_r0__o_ok }
+ sync init
+ end
+ process $group_58
+ assign \alu_op__insn_type 7'0000000
+ assign \alu_op__fn_unit 10'0000000000
+ assign \alu_op__insn 32'00000000000000000000000000000000
+ assign \alu_op__is_32bit 1'0
+ assign \alu_op__traptype 4'0000
+ assign \alu_op__trapaddr 13'0000000000000
+ assign { \alu_op__trapaddr \alu_op__traptype \alu_op__is_32bit \alu_op__insn \alu_op__fn_unit \alu_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r0$next
+ process $group_64
+ assign \src_r0$next \src_r0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [0] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r0$next \src1_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r0 \src_r0$next
+ end
+ process $group_65
+ assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [0] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_ra \src1_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_ra \src_r0
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r1$next
+ process $group_66
+ assign \src_r1$next \src_r1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [1] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r1$next \src2_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r1 \src_r1$next
+ end
+ process $group_67
+ assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [1] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_rb \src2_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_rb \src_r1
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r2$next
+ process $group_68
+ assign \src_r2$next \src_r2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [2] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r2$next \src3_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r2 \src_r2$next
+ end
+ process $group_69
+ assign \alu_spr1 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [2] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_spr1 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_spr1 \src_r2
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r3$next
+ process $group_70
+ assign \src_r3$next \src_r3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [3] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r3$next \src4_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r3 \src_r3$next
+ end
+ process $group_71
+ assign \alu_spr2 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [3] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_spr2 \src4_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_spr2 \src_r3
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r4$next
+ process $group_72
+ assign \src_r4$next \src_r4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [4] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r4$next \src5_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r4 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r4 \src_r4$next
+ end
+ process $group_73
+ assign \alu_cia 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [4] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_cia \src5_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_cia \src_r4
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 64 \src_r5$next
+ process $group_74
+ assign \src_r5$next \src_r5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [5] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \src_r5$next \src6_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ sync init
+ update \src_r5 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r5 \src_r5$next
+ end
+ process $group_75
+ assign \alu_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \src_l_q_src [5] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \alu_msr \src6_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign \alu_msr \src_r5
+ end
+ sync init
+ end
+ process $group_76
+ assign \alu_p_valid_i 1'0
+ assign \alu_p_valid_i \alui_l_q_alui
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
+ cell $and $90
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_p_ready_o
+ connect \B \alui_l_q_alui
+ connect \Y $89
+ end
+ process $group_77
+ assign \alui_l_r_alui$next \alui_l_r_alui
+ assign \alui_l_r_alui$next $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \alui_l_r_alui$next 1'1
+ end
+ sync init
+ update \alui_l_r_alui 1'1
+ sync posedge \clk
+ update \alui_l_r_alui \alui_l_r_alui$next
+ end
+ process $group_78
+ assign \alui_l_s_alui 1'0
+ assign \alui_l_s_alui \all_rd_pulse
+ sync init
+ end
+ process $group_79
+ assign \alu_n_ready_i 1'0
+ assign \alu_n_ready_i \alu_l_q_alu
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
+ wire width 1 $91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
+ cell $and $92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_n_valid_o
+ connect \B \alu_l_q_alu
+ connect \Y $91
+ end
+ process $group_80
+ assign \alu_l_r_alu$next \alu_l_r_alu
+ assign \alu_l_r_alu$next $91
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \alu_l_r_alu$next 1'1
+ end
+ sync init
+ update \alu_l_r_alu 1'1
+ sync posedge \clk
+ update \alu_l_r_alu \alu_l_r_alu$next
+ end
+ process $group_81
+ assign \alu_l_s_alu 1'0
+ assign \alu_l_s_alu \all_rd_pulse
+ sync init
+ end
+ process $group_82
+ assign \busy_o 1'0
+ assign \busy_o \opc_l_q_opc
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ wire width 6 $93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ cell $and $94
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \src_l_q_src
+ connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
+ connect \Y $93
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ wire width 6 $95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ cell $and $96
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A $93
+ connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
+ connect \Y $95
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ wire width 6 $97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ cell $not $98
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \rdmaskn
+ connect \Y $97
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ wire width 6 $99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
+ cell $and $100
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A $95
+ connect \B $97
+ connect \Y $99
+ end
+ process $group_83
+ assign \rd__rel 6'000000
+ assign \rd__rel $99
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ wire width 1 $101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ cell $and $102
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $101
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ wire width 1 $103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ cell $and $104
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $103
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ wire width 1 $105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ cell $and $106
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $105
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ wire width 1 $107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ cell $and $108
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $107
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ wire width 1 $109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
+ cell $and $110
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $109
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 5 $111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $112
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A \req_l_q_req
+ connect \B { $101 $103 $105 $107 $109 }
+ connect \Y $111
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 5 $113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $114
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 5
+ connect \A $111
+ connect \B \wrmask
+ connect \Y $113
+ end
+ process $group_84
+ assign \wr__rel 5'00000
+ assign \wr__rel $113
+ sync init
+ end
+ process $group_85
+ assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ switch { \wr__go [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ case 1'1
+ assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 \dest2_o
+ process $group_86
+ assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ switch { \wr__go [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ case 1'1
+ assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 \dest3_o
+ process $group_87
+ assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ switch { \wr__go [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ case 1'1
+ assign \dest3_o { \data_r2__spr2_ok \data_r2__spr2 } [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 \dest4_o
+ process $group_88
+ assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ switch { \wr__go [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ case 1'1
+ assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 \dest5_o
+ process $group_89
+ assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ switch { \wr__go [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
+ case 1'1
+ assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0]
+ end
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.p"
+module \p$46
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.n"
+module \n$47
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.p"
+module \p$49
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.n"
+module \n$50
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.input"
+module \input$51
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 7 input 1 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 10 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 5 \op__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 6 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 7 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 8 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 9 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 10 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 11 \op__zero_a
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 2 input 12 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 13 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 3 input 14 \op__write_cr__data
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 15 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 16 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 18 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 4 input 19 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 32 input 20 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 21 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 input 22 \rb
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ wire width 2 output 23 \muxid$1
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 7 output 24 \op__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 10 output 25 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 64 output 26 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 27 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 28 \op__lk$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 29 \op__rc__rc$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 30 \op__rc__rc_ok$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 31 \op__oe__oe$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 32 \op__oe__oe_ok$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 33 \op__invert_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 34 \op__zero_a$12
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 2 output 35 \op__input_carry$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 36 \op__invert_out$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 3 output 37 \op__write_cr__data$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 38 \op__write_cr__ok$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 39 \op__output_carry$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 40 \op__is_32bit$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 41 \op__is_signed$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 4 output 42 \op__data_len$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 32 output 43 \op__insn$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 output 44 \ra$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ wire width 64 output 45 \rb$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
+ wire width 64 \a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+ wire width 64 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+ cell $not $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \ra
+ connect \Y $24
+ end
+ process $group_0
+ assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+ switch { \op__invert_a }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+ case 1'1
+ assign \a $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
+ case
+ assign \a \ra
+ end
+ sync init
+ end
+ process $group_1
+ assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$22 \a
+ sync init
+ end
+ process $group_2
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_3
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 10'0000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__lk$6 1'0
+ assign \op__rc__rc$7 1'0
+ assign \op__rc__rc_ok$8 1'0
+ assign \op__oe__oe$9 1'0
+ assign \op__oe__oe_ok$10 1'0
+ assign \op__invert_a$11 1'0
+ assign \op__zero_a$12 1'0
+ assign \op__input_carry$13 2'00
+ assign \op__invert_out$14 1'0
+ assign \op__write_cr__data$15 3'000
+ assign \op__write_cr__ok$16 1'0
+ assign \op__output_carry$17 1'0
+ assign \op__is_32bit$18 1'0
+ assign \op__is_signed$19 1'0
+ assign \op__data_len$20 4'0000
+ assign \op__insn$21 32'00000000000000000000000000000000
+ assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_23
+ assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$23 \rb
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.bpermd"
+module \bpermd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54"
+ wire width 64 input 0 \rs
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56"
+ wire width 64 input 1 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55"
+ wire width 64 output 2 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_0
+ process $group_0
+ assign \rb64_0 1'0
+ assign \rb64_0 \rb [63]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_1
+ process $group_1
+ assign \rb64_1 1'0
+ assign \rb64_1 \rb [62]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_2
+ process $group_2
+ assign \rb64_2 1'0
+ assign \rb64_2 \rb [61]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_3
+ process $group_3
+ assign \rb64_3 1'0
+ assign \rb64_3 \rb [60]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_4
+ process $group_4
+ assign \rb64_4 1'0
+ assign \rb64_4 \rb [59]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_5
+ process $group_5
+ assign \rb64_5 1'0
+ assign \rb64_5 \rb [58]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_6
+ process $group_6
+ assign \rb64_6 1'0
+ assign \rb64_6 \rb [57]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_7
+ process $group_7
+ assign \rb64_7 1'0
+ assign \rb64_7 \rb [56]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_8
+ process $group_8
+ assign \rb64_8 1'0
+ assign \rb64_8 \rb [55]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_9
+ process $group_9
+ assign \rb64_9 1'0
+ assign \rb64_9 \rb [54]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_10
+ process $group_10
+ assign \rb64_10 1'0
+ assign \rb64_10 \rb [53]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_11
+ process $group_11
+ assign \rb64_11 1'0
+ assign \rb64_11 \rb [52]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_12
+ process $group_12
+ assign \rb64_12 1'0
+ assign \rb64_12 \rb [51]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_13
+ process $group_13
+ assign \rb64_13 1'0
+ assign \rb64_13 \rb [50]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_14
+ process $group_14
+ assign \rb64_14 1'0
+ assign \rb64_14 \rb [49]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_15
+ process $group_15
+ assign \rb64_15 1'0
+ assign \rb64_15 \rb [48]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_16
+ process $group_16
+ assign \rb64_16 1'0
+ assign \rb64_16 \rb [47]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_17
+ process $group_17
+ assign \rb64_17 1'0
+ assign \rb64_17 \rb [46]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_18
+ process $group_18
+ assign \rb64_18 1'0
+ assign \rb64_18 \rb [45]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_19
+ process $group_19
+ assign \rb64_19 1'0
+ assign \rb64_19 \rb [44]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_20
+ process $group_20
+ assign \rb64_20 1'0
+ assign \rb64_20 \rb [43]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_21
+ process $group_21
+ assign \rb64_21 1'0
+ assign \rb64_21 \rb [42]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_22
+ process $group_22
+ assign \rb64_22 1'0
+ assign \rb64_22 \rb [41]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_23
+ process $group_23
+ assign \rb64_23 1'0
+ assign \rb64_23 \rb [40]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_24
+ process $group_24
+ assign \rb64_24 1'0
+ assign \rb64_24 \rb [39]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_25
+ process $group_25
+ assign \rb64_25 1'0
+ assign \rb64_25 \rb [38]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_26
+ process $group_26
+ assign \rb64_26 1'0
+ assign \rb64_26 \rb [37]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_27
+ process $group_27
+ assign \rb64_27 1'0
+ assign \rb64_27 \rb [36]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_28
+ process $group_28
+ assign \rb64_28 1'0
+ assign \rb64_28 \rb [35]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_29
+ process $group_29
+ assign \rb64_29 1'0
+ assign \rb64_29 \rb [34]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_30
+ process $group_30
+ assign \rb64_30 1'0
+ assign \rb64_30 \rb [33]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_31
+ process $group_31
+ assign \rb64_31 1'0
+ assign \rb64_31 \rb [32]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_32
+ process $group_32
+ assign \rb64_32 1'0
+ assign \rb64_32 \rb [31]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_33
+ process $group_33
+ assign \rb64_33 1'0
+ assign \rb64_33 \rb [30]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_34
+ process $group_34
+ assign \rb64_34 1'0
+ assign \rb64_34 \rb [29]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_35
+ process $group_35
+ assign \rb64_35 1'0
+ assign \rb64_35 \rb [28]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_36
+ process $group_36
+ assign \rb64_36 1'0
+ assign \rb64_36 \rb [27]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_37
+ process $group_37
+ assign \rb64_37 1'0
+ assign \rb64_37 \rb [26]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_38
+ process $group_38
+ assign \rb64_38 1'0
+ assign \rb64_38 \rb [25]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_39
+ process $group_39
+ assign \rb64_39 1'0
+ assign \rb64_39 \rb [24]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_40
+ process $group_40
+ assign \rb64_40 1'0
+ assign \rb64_40 \rb [23]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_41
+ process $group_41
+ assign \rb64_41 1'0
+ assign \rb64_41 \rb [22]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_42
+ process $group_42
+ assign \rb64_42 1'0
+ assign \rb64_42 \rb [21]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_43
+ process $group_43
+ assign \rb64_43 1'0
+ assign \rb64_43 \rb [20]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_44
+ process $group_44
+ assign \rb64_44 1'0
+ assign \rb64_44 \rb [19]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_45
+ process $group_45
+ assign \rb64_45 1'0
+ assign \rb64_45 \rb [18]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_46
+ process $group_46
+ assign \rb64_46 1'0
+ assign \rb64_46 \rb [17]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_47
+ process $group_47
+ assign \rb64_47 1'0
+ assign \rb64_47 \rb [16]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_48
+ process $group_48
+ assign \rb64_48 1'0
+ assign \rb64_48 \rb [15]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_49
+ process $group_49
+ assign \rb64_49 1'0
+ assign \rb64_49 \rb [14]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_50
+ process $group_50
+ assign \rb64_50 1'0
+ assign \rb64_50 \rb [13]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_51
+ process $group_51
+ assign \rb64_51 1'0
+ assign \rb64_51 \rb [12]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_52
+ process $group_52
+ assign \rb64_52 1'0
+ assign \rb64_52 \rb [11]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_53
+ process $group_53
+ assign \rb64_53 1'0
+ assign \rb64_53 \rb [10]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_54
+ process $group_54
+ assign \rb64_54 1'0
+ assign \rb64_54 \rb [9]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_55
+ process $group_55
+ assign \rb64_55 1'0
+ assign \rb64_55 \rb [8]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_56
+ process $group_56
+ assign \rb64_56 1'0
+ assign \rb64_56 \rb [7]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_57
+ process $group_57
+ assign \rb64_57 1'0
+ assign \rb64_57 \rb [6]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_58
+ process $group_58
+ assign \rb64_58 1'0
+ assign \rb64_58 \rb [5]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_59
+ process $group_59
+ assign \rb64_59 1'0
+ assign \rb64_59 \rb [4]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_60
+ process $group_60
+ assign \rb64_60 1'0
+ assign \rb64_60 \rb [3]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_61
+ process $group_61
+ assign \rb64_61 1'0
+ assign \rb64_61 \rb [2]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_62
+ process $group_62
+ assign \rb64_62 1'0
+ assign \rb64_62 \rb [1]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61"
+ wire width 1 \rb64_63
+ process $group_63
+ assign \rb64_63 1'0
+ assign \rb64_63 \rb [0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_0
+ process $group_64
+ assign \idx_0 8'00000000
+ assign \idx_0 \rs [7:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60"
+ wire width 64 \perm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_0
+ connect \B 7'1000000
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_1
+ connect \B 7'1000000
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_2
+ connect \B 7'1000000
+ connect \Y $5
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_3
+ connect \B 7'1000000
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_4
+ connect \B 7'1000000
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_5
+ connect \B 7'1000000
+ connect \Y $11
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_6
+ connect \B 7'1000000
+ connect \Y $13
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67"
+ wire width 8 \idx_7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ cell $lt $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \idx_7
+ connect \B 7'1000000
+ connect \Y $15
+ end
+ process $group_65
+ assign \perm 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ switch { $1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
+ switch \idx_0
+ case 8'00000000
+ assign \perm [0] \rb64_0
+ case 8'00000001
+ assign \perm [0] \rb64_1
+ case 8'00000010
+ assign \perm [0] \rb64_2
+ case 8'00000011
+ assign \perm [0] \rb64_3
+ case 8'00000100
+ assign \perm [0] \rb64_4
+ case 8'00000101
+ assign \perm [0] \rb64_5
+ case 8'00000110
+ assign \perm [0] \rb64_6
+ case 8'00000111
+ assign \perm [0] \rb64_7
+ case 8'00001000
+ assign \perm [0] \rb64_8
+ case 8'00001001
+ assign \perm [0] \rb64_9
+ case 8'00001010
+ assign \perm [0] \rb64_10
+ case 8'00001011
+ assign \perm [0] \rb64_11
+ case 8'00001100
+ assign \perm [0] \rb64_12
+ case 8'00001101
+ assign \perm [0] \rb64_13
+ case 8'00001110
+ assign \perm [0] \rb64_14
+ case 8'00001111
+ assign \perm [0] \rb64_15
+ case 8'00010000
+ assign \perm [0] \rb64_16
+ case 8'00010001
+ assign \perm [0] \rb64_17
+ case 8'00010010
+ assign \perm [0] \rb64_18
+ case 8'00010011
+ assign \perm [0] \rb64_19
+ case 8'00010100
+ assign \perm [0] \rb64_20
+ case 8'00010101
+ assign \perm [0] \rb64_21
case 8'00010110
assign \perm [0] \rb64_22
case 8'00010111
assign \perm [0] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_1
case 8'00000000
assign \perm [1] \rb64_0
assign \perm [1] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_2
case 8'00000000
assign \perm [2] \rb64_0
assign \perm [2] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $7 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_3
case 8'00000000
assign \perm [3] \rb64_0
assign \perm [3] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $9 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_4
case 8'00000000
assign \perm [4] \rb64_0
assign \perm [4] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $11 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_5
case 8'00000000
assign \perm [5] \rb64_0
assign \perm [5] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $13 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_6
case 8'00000000
assign \perm [6] \rb64_0
assign \perm [6] \rb64_63
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/bpermd.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70"
switch \idx_7
case 8'00000000
assign \perm [7] \rb64_0
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.main.popcount"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.popcount"
module \popcount
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:27"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27"
wire width 64 input 0 \a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29"
wire width 64 input 1 \data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30"
wire width 64 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $3
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_0 $1 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_1 $4 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $9
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_2 $7 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $12
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_3 $10 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $15
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_4 $13 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $18
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_5 $16 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $21
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_6 $19 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $24
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_7 $22 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $27
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_8 $25 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $30
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_9 $28 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $33
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_10 $31 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 3 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $36
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \pop_2_11 $34 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 2 \pop_2_12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
wire width 3 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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sync init
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sync init
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sync init
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sync init
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sync init
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sync init
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sync init
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sync init
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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cell $add $159
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \pop_4_4 $157 [3:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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cell $add $162
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \pop_4_5 $160 [3:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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cell $add $165
parameter \A_SIGNED 0
parameter \A_WIDTH 4
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sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 4 \pop_4_7
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wire width 5 $167
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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cell $add $168
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \pop_4_7 $166 [3:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 5 \pop_5_0
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wire width 6 $169
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $170
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $171
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \pop_5_0 $169 [4:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 5 \pop_5_1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $172
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $173
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $174
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \pop_5_1 $172 [4:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 5 \pop_5_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $175
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $176
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $177
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \pop_5_2 $175 [4:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 5 \pop_5_3
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wire width 6 $178
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 6 $179
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $180
parameter \A_SIGNED 0
parameter \A_WIDTH 5
assign \pop_5_3 $178 [4:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 6 \pop_6_0
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wire width 7 $181
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 7 $182
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $183
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \pop_6_0 $181 [5:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 6 \pop_6_1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 7 $184
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 7 $185
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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cell $add $186
parameter \A_SIGNED 0
parameter \A_WIDTH 6
assign \pop_6_1 $184 [5:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 7 \pop_7_0
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wire width 8 $187
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
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wire width 8 $188
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53"
cell $add $189
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \pop_7_0 $187 [6:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:55"
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wire width 1 $190
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55"
cell $eq $191
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B 1'1
connect \Y $190
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:59"
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wire width 1 $192
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59"
cell $eq $193
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B 3'100
connect \Y $192
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $194
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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cell $pos $195
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_0
connect \Y $194
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $196
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $197
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_1
connect \Y $196
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $198
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $199
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_2
connect \Y $198
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $200
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $201
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_3
connect \Y $200
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $202
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $203
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_4
connect \Y $202
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 8 $204
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $205
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_5
connect \Y $204
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
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wire width 8 $206
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $207
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_6
connect \Y $206
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 8 $208
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $209
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \pop_4_7
connect \Y $208
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 32 $210
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $211
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \pop_6_0
connect \Y $210
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 32 $212
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $213
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \pop_6_1
connect \Y $212
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
wire width 64 $214
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21"
cell $pos $215
parameter \A_SIGNED 0
parameter \A_WIDTH 7
end
process $group_63
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55"
switch { $192 $190 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55"
case 2'-1
assign \o [7:0] $194
assign \o [15:8] $196
assign \o [47:40] $204
assign \o [55:48] $206
assign \o [63:56] $208
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59"
case 2'1-
assign \o [31:0] $210
assign \o [63:32] $212
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:63"
case
assign \o $214
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.main.clz"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main.clz"
module \clz
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:11"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11"
wire width 64 input 0 \sig_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:13"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13"
wire width 7 output 1 \lz
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair0
process $group_0
assign \pair0 2'00
assign \pair0 \sig_in [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_0
process $group_1
assign \cnt_1_0 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_0 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_0 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_0 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair2
process $group_2
assign \pair2 2'00
assign \pair2 \sig_in [3:2]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_1
process $group_3
assign \cnt_1_1 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_1 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_1 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_1 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair4
process $group_4
assign \pair4 2'00
assign \pair4 \sig_in [5:4]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_2
process $group_5
assign \cnt_1_2 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_2 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_2 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_2 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair6
process $group_6
assign \pair6 2'00
assign \pair6 \sig_in [7:6]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_3
process $group_7
assign \cnt_1_3 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_3 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_3 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_3 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair8
process $group_8
assign \pair8 2'00
assign \pair8 \sig_in [9:8]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_4
process $group_9
assign \cnt_1_4 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_4 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_4 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_4 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair10
process $group_10
assign \pair10 2'00
assign \pair10 \sig_in [11:10]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_5
process $group_11
assign \cnt_1_5 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_5 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_5 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_5 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair12
process $group_12
assign \pair12 2'00
assign \pair12 \sig_in [13:12]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_6
process $group_13
assign \cnt_1_6 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_6 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_6 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_6 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair14
process $group_14
assign \pair14 2'00
assign \pair14 \sig_in [15:14]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_7
process $group_15
assign \cnt_1_7 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_7 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_7 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_7 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair16
process $group_16
assign \pair16 2'00
assign \pair16 \sig_in [17:16]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_8
process $group_17
assign \cnt_1_8 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_8 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_8 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_8 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair18
process $group_18
assign \pair18 2'00
assign \pair18 \sig_in [19:18]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_9
process $group_19
assign \cnt_1_9 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_9 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_9 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_9 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair20
process $group_20
assign \pair20 2'00
assign \pair20 \sig_in [21:20]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_10
process $group_21
assign \cnt_1_10 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_10 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_10 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_10 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair22
process $group_22
assign \pair22 2'00
assign \pair22 \sig_in [23:22]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_11
process $group_23
assign \cnt_1_11 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_11 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_11 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_11 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair24
process $group_24
assign \pair24 2'00
assign \pair24 \sig_in [25:24]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_12
process $group_25
assign \cnt_1_12 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_12 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_12 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_12 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair26
process $group_26
assign \pair26 2'00
assign \pair26 \sig_in [27:26]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_13
process $group_27
assign \cnt_1_13 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_13 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_13 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_13 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair28
process $group_28
assign \pair28 2'00
assign \pair28 \sig_in [29:28]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_14
process $group_29
assign \cnt_1_14 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_14 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_14 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_14 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair30
process $group_30
assign \pair30 2'00
assign \pair30 \sig_in [31:30]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_15
process $group_31
assign \cnt_1_15 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_15 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_15 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_15 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair32
process $group_32
assign \pair32 2'00
assign \pair32 \sig_in [33:32]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_16
process $group_33
assign \cnt_1_16 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_16 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_16 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_16 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair34
process $group_34
assign \pair34 2'00
assign \pair34 \sig_in [35:34]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_17
process $group_35
assign \cnt_1_17 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_17 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_17 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_17 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair36
process $group_36
assign \pair36 2'00
assign \pair36 \sig_in [37:36]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_18
process $group_37
assign \cnt_1_18 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_18 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_18 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_18 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair38
process $group_38
assign \pair38 2'00
assign \pair38 \sig_in [39:38]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_19
process $group_39
assign \cnt_1_19 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_19 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_19 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_19 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair40
process $group_40
assign \pair40 2'00
assign \pair40 \sig_in [41:40]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_20
process $group_41
assign \cnt_1_20 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_20 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_20 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_20 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair42
process $group_42
assign \pair42 2'00
assign \pair42 \sig_in [43:42]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_21
process $group_43
assign \cnt_1_21 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_21 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_21 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_21 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair44
process $group_44
assign \pair44 2'00
assign \pair44 \sig_in [45:44]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_22
process $group_45
assign \cnt_1_22 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_22 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_22 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_22 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair46
process $group_46
assign \pair46 2'00
assign \pair46 \sig_in [47:46]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_23
process $group_47
assign \cnt_1_23 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_23 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_23 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_23 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair48
process $group_48
assign \pair48 2'00
assign \pair48 \sig_in [49:48]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_24
process $group_49
assign \cnt_1_24 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_24 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_24 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_24 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair50
process $group_50
assign \pair50 2'00
assign \pair50 \sig_in [51:50]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_25
process $group_51
assign \cnt_1_25 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_25 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_25 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_25 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair52
process $group_52
assign \pair52 2'00
assign \pair52 \sig_in [53:52]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_26
process $group_53
assign \cnt_1_26 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_26 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_26 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_26 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair54
process $group_54
assign \pair54 2'00
assign \pair54 \sig_in [55:54]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_27
process $group_55
assign \cnt_1_27 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_27 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_27 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_27 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair56
process $group_56
assign \pair56 2'00
assign \pair56 \sig_in [57:56]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_28
process $group_57
assign \cnt_1_28 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_28 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_28 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_28 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair58
process $group_58
assign \pair58 2'00
assign \pair58 \sig_in [59:58]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_29
process $group_59
assign \cnt_1_29 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_29 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_29 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_29 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair60
process $group_60
assign \pair60 2'00
assign \pair60 \sig_in [61:60]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_30
process $group_61
assign \cnt_1_30 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_30 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_30 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_30 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:24"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24"
wire width 2 \pair62
process $group_62
assign \pair62 2'00
assign \pair62 \sig_in [63:62]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:27"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27"
wire width 2 \cnt_1_31
process $group_63
assign \cnt_1_31 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28"
switch \pair62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:29"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29"
case 2'00
assign \cnt_1_31 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:31"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31"
case 2'01
assign \cnt_1_31 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33"
case
assign \cnt_1_31 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_64
assign \cnt_2_0 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_0 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_0 $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_0 { 1'0 \cnt_1_1 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $12
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_65
assign \cnt_2_2 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $7 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $9 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_2 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_2 $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_2 { 1'0 \cnt_1_3 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $18
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_66
assign \cnt_2_4 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $13 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_4 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_4 $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_4 { 1'0 \cnt_1_5 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $24
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_67
assign \cnt_2_6 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $21 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_6 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_6 $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_6 { 1'0 \cnt_1_7 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $26
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $27
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $30
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_68
assign \cnt_2_8 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $25 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $27 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_8 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_8 $29
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_8 { 1'0 \cnt_1_9 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $36
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_69
assign \cnt_2_10 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_10 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_10 $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_10 { 1'0 \cnt_1_11 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $42
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_70
assign \cnt_2_12 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $37 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $39 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_12 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_12 $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_12 { 1'0 \cnt_1_13 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $48
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_71
assign \cnt_2_14 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $43 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $45 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_14 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_14 $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_14 { 1'0 \cnt_1_15 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $54
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_72
assign \cnt_2_16 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $49 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $51 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_16 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_16 $53
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_16 { 1'0 \cnt_1_17 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $55
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $57
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $60
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_73
assign \cnt_2_18 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $55 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $57 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_18 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_18 $59
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_18 { 1'0 \cnt_1_19 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $61
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $63
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $66
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_74
assign \cnt_2_20 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $61 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $63 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_20 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_20 $65
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_20 { 1'0 \cnt_1_21 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $67
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $69
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $72
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_75
assign \cnt_2_22 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $67 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_22 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_22 $71
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_22 { 1'0 \cnt_1_23 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $73
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $75
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $78
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_76
assign \cnt_2_24 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_24 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_24 $77
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_24 { 1'0 \cnt_1_25 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $79
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $82
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $81
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $84
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_77
assign \cnt_2_26 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $81 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_26 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_26 $83
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_26 { 1'0 \cnt_1_27 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $85
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $87
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $90
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_78
assign \cnt_2_28 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $85 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $87 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_28 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_28 $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_28 { 1'0 \cnt_1_29 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 3 \cnt_2_30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $91
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $93
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 3 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $96
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
process $group_79
assign \cnt_2_30 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $91 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $93 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_2_30 { 1'1 { 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_2_30 $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_2_30 { 1'0 \cnt_1_31 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $97
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $102
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_80
assign \cnt_3_0 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $97 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $99 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_0 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_0 $101
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_0 { 1'0 \cnt_2_2 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $103
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $105
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $108
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_81
assign \cnt_3_2 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $103 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $105 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_2 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_2 $107
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_2 { 1'0 \cnt_2_6 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $109
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $111
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $114
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_82
assign \cnt_3_4 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $109 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $111 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_4 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_4 $113
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_4 { 1'0 \cnt_2_10 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $115
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $117
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $120
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_83
assign \cnt_3_6 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $115 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $117 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_6 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_6 $119
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_6 { 1'0 \cnt_2_14 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $121
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $121
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $123
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $125
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $126
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_84
assign \cnt_3_8 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $121 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $123 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_8 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_8 $125
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_8 { 1'0 \cnt_2_18 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $127
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $127
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $129
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $129
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $131
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $132
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_85
assign \cnt_3_10 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $127 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $129 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_10 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_10 $131
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_10 { 1'0 \cnt_2_22 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $133
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $133
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $135
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $135
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $137
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $138
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_86
assign \cnt_3_12 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $133 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $135 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_12 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_12 $137
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_12 { 1'0 \cnt_2_26 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 4 \cnt_3_14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $139
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $139
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $141
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $141
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 4 $143
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $144
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_87
assign \cnt_3_14 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $139 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $141 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_3_14 { 1'1 { 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_3_14 $143
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_3_14 { 1'0 \cnt_2_30 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 5 \cnt_4_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $145
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $146
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $145
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $147
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $147
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 5 $149
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $150
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_88
assign \cnt_4_0 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $145 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $147 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_4_0 { 1'1 { 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_4_0 $149
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_4_0 { 1'0 \cnt_3_2 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 5 \cnt_4_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $151
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $151
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $153
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $153
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 5 $155
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $156
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_89
assign \cnt_4_2 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $151 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $153 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_4_2 { 1'1 { 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_4_2 $155
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_4_2 { 1'0 \cnt_3_6 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 5 \cnt_4_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $157
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $157
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $159
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $159
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 5 $161
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $162
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_90
assign \cnt_4_4 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $157 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $159 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_4_4 { 1'1 { 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_4_4 $161
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_4_4 { 1'0 \cnt_3_10 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 5 \cnt_4_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $163
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $164
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $163
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $165
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $166
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $165
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 5 $167
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $168
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_91
assign \cnt_4_6 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $163 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $165 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_4_6 { 1'1 { 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_4_6 $167
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_4_6 { 1'0 \cnt_3_14 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 6 \cnt_5_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $169
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $170
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $169
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $171
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $172
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $171
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 6 $173
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $174
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
process $group_92
assign \cnt_5_0 6'000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $169 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $171 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_5_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_5_0 $173
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_5_0 { 1'0 \cnt_4_2 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 6 \cnt_5_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $175
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $176
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $175
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $177
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $178
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $177
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 6 $179
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $180
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
process $group_93
assign \cnt_5_2 6'000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $175 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $177 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_5_2 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_5_2 $179
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_5_2 { 1'0 \cnt_4_6 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:53"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53"
wire width 7 \cnt_6_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
wire width 1 $181
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
cell $eq $182
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $181
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
wire width 1 $183
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
cell $eq $184
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $183
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
wire width 7 $185
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59"
cell $pos $186
parameter \A_SIGNED 0
parameter \A_WIDTH 6
end
process $group_94
assign \cnt_6_0 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
switch { $181 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
switch { $183 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:56"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56"
case 1'1
assign \cnt_6_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 1'0 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58"
case
assign \cnt_6_0 $185
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60"
case
assign \cnt_6_0 { 1'0 \cnt_5_2 }
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.main"
-module \main$38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main"
+module \main$52
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 11 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 input 12 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 13 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 input 14 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 15 \op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 17 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 18 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 input 19 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 input 20 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 21 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 22 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 23 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 output 24 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 output 25 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 output 26 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 27 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 28 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 29 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 30 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 31 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 32 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 33 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 34 \op__zero_a$12
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 output 35 \op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 36 \op__invert_out$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 output 37 \op__write_cr__data$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 38 \op__write_cr__ok$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 39 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 40 \op__is_32bit$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 41 \op__is_signed$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 output 42 \op__data_len$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 output 43 \op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 44 \o
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end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
wire width 1 $156
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
cell $eq $157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $156
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
wire width 64 $158
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:75"
wire width 1 \par0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:76"
wire width 1 \par1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
wire width 1 $159
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
cell $xor $160
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \par1
connect \Y $159
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
cell $pos $161
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $159
connect \Y $158
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
wire width 64 $162
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
wire width 8 $163
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
cell $sub $164
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 6'100000
connect \Y $163
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:13"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13"
wire width 8 $165
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/clz.py:13"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13"
cell $pos $166
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \A \clz_lz
connect \Y $165
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
wire width 8 $167
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
cell $mux $168
parameter \WIDTH 8
connect \A $165
connect \S \op__is_32bit
connect \Y $167
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
cell $pos $169
parameter \A_SIGNED 0
parameter \A_WIDTH 8
assign \o_ok 1'0
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
assign \o $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
assign \o $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
assign \o $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
assign \o { { $140 $142 $144 $146 $148 $150 $152 $154 } { $124 $126 $128 $130 $132 $134 $136 $138 } { $108 $110 $112 $114 $116 $118 $120 $122 } { $92 $94 $96 $98 $100 $102 $104 $106 } { $76 $78 $80 $82 $84 $86 $88 $90 } { $60 $62 $64 $66 $68 $70 $72 $74 } { $44 $46 $48 $50 $52 $54 $56 $58 } { $28 $30 $32 $34 $36 $38 $40 $42 } }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
assign \o \popcount_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
switch { $156 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
case 1'1
assign \o $158
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
case
assign { \o_ok \o } [0] \par0
assign { \o_ok \o } [32] \par1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
assign \o $162
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
assign \o \bpermd_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
assign \o_ok 1'0
end
process $group_2
assign \popcount_a 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
assign \popcount_a \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/popcount.py:28"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28"
wire width 64 \b
process $group_3
assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
assign \b \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 $170
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
cell $pos $171
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_4
assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
assign \popcount_data_len $170
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
wire width 1 $172
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
cell $reduce_xor $173
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_5
assign \par0 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
assign \par0 $172
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:78"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
wire width 1 $174
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:78"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
cell $reduce_xor $175
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
process $group_6
assign \par1 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
assign \par1 $174
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:88"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
wire width 1 \count_right
process $group_7
assign \count_right 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
assign \count_right { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [9]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:92"
wire width 32 \a32
process $group_8
assign \a32 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
assign \a32 \ra [31:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:91"
wire width 64 \cntz_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
wire width 64 $176
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
wire width 32 $177
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
cell $mux $178
parameter \WIDTH 32
connect \A \a32
connect \S \count_right
connect \Y $177
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
cell $pos $179
parameter \A_SIGNED 0
parameter \A_WIDTH 32
connect \A $177
connect \Y $176
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
wire width 64 $180
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:98"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
cell $mux $181
parameter \WIDTH 64
connect \A \ra
end
process $group_9
assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:95"
switch { \op__is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:95"
case 1'1
assign \cntz_i $176
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97"
case
assign \cntz_i $180
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
end
process $group_10
assign \clz_sig_in 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
assign \clz_sig_in \cntz_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
end
process $group_11
assign \bpermd_rs 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
assign \bpermd_rs \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
end
process $group_12
assign \bpermd_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
assign \bpermd_rb \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/main_stage.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
attribute \nmigen.decoding ""
case
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe.output"
-module \output$39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.output"
+module \output$53
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 5 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 6 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 8 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 10 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 11 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 input 12 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 13 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 input 14 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 15 \op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 17 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 18 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 input 19 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 input 20 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 21 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 22 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 input 23 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 input 24 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 25 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 output 26 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 output 27 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 output 28 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 29 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 30 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 31 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 32 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 33 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 34 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 35 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 36 \op__zero_a$12
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 output 37 \op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 38 \op__invert_out$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 output 39 \op__write_cr__data$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 40 \op__write_cr__ok$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 41 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 42 \op__is_32bit$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 43 \op__is_signed$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 output 44 \op__data_len$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 output 45 \op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 46 \o$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 47 \o_ok$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 48 \cr_a$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 49 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 50 \xer_ca$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 51 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
wire width 65 \o$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
wire width 65 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
wire width 64 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A \o
connect \Y $28
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
cell $pos $30
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $28
connect \Y $27
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 65 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
cell $pos $32
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
process $group_0
assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
switch { \op__invert_out }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
case 1'1
assign \o$26 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
case
assign \o$26 $31
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire width 64 \target
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
wire width 64 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
cell $pos $34
parameter \A_SIGNED 0
parameter \A_WIDTH 32
end
process $group_1
assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
switch { \op__is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
case 1'1
assign \target $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
case
assign \target \o$26 [63:0]
end
assign \xer_ca_ok \op__output_carry
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
wire width 1 \is_cmp
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
cell $eq $36
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmp $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
wire width 1 \is_cmpeqb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
cell $eq $38
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmpeqb $37
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
wire width 1 \msb_test
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
cell $xor $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \msb_test $39
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
wire width 1 \is_nzero
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
cell $reduce_bool $42
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \is_nzero $41
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 1 \is_positive
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $not $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \msb_test
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_positive $45
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
wire width 1 \is_negative
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
cell $and $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_negative $47
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
wire width 4 \cr0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
wire width 1 \so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
cell $not $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_10
assign \cr0 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
switch { \is_cmpeqb }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
case 1'1
assign \cr0 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
case
assign \cr0 { \is_negative \is_positive $49 \so }
end
connect \so 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu.pipe"
-module \pipe$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe"
+module \pipe$48
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 2 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 3 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 4 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 input 6 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 9 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 10 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 11 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 12 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 13 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 14 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 15 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 input 16 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 17 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 input 18 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 19 \op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 20 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 21 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 22 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 input 23 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 input 24 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 25 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 26 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 27 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 28 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 29 \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$1$next
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 output 30 \op__insn_type$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 output 31 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \op__fn_unit$3$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 34 \op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__lk$6$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 35 \op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__rc__rc$7$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__rc__rc_ok$8$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 37 \op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__oe__oe$9$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__oe__oe_ok$10$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 39 \op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_a$11$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 40 \op__zero_a$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__zero_a$12$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 output 41 \op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \op__input_carry$13$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 42 \op__invert_out$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_out$14$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 output 43 \op__write_cr__data$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \op__write_cr__data$15$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 44 \op__write_cr__ok$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__write_cr__ok$16$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 45 \op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__output_carry$17$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 46 \op__is_32bit$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_32bit$18$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 output 47 \op__is_signed$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_signed$19$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 output 48 \op__data_len$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \op__data_len$20$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 output 49 \op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \op__insn$21$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 50 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 51 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 52 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 53 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 54 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ca$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 55 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$next
- cell \p$35 \p
+ cell \p$49 \p
connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
end
- cell \n$36 \n
+ cell \n$50 \n
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \input_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \input_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \input_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \input_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \input_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \input_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \input_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \input_op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \input_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \input_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \input_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \input_muxid$22
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \input_op__insn_type$23
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_a$110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__zero_a$111
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \op__input_carry$112
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_out$113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \op__write_cr__data$114
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__write_cr__ok$115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__output_carry$116
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_32bit$117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_signed$118
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \op__data_len$119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \op__insn$120
process $group_77
assign \op__insn_type$101 7'0000000
assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \output_op__insn$86 \output_op__data_len$85 \output_op__is_signed$84 \output_op__is_32bit$83 \output_op__output_carry$82 { \output_op__write_cr__ok$81 \output_op__write_cr__data$80 } \output_op__invert_out$79 \output_op__input_carry$78 \output_op__zero_a$77 \output_op__invert_a$76 { \output_op__oe__oe_ok$75 \output_op__oe__oe$74 } { \output_op__rc__rc_ok$73 \output_op__rc__rc$72 } \output_op__lk$71 { \output_op__imm_data__imm_ok$70 \output_op__imm_data__imm$69 } \output_op__fn_unit$68 \output_op__insn_type$67 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$121
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$122
process $group_97
assign \o$121 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \o_ok$122 \o$121 } { \output_o_ok$88 \output_o$87 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$124
process $group_99
assign \cr_a$123 4'0000
assign { \cr_a_ok$124 \cr_a$123 } { \output_cr_a_ok \output_cr_a$89 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ca$125
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$126
process $group_101
assign \xer_ca$125 2'00
assign { \xer_ca_ok$126 \xer_ca$125 } { \output_xer_ca_ok \output_xer_ca$90 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
process $group_103
assign \r_busy$next \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \r_busy$next 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \r_busy$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \r_busy$next 1'0
end
process $group_104
assign \muxid$1$next \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \muxid$1$next \muxid$100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \muxid$1$next \muxid$100
end
assign \op__is_signed$19$next \op__is_signed$19
assign \op__data_len$20$next \op__data_len$20
assign \op__insn$21$next \op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
process $group_125
assign \o$next \o
assign \o_ok$next \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \o_ok$next \o$next } { \o_ok$122 \o$121 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \o_ok$next \o$next } { \o_ok$122 \o$121 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \o_ok$next 1'0
process $group_127
assign \cr_a$next \cr_a
assign \cr_a_ok$next \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$124 \cr_a$123 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$124 \cr_a$123 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_a_ok$next 1'0
process $group_129
assign \xer_ca$next \xer_ca
assign \xer_ca_ok$next \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$126 \xer_ca$125 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$126 \xer_ca$125 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_ca_ok$next 1'0
connect \xer_ca_ok$96 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu"
-module \alu$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu"
+module \alu$45
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 3 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 5 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 7 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 8 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 9 \n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 input 11 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 input 12 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 14 \op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 15 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 16 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 17 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 18 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 19 \op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 20 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 input 21 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 22 \op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 input 23 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 24 \op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 25 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 26 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 27 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 input 28 \op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 input 29 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 30 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 31 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 32 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 33 \p_ready_o
- cell \p$32 \p
+ cell \p$46 \p
connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
end
- cell \n$33 \n
+ cell \n$47 \n
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \pipe_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \pipe_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \pipe_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \pipe_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \pipe_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \pipe_op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \pipe_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \pipe_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \pipe_n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \pipe_op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \pipe_op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \pipe_op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__lk$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__invert_a$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__zero_a$12
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \pipe_op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__invert_out$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \pipe_op__write_cr__data$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__write_cr__ok$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__output_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__is_32bit$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \pipe_op__is_signed$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \pipe_op__data_len$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \pipe_op__insn$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \pipe_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \pipe_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_ca_ok
- cell \pipe$34 \pipe
+ cell \pipe$48 \pipe
connect \rst \rst
connect \clk \clk
connect \p_valid_i \pipe_p_valid_i
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$22
process $group_27
assign \muxid$22 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \op__insn_type$23
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \op__fn_unit$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \op__imm_data__imm$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__imm_data__imm_ok$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__lk$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__rc__rc$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__rc__rc_ok$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__oe__oe$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__oe__oe_ok$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_a$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__zero_a$33
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \op__input_carry$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__invert_out$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \op__write_cr__data$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__write_cr__ok$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__output_carry$38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_32bit$39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \op__is_signed$40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \op__data_len$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \op__insn$42
process $group_28
assign \op__insn_type$23 7'0000000
connect \muxid 2'00
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.src_l"
-module \src_l$40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l"
+module \src_l$54
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 2 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 2 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 2 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 2 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 2 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 2 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 2 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 2 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 2'00
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 2 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 2 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 2 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 2 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 2 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 2 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 2 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.opc_l"
-module \opc_l$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l"
+module \opc_l$55
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.req_l"
-module \req_l$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l"
+module \req_l$56
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 output 2 \q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 input 3 \s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 input 4 \r_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 3'000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \q_req $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \qn_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \qn_req $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 3 \qlq_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.rst_l"
-module \rst_l$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l"
+module \rst_l$57
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.rok_l"
-module \rok_l$44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l"
+module \rok_l$58
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 3 \s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 4 \r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rdok $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rdok $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alui_l"
-module \alui_l$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l"
+module \alui_l$59
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alui $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alui $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0.alu_l"
-module \alu_l$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l"
+module \alu_l$60
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.logical0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.logical0"
module \logical0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 input 3 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 6 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 7 \oper_i__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 8 \oper_i__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 9 \oper_i__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 10 \oper_i__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 11 \oper_i__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 12 \oper_i__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 input 13 \oper_i__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 14 \oper_i__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 input 15 \oper_i__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 16 \oper_i__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 17 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 18 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 input 19 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 input 20 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 input 21 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 22 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 23 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 2 input 24 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 output 25 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 input 26 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 27 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 28 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 29 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 30 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 31 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 32 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 33 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 34 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 35 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 36 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 37 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 38 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 39 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \alu_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \alu_n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \alu_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \alu_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \alu_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \alu_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \alu_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \alu_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \alu_op__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \alu_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \alu_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \alu_p_ready_o
- cell \alu$31 \alu
+ cell \alu$45 \alu
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
connect \p_valid_i \alu_p_valid_i
connect \p_ready_o \alu_p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 2 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 2 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 2 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 2 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 2 \src_l_q_src
- cell \src_l$40 \src_l
+ cell \src_l$54 \src_l
connect \rst \rst
connect \clk \clk
connect \s_src \src_l_s_src
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
- cell \opc_l$41 \opc_l
+ cell \opc_l$55 \opc_l
connect \rst \rst
connect \clk \clk
connect \s_opc \opc_l_s_opc
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \req_l_q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \req_l_s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \req_l_r_req
- cell \req_l$42 \req_l
+ cell \req_l$56 \req_l
connect \rst \rst
connect \clk \clk
connect \q_req \req_l_q_req
connect \s_req \req_l_s_req
connect \r_req \req_l_r_req
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
- cell \rst_l$43 \rst_l
+ cell \rst_l$57 \rst_l
connect \rst \rst
connect \clk \clk
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rok_l_s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok$next
- cell \rok_l$44 \rok_l
+ cell \rok_l$58 \rok_l
connect \rst \rst
connect \clk \clk
connect \q_rdok \rok_l_q_rdok
connect \s_rdok \rok_l_s_rdok
connect \r_rdok \rok_l_r_rdok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alui_l_q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alui_l_s_alui
- cell \alui_l$45 \alui_l
+ cell \alui_l$59 \alui_l
connect \rst \rst
connect \clk \clk
connect \q_alui \alui_l_q_alui
connect \r_alui \alui_l_r_alui
connect \s_alui \alui_l_s_alui
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
- cell \alu_l$46 \alu_l
+ cell \alu_l$60 \alu_l
connect \rst \rst
connect \clk \clk
connect \q_alu \alu_l_q_alu
connect \r_alu \alu_l_r_alu
connect \s_alu \alu_l_s_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
wire width 1 \all_rd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rok_l_q_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 2 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A \rd__rel
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 2 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $or $7
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \rd__go
connect \Y $6
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $reduce_and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A $6
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly$next
process $group_1
assign \all_rd_dly$next \all_rd_dly
sync posedge \clk
update \all_rd_dly \all_rd_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
wire width 1 \all_rd_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \all_rd_dly
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd_pulse $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire width 1 \alu_done
process $group_3
assign \alu_done 1'0
assign \alu_done \alu_n_valid_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly$next
process $group_4
assign \alu_done_dly$next \alu_done_dly
sync posedge \clk
update \alu_done_dly \alu_done_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
wire width 1 \alu_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_done_dly
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_pulse $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 3 \alu_pulsem
process $group_6
assign \alu_pulsem 3'000
assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
wire width 3 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_7
assign \prev_wr_go$next \prev_wr_go
assign \prev_wr_go$next $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \prev_wr_go$next 3'000
sync posedge \clk
update \prev_wr_go \prev_wr_go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wrmask
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $reduce_bool $27
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A $25
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $22
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o $29
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wr__go
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \prev_wr_go
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_n_ready_i
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 3 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B \wrmask
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $43
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_ready_i
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_valid_o
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_10
assign \req_done 1'0
assign \req_done $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
case 1'1
assign \req_done 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
wire width 1 \reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
cell $or $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset $55
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \rst_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_r $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 3 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
wire width 3 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \reset_w $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 2 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire width 2 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \rok_l_s_rdok \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
assign \rok_l_r_rdok$next $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \rok_l_r_rdok$next 1'1
process $group_19
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_20
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_21
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 2'00
process $group_22
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 2'11
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
wire width 3 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_s_req $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
wire width 3 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_r_req $67
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__lk$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__invert_out$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn$next
process $group_25
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__is_signed$next \oper_l__is_signed
assign \oper_l__data_len$next \oper_l__data_len
assign \oper_l__insn$next \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 10 \oper_r__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 2 \oper_r__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 3 \oper_r__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 1 \oper_r__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 4 \oper_r__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
wire width 32 \oper_r__insn
process $group_45
assign \oper_r__insn_type 7'0000000
assign \oper_r__is_signed 1'0
assign \oper_r__data_len 4'0000
assign \oper_r__insn 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_65
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r0_l__o_ok$next 1'0
update \data_r0_l__o \data_r0_l__o$next
update \data_r0_l__o_ok \data_r0_l__o_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r0__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r0__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $72
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_67
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $71 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0__o_ok \data_r0__o } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_69
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r1_l__cr_a_ok$next 1'0
update \data_r1_l__cr_a \data_r1_l__cr_a$next
update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 4 \data_r1__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r1__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_71
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_73
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $77 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r2_l__xer_ca_ok$next 1'0
update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 2 \data_r2__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r2__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_75
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
end
assign { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } \alu_op__invert_out \alu_op__input_carry \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $82
parameter \WIDTH 1
connect \A \src_l_q_src [0]
assign \src_sel $81
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $84
parameter \WIDTH 64
connect \A \src1_i
assign \src_or_imm $83
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel$85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $87
parameter \WIDTH 1
connect \A \src_l_q_src [1]
assign \src_sel$85 $86
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $90
parameter \WIDTH 64
connect \A \src2_i
assign \src_or_imm$88 $89
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0$next
process $group_102
assign \src_r0$next \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0$next \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_103
assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_ra \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_ra \src_r0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1$next
process $group_104
assign \src_r1$next \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel$85 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1$next \src_or_imm$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_105
assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel$85 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_rb \src_or_imm$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_rb \src_r1
end
assign \alu_p_valid_i \alui_l_q_alui
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
cell $and $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_107
assign \alui_l_r_alui$next \alui_l_r_alui
assign \alui_l_r_alui$next $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alui_l_r_alui$next 1'1
assign \alu_n_ready_i \alu_l_q_alu
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
wire width 1 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_110
assign \alu_l_r_alu$next \alu_l_r_alu
assign \alu_l_r_alu$next $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alu_l_r_alu$next 1'1
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 2 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $96
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B { \busy_o \busy_o }
connect \Y $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__zero_a
connect \Y $97
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 2 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B { $99 $97 }
connect \Y $101
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 2 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $not $104
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A \rdmaskn
connect \Y $103
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 2 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $106
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \rd__rel $105
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $107
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $109
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $111
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $114
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { $107 $109 $111 }
connect \Y $113
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $116
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_115
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 4 \dest2_o
process $group_116
assign \dest2_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 2 \dest3_o
process $group_117
assign \dest3_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.p"
-module \p$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.p"
+module \p$62
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.n"
-module \n$49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.n"
+module \n$63
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.p"
-module \p$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.p"
+module \p$65
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wire width 1 input 0 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 input 1 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.n"
-module \n$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.n"
+module \n$66
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wire width 1 input 0 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 1 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
wire width 1 \trigger
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.input"
-module \input$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.input"
+module \input$67
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wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 5 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 7 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 9 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 10 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 11 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 12 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 13 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 15 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 17 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 18 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 19 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 20 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 21 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 22 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 output 23 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 10 output 24 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 output 25 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 26 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 27 \op__rc__rc$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 1 output 28 \op__rc__rc_ok$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 1 output 29 \op__oe__oe$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 1 output 30 \op__oe__oe_ok$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 3 output 31 \op__write_cr__data$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 32 \op__write_cr__ok$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 output 33 \op__input_carry$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 1 output 34 \op__output_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 35 \op__input_cr$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 36 \op__output_cr$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 37 \op__is_32bit$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 38 \op__is_signed$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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wire width 32 output 39 \op__insn$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 output 40 \ra$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 output 41 \rb$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 output 42 \rc$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 output 43 \xer_ca$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
process $group_0
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
end
process $group_2
assign \xer_ca$22 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:36"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
switch \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:37"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
attribute \nmigen.decoding "ZERO/0"
case 2'00
assign \xer_ca$22 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:39"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \xer_ca$22 2'11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_input_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
attribute \nmigen.decoding "CA/2"
case 2'10
assign \xer_ca$22 \xer_ca
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.main.rotator.rotl"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main.rotator.rotl"
module \rotl
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:8"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
wire width 64 input 0 \a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:9"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
wire width 6 input 1 \b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:11"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
wire width 64 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:17"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:17"
wire width 64 \shl
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
wire width 127 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
wire width 127 $2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
cell $sshl $3
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \shl $1 [63:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
wire width 64 \shr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
wire width 8 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
cell $sub $5
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B \b
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
wire width 64 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
cell $sshr $7
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \shr $6
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:23"
wire width 64 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:23"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:23"
cell $or $9
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.main.rotator"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main.rotator"
module \rotator
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:43"
wire width 5 input 0 \me
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
wire width 5 input 1 \mb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
wire width 1 input 2 \mb_extra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
wire width 64 input 3 \rs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
wire width 64 input 4 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
wire width 7 input 5 \shift
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
wire width 1 input 6 \is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:51"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
wire width 1 input 7 \arith
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
wire width 1 input 8 \sign_ext_rs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
wire width 1 input 9 \right_shift
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
wire width 1 input 10 \clear_left
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
wire width 1 input 11 \clear_right
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
wire width 64 output 12 \result_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
wire width 1 output 13 \carry_out_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:8"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
wire width 64 \rotl_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:9"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
wire width 6 \rotl_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotl.py:11"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
wire width 64 \rotl_o
cell \rotl \rotl
connect \a \rotl_a
connect \b \rotl_b
connect \o \rotl_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
wire width 32 \hi32
process $group_0
assign \hi32 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
switch { \sign_ext_rs \is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:77"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
case 2'-1
assign \hi32 \rs [31:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:79"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
case 2'1-
assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:82"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
case
assign \hi32 \rs [63:32]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:74"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
wire width 64 \repl32
process $group_1
assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
assign \repl32 { \hi32 \rs [31:0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:86"
wire width 6 \shift_signed
process $group_2
assign \shift_signed 6'000000
assign \shift_signed \shift [5:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:65"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65"
wire width 6 \rot_count
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
wire width 7 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
wire width 7 $2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
cell $neg $3
parameter \A_SIGNED 1
parameter \A_WIDTH 6
connect $1 $2
process $group_3
assign \rot_count 6'000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90"
switch { \right_shift }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:90"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90"
case 1'1
assign \rot_count $1 [5:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
case
assign \rot_count \shift [5:0]
end
assign \rotl_b \rot_count
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:66"
wire width 64 \rot
process $group_6
assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
assign \rot \rotl_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:67"
wire width 7 \sh
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \is_32bit
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
wire width 1 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
cell $and $7
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \sh { $6 \shift [5:0] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:68"
wire width 7 \mb$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
wire width 7 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
cell $pos $10
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A \mb
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:118"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:118"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \mb$8 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:108"
switch { \right_shift \clear_left }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:108"
case 2'-1
assign \mb$8 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
switch { \is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
case 1'1
assign \mb$8 [6:5] 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
case
assign \mb$8 [6:5] { 1'0 \mb_extra }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:114"
case 2'1-
assign \mb$8 \sh
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
switch { \is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
case 1'1
assign \mb$8 [6:5] { \sh [5] $11 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:119"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
case
assign \mb$8 { 1'0 \is_32bit 5'00000 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:69"
wire width 7 \me$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
wire width 1 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
cell $and $15
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \is_32bit
connect \Y $14
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
wire width 1 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
cell $not $17
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \clear_left
connect \Y $16
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
wire width 1 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
cell $and $19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $16
connect \Y $18
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
wire width 6 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
cell $not $21
parameter \A_SIGNED 0
parameter \A_WIDTH 6
end
process $group_9
assign \me$13 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
switch { $18 $14 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:123"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
case 2'-1
assign \me$13 { 2'01 \me }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
case 2'1-
assign \me$13 { 1'0 \mb_extra \mb }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:129"
case
assign \me$13 { \sh [6] $20 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:12"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:12"
wire width 64 \right_mask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:13"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:13"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
cell $le $23
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'1000000
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
wire width 257 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
wire width 8 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
cell $sub $26
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B \mb$8
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
wire width 256 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
cell $sshl $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $25
connect \Y $27
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
wire width 257 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
cell $sub $30
parameter \A_SIGNED 0
parameter \A_WIDTH 256
connect $24 $29
process $group_10
assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:13"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:13"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
case 1'1
assign \right_mask $24 [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
wire width 64 \mr
process $group_11
assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
assign \mr \right_mask
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:18"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:18"
wire width 64 \left_mask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
wire width 257 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
wire width 257 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
wire width 8 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
cell $sub $34
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B \me$13
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
wire width 256 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
cell $sshl $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $33
connect \Y $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
wire width 257 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
cell $sub $38
parameter \A_SIGNED 0
parameter \A_WIDTH 256
connect \B 1'1
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
cell $not $39
parameter \A_SIGNED 0
parameter \A_WIDTH 257
assign \left_mask $31 [63:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
wire width 64 \ml
process $group_13
assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
assign \ml \left_mask
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
wire width 2 \output_mode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
wire width 1 $40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
cell $not $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \clear_right
connect \Y $40
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
wire width 1 $42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
cell $and $43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $40
connect \Y $42
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
wire width 1 $44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
cell $or $45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \right_shift
connect \Y $44
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
wire width 1 $46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
cell $and $47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \repl32 [63]
connect \Y $46
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
wire width 1 $48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
cell $gt $49
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \B \me$13 [5:0]
connect \Y $48
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
wire width 1 $50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
cell $and $51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_14
assign \output_mode 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
switch { $44 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
case 1'1
assign \output_mode { 1'1 $46 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
case
assign \output_mode { 1'0 $50 }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $and $53
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \ml
connect \Y $52
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $and $55
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $52
connect \Y $54
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $and $58
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \ml
connect \Y $57
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $not $59
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $57
connect \Y $56
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $and $61
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $56
connect \Y $60
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
wire width 64 $62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
cell $or $63
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $60
connect \Y $62
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $or $65
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \ml
connect \Y $64
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $and $67
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $64
connect \Y $66
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $or $70
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \ml
connect \Y $69
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $not $71
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A $69
connect \Y $68
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $and $73
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $68
connect \Y $72
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
wire width 64 $74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
cell $or $75
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $72
connect \Y $74
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
wire width 64 $76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
cell $and $77
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \mr
connect \Y $76
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
wire width 64 $78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
cell $not $79
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A \mr
connect \Y $78
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
wire width 64 $80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
cell $or $81
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
process $group_15
assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
switch \output_mode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
case 2'00
assign \result_o $62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
case 2'01
assign \result_o $74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
case 2'10
assign \result_o $76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
case 2'11
assign \result_o $80
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
wire width 1 $82
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
wire width 64 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
cell $not $84
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A \ml
connect \Y $83
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
wire width 64 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $83
connect \Y $85
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
process $group_16
assign \carry_out_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
switch \output_mode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
case 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
case 2'01
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
case 2'10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
case 2'11
assign \carry_out_o $82
end
end
end
attribute \generator "nMigen"
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-module \main$54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main"
+module \main$68
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wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 5 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 7 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 9 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 10 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 11 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 12 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 13 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 15 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 17 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 18 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 19 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 20 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 21 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 output 22 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 output 23 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 output 24 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 25 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 26 \op__rc__rc$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 27 \op__rc__rc_ok$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 28 \op__oe__oe$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 29 \op__oe__oe_ok$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 output 30 \op__write_cr__data$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 31 \op__write_cr__ok$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 output 32 \op__input_carry$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 33 \op__output_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 34 \op__input_cr$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 35 \op__output_cr$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 36 \op__is_32bit$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 37 \op__is_signed$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 output 38 \op__insn$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 39 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 40 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 41 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:43"
wire width 5 \rotator_me
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
wire width 5 \rotator_mb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
wire width 1 \rotator_mb_extra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
wire width 64 \rotator_rs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
wire width 64 \rotator_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:48"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
wire width 7 \rotator_shift
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:49"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
wire width 1 \rotator_is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:51"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
wire width 1 \rotator_arith
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
wire width 1 \rotator_sign_ext_rs
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
wire width 1 \rotator_right_shift
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:52"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
wire width 1 \rotator_clear_left
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
wire width 1 \rotator_clear_right
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
wire width 64 \rotator_result_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/rotator.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
wire width 1 \rotator_carry_out_o
cell \rotator \rotator
connect \me \rotator_me
connect \result_o \rotator_result_o
connect \carry_out_o \rotator_carry_out_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:38"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:38"
wire width 5 \mb
process $group_0
assign \mb 5'00000
assign \mb { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:39"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:39"
wire width 5 \me
process $group_1
assign \me 5'00000
assign \me { \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:40"
wire width 1 \mb_extra
process $group_2
assign \mb_extra 1'0
process $group_12
assign \o_ok 1'0
assign \o_ok 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:64"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:65"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
attribute \nmigen.decoding "OP_SHL/60"
case 7'0111100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
attribute \nmigen.decoding "OP_SHR/61"
case 7'0111101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
attribute \nmigen.decoding "OP_RLC/56"
case 7'0111000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
attribute \nmigen.decoding "OP_RLCL/57"
case 7'0111001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
attribute \nmigen.decoding "OP_RLCR/58"
case 7'0111010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
attribute \nmigen.decoding ""
case
assign \o_ok 1'0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:63"
wire width 3 \mode
process $group_13
assign \mode 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:64"
switch \op__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:65"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
attribute \nmigen.decoding "OP_SHL/60"
case 7'0111100
assign \mode 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
attribute \nmigen.decoding "OP_SHR/61"
case 7'0111101
assign \mode 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
attribute \nmigen.decoding "OP_RLC/56"
case 7'0111000
assign \mode 3'110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
attribute \nmigen.decoding "OP_RLCL/57"
case 7'0111001
assign \mode 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
attribute \nmigen.decoding "OP_RLCR/58"
case 7'0111010
assign \mode 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
attribute \nmigen.decoding ""
case
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu.pipe.output"
-module \output$55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.output"
+module \output$69
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 0 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 2 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 5 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 7 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 9 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 10 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 11 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 12 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 13 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 15 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 17 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 18 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 19 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 input 20 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 input 21 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 22 \muxid$1
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 output 23 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 output 24 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 output 25 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 26 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 27 \op__rc__rc$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 28 \op__rc__rc_ok$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 29 \op__oe__oe$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 30 \op__oe__oe_ok$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 output 31 \op__write_cr__data$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 32 \op__write_cr__ok$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 output 33 \op__input_carry$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 34 \op__output_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 35 \op__input_cr$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 36 \op__output_cr$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 37 \op__is_32bit$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 38 \op__is_signed$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 output 39 \op__insn$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 40 \o$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 41 \o_ok$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 42 \cr_a$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 43 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 44 \xer_ca$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 45 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
wire width 65 \o$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 65 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
cell $pos $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \o$23 $24
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
wire width 64 \target
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
wire width 64 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
cell $pos $27
parameter \A_SIGNED 0
parameter \A_WIDTH 32
end
process $group_1
assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
switch { \op__is_32bit }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:30"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
case 1'1
assign \target $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
case
assign \target \o$23 [63:0]
end
assign \xer_ca_ok \op__output_carry
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
wire width 1 \is_cmp
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
wire width 1 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:53"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
cell $eq $29
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmp $28
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
wire width 1 \is_cmpeqb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
wire width 1 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:54"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
cell $eq $31
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \is_cmpeqb $30
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
wire width 1 \msb_test
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
wire width 1 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
cell $xor $33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \msb_test $32
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
wire width 1 \is_nzero
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
wire width 1 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:56"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
cell $reduce_bool $35
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign \is_nzero $34
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
wire width 1 \is_positive
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $not $37
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \msb_test
connect \Y $36
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 1 $38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:57"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
cell $and $39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_positive $38
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
wire width 1 \is_negative
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
wire width 1 $40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:58"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
cell $and $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \is_negative $40
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
wire width 4 \cr0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:46"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
wire width 1 \so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
wire width 1 $42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:63"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
cell $not $43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_10
assign \cr0 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
switch { \is_cmpeqb }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
case 1'1
assign \cr0 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/common_output_stage.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
case
assign \cr0 { \is_negative \is_positive $42 \so }
end
connect \so 1'0
end
attribute \generator "nMigen"
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-module \pipe$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe"
+module \pipe$64
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 2 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 3 \p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 input 4 \muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 6 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 9 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 10 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 11 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 12 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 13 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 15 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 17 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 18 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 19 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 20 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 21 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 22 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 23 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 24 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 25 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 26 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 27 \n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 output 28 \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$1$next
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 output 29 \op__insn_type$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 output 30 \op__fn_unit$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \op__fn_unit$3$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 output 31 \op__imm_data__imm$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 32 \op__imm_data__imm_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 33 \op__rc__rc$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc$6$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 34 \op__rc__rc_ok$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc_ok$7$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 35 \op__oe__oe$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe$8$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 36 \op__oe__oe_ok$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe_ok$9$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 output 37 \op__write_cr__data$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \op__write_cr__data$10$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 38 \op__write_cr__ok$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__write_cr__ok$11$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 output 39 \op__input_carry$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \op__input_carry$12$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 40 \op__output_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__output_carry$13$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 output 41 \op__input_cr$14
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wire width 32 \op__insn$18$next
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wire width 1 \xer_ca_ok$next
- cell \p$51 \p
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connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
end
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connect \n_ready_i \n_ready_i
end
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connect \muxid \input_muxid
connect \op__insn_type \input_op__insn_type
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connect \rc$21 \input_rc$40
connect \xer_ca$22 \input_xer_ca$41
end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \output_op__input_carry$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \output_op__output_carry$72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \output_op__input_cr$73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \output_op__output_cr$74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \output_op__is_32bit$75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \output_op__is_signed$76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \output_op__insn$77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \output_o$78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_o_ok$79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \output_cr_a$80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \output_xer_ca$81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_ca_ok
- cell \output$55 \output
+ cell \output$69 \output
connect \muxid \output_muxid
connect \op__insn_type \output_op__insn_type
connect \op__fn_unit \output_op__fn_unit
assign \main_rc \input_rc$40
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 \xer_ca$82
process $group_43
assign \xer_ca$82 2'00
assign { \output_o_ok \output_o } { \main_o_ok \main_o }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$84
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$85
process $group_64
assign \output_cr_a 4'0000
assign { \cr_a_ok$83 \output_cr_a } { \cr_a_ok$85 \cr_a$84 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$87
process $group_66
assign \output_xer_ca 2'00
assign { \xer_ca_ok$86 \output_xer_ca } { \xer_ca_ok$87 \main_xer_ca }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:621"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
wire width 1 \p_valid_i$88
process $group_68
assign \p_valid_i$88 1'0
assign \p_valid_i$88 \p_valid_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:619"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
process $group_69
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:620"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
wire width 1 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:624"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
cell $and $90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \p_valid_i_p_ready_o $89
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$91
process $group_71
assign \muxid$91 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \op__insn_type$92
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \op__fn_unit$93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \op__imm_data__imm$94
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__imm_data__imm_ok$95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc$96
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc_ok$97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe$98
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe_ok$99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \op__write_cr__data$100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__write_cr__ok$101
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \op__input_carry$102
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__output_carry$103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__input_cr$104
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__output_cr$105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__is_32bit$106
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__is_signed$107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \op__insn$108
process $group_72
assign \op__insn_type$92 7'0000000
assign { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 } { \output_op__insn$77 \output_op__is_signed$76 \output_op__is_32bit$75 \output_op__output_cr$74 \output_op__input_cr$73 \output_op__output_carry$72 \output_op__input_carry$71 { \output_op__write_cr__ok$70 \output_op__write_cr__data$69 } { \output_op__oe__oe_ok$68 \output_op__oe__oe$67 } { \output_op__rc__rc_ok$66 \output_op__rc__rc$65 } { \output_op__imm_data__imm_ok$64 \output_op__imm_data__imm$63 } \output_op__fn_unit$62 \output_op__insn_type$61 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$110
process $group_89
assign \o$109 64'0000000000000000000000000000000000000000000000000000000000000000
assign { \o_ok$110 \o$109 } { \output_o_ok$79 \output_o$78 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$112
process $group_91
assign \cr_a$111 4'0000
assign { \cr_a_ok$112 \cr_a$111 } { \output_cr_a_ok \output_cr_a$80 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ca$113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$114
process $group_93
assign \xer_ca$113 2'00
assign { \xer_ca_ok$114 \xer_ca$113 } { \output_xer_ca_ok \output_xer_ca$81 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:615"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
process $group_95
assign \r_busy$next \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \r_busy$next 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \r_busy$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \r_busy$next 1'0
end
process $group_96
assign \muxid$1$next \muxid$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign \muxid$1$next \muxid$91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign \muxid$1$next \muxid$91
end
assign \op__is_32bit$16$next \op__is_32bit$16
assign \op__is_signed$17$next \op__is_signed$17
assign \op__insn$18$next \op__insn$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \op__insn$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_cr$15$next \op__input_cr$14$next \op__output_carry$13$next \op__input_carry$12$next { \op__write_cr__ok$11$next \op__write_cr__data$10$next } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \op__insn$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_cr$15$next \op__input_cr$14$next \op__output_carry$13$next \op__input_carry$12$next { \op__write_cr__ok$11$next \op__write_cr__data$10$next } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
process $group_114
assign \o$next \o
assign \o_ok$next \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \o_ok$next \o$next } { \o_ok$110 \o$109 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \o_ok$next \o$next } { \o_ok$110 \o$109 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \o_ok$next 1'0
process $group_116
assign \cr_a$next \cr_a
assign \cr_a_ok$next \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$112 \cr_a$111 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$112 \cr_a$111 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_a_ok$next 1'0
process $group_118
assign \xer_ca$19$next \xer_ca$19
assign \xer_ca_ok$next \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:631"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
assign { \xer_ca_ok$next \xer_ca$19$next } { \xer_ca_ok$114 \xer_ca$113 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/singlepipe.py:637"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
assign { \xer_ca_ok$next \xer_ca$19$next } { \xer_ca_ok$114 \xer_ca$113 }
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_ca_ok$next 1'0
connect \xer_ca_ok$87 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu"
-module \alu$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu"
+module \alu$61
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 3 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 4 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 5 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 7 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 output 8 \n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 input 9 \n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 11 \op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 12 \op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 15 \op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 17 \op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 18 \op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 19 \op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 20 \op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 21 \op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 22 \op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 23 \op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 24 \op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 25 \op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 26 \op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 27 \ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 28 \rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 input 29 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 input 30 \xer_ca$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 input 31 \p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 output 32 \p_ready_o
- cell \p$48 \p
+ cell \p$62 \p
connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
end
- cell \n$49 \n
+ cell \n$63 \n
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \pipe_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \pipe_p_ready_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \pipe_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \pipe_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \pipe_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \pipe_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \pipe_rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 \pipe_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \pipe_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \pipe_n_ready_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \pipe_muxid$2
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \pipe_op__insn_type$3
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \pipe_op__fn_unit$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \pipe_op__imm_data__imm$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__imm_data__imm_ok$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__rc__rc$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__rc__rc_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__oe__oe$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__oe__oe_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \pipe_op__write_cr__data$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__write_cr__ok$12
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \pipe_op__input_carry$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__output_carry$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__input_cr$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__output_cr$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__is_32bit$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \pipe_op__is_signed$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \pipe_op__insn$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \pipe_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \pipe_xer_ca$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_ca_ok
- cell \pipe$50 \pipe
+ cell \pipe$64 \pipe
connect \rst \rst
connect \clk \clk
connect \p_valid_i \pipe_p_valid_i
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
wire width 2 \muxid$21
process $group_26
assign \muxid$21 2'00
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \op__insn_type$22
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \op__fn_unit$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \op__imm_data__imm$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__imm_data__imm_ok$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__rc__rc_ok$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__oe__oe_ok$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \op__write_cr__data$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__write_cr__ok$31
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \op__input_carry$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__output_carry$33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__input_cr$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__output_cr$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__is_32bit$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \op__is_signed$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \op__insn$38
process $group_27
assign \op__insn_type$22 7'0000000
connect \muxid 2'00
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.src_l"
-module \src_l$56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
+module \src_l$70
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 4 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 4 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 4'0000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 4 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 4 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 4 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 4 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 4 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.opc_l"
-module \opc_l$57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
+module \opc_l$71
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.req_l"
-module \req_l$58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l"
+module \req_l$72
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 output 2 \q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 input 3 \s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 input 4 \r_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 3'000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_req
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \q_req $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \qn_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \qn_req $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 3 \qlq_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.rst_l"
-module \rst_l$59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l"
+module \rst_l$73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.rok_l"
-module \rok_l$60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l"
+module \rok_l$74
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 3 \s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 4 \r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rdok
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rdok $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rdok $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alui_l"
-module \alui_l$61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l"
+module \alui_l$75
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alui
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alui $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alui $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0.alu_l"
-module \alu_l$62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l"
+module \alu_l$76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 2 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 4 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.shiftrot0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0"
module \shiftrot0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 input 3 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 6 \oper_i__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 7 \oper_i__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 8 \oper_i__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 9 \oper_i__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 input 10 \oper_i__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 11 \oper_i__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 input 12 \oper_i__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 13 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 14 \oper_i__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 15 \oper_i__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 16 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 input 17 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 input 18 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 19 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 20 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 4 input 21 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 22 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 input 23 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 24 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 25 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 26 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 2 input 27 \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 28 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 29 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 30 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 31 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 32 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 output 33 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 34 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 output 35 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 36 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 37 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 38 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
wire width 1 \alu_n_valid_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
wire width 1 \alu_n_ready_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \alu_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \alu_op__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \alu_op__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \alu_op__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \alu_op__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \alu_op__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \alu_op__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 64 \alu_rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
wire width 2 \alu_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
wire width 1 \alu_p_valid_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
wire width 1 \alu_p_ready_o
- cell \alu$47 \alu
+ cell \alu$61 \alu
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
connect \p_valid_i \alu_p_valid_i
connect \p_ready_o \alu_p_ready_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 4 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 4 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 4 \src_l_q_src
- cell \src_l$56 \src_l
+ cell \src_l$70 \src_l
connect \rst \rst
connect \clk \clk
connect \s_src \src_l_s_src
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
- cell \opc_l$57 \opc_l
+ cell \opc_l$71 \opc_l
connect \rst \rst
connect \clk \clk
connect \s_opc \opc_l_s_opc
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \req_l_q_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \req_l_s_req
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \req_l_r_req
- cell \req_l$58 \req_l
+ cell \req_l$72 \req_l
connect \rst \rst
connect \clk \clk
connect \q_req \req_l_q_req
connect \s_req \req_l_s_req
connect \r_req \req_l_r_req
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
- cell \rst_l$59 \rst_l
+ cell \rst_l$73 \rst_l
connect \rst \rst
connect \clk \clk
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_q_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rok_l_s_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rok_l_r_rdok$next
- cell \rok_l$60 \rok_l
+ cell \rok_l$74 \rok_l
connect \rst \rst
connect \clk \clk
connect \q_rdok \rok_l_q_rdok
connect \s_rdok \rok_l_s_rdok
connect \r_rdok \rok_l_r_rdok
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alui_l_q_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_r_alui$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alui_l_s_alui
- cell \alui_l$61 \alui_l
+ cell \alui_l$75 \alui_l
connect \rst \rst
connect \clk \clk
connect \q_alui \alui_l_q_alui
connect \r_alui \alui_l_r_alui
connect \s_alui \alui_l_s_alui
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
- cell \alu_l$62 \alu_l
+ cell \alu_l$76 \alu_l
connect \rst \rst
connect \clk \clk
connect \q_alu \alu_l_q_alu
connect \r_alu \alu_l_r_alu
connect \s_alu \alu_l_s_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:177"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177"
wire width 1 \all_rd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:178"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rok_l_q_rdok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $not $5
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rd__rel
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 4 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $or $7
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \rd__go
connect \Y $6
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $reduce_and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A $6
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:179"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182"
wire width 1 \all_rd_dly$next
process $group_1
assign \all_rd_dly$next \all_rd_dly
sync posedge \clk
update \all_rd_dly \all_rd_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:183"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
wire width 1 \all_rd_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $not $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \all_rd_dly
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185"
cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \all_rd_pulse $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
wire width 1 \alu_done
process $group_3
assign \alu_done 1'0
assign \alu_done \alu_n_valid_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:189"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
wire width 1 \alu_done_dly$next
process $group_4
assign \alu_done_dly$next \alu_done_dly
sync posedge \clk
update \alu_done_dly \alu_done_dly$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:190"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
wire width 1 \alu_pulse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_done_dly
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:194"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_pulse $17
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 3 \alu_pulsem
process $group_6
assign \alu_pulsem 3'000
assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
wire width 3 \prev_wr_go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
wire width 3 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_7
assign \prev_wr_go$next \prev_wr_go
assign \prev_wr_go$next $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \prev_wr_go$next 3'000
sync posedge \clk
update \prev_wr_go \prev_wr_go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wrmask
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 3 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $reduce_bool $27
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A $25
connect \Y $22
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $not $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $22
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:208"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o $29
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \wr__go
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \prev_wr_go
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $35
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_n_ready_i
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 3 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B \wrmask
connect \Y $41
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $eq $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
wire width 1 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $43
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 1'0
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_ready_i
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \alu_n_valid_o
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
wire width 1 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_10
assign \req_done 1'0
assign \req_done $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
switch { $53 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:216"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216"
case 1'1
assign \req_done 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:220"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
wire width 1 \reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
cell $or $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset $55
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:221"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \rst_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:225"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_r $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 3 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
wire width 3 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \reset_w $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 4 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
wire width 4 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:227"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rok_l_s_rdok \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
wire width 1 $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:231"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
assign \rok_l_r_rdok$next $63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \rok_l_r_rdok$next 1'1
process $group_19
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_20
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \req_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_21
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 4'0000
process $group_22
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 4'1111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
wire width 3 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:246"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_s_req $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
wire width 3 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \req_l_r_req $67
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 10 \oper_l__fn_unit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__rc__rc_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__oe__oe_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 3 \oper_l__write_cr__data$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__write_cr__ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \oper_l__input_carry$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_carry$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__input_cr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__output_cr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 32 \oper_l__insn$next
process $group_25
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__is_signed$next \oper_l__is_signed
assign \oper_l__insn$next \oper_l__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 10 \oper_r__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 3 \oper_r__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 2 \oper_r__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 1 \oper_r__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
wire width 32 \oper_r__insn
process $group_42
assign \oper_r__insn_type 7'0000000
assign \oper_r__is_32bit 1'0
assign \oper_r__is_signed 1'0
assign \oper_r__insn 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \data_r0_l__o$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r0_l__o_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_59
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $69 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r0_l__o_ok$next 1'0
update \data_r0_l__o \data_r0_l__o$next
update \data_r0_l__o_ok \data_r0_l__o_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 64 \data_r0__o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r0__o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $72
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_61
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $71 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r0__o_ok \data_r0__o } { \o_ok \o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \data_r1_l__cr_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r1_l__cr_a_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_63
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $73 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r1_l__cr_a_ok$next 1'0
update \data_r1_l__cr_a \data_r1_l__cr_a$next
update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 4 \data_r1__cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r1__cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_65
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $75 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 2 \data_r2_l__xer_ca$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \data_r2_l__xer_ca_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_67
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $77 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \data_r2_l__xer_ca_ok$next 1'0
update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 2 \data_r2__xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261"
wire width 1 \data_r2__xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_69
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { $79 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
end
assign { \alu_op__insn \alu_op__is_signed \alu_op__is_32bit \alu_op__output_cr \alu_op__input_cr \alu_op__output_carry \alu_op__input_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 1 \src_sel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:158"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
cell $mux $82
parameter \WIDTH 1
connect \A \src_l_q_src [1]
assign \src_sel $81
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:156"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156"
wire width 64 \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
wire width 64 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
cell $mux $84
parameter \WIDTH 64
connect \A \src2_i
assign \src_or_imm $83
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0$next
process $group_91
assign \src_r0$next \src_r0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0$next \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_92
assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_ra \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_ra \src_r0
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1$next
process $group_93
assign \src_r1$next \src_r1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1$next \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_94
assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_sel }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_rb \src_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_rb \src_r1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r2$next
process $group_95
assign \src_r2$next \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2$next \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_96
assign \alu_rc 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_rc \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_rc \src_r2
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 2 \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 2 \src_r3$next
process $group_97
assign \src_r3$next \src_r3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r3$next \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
end
process $group_98
assign \alu_xer_ca 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [3] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \alu_xer_ca \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \alu_xer_ca \src_r3
end
assign \alu_p_valid_i \alui_l_q_alui
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:320"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_100
assign \alui_l_r_alui$next \alui_l_r_alui
assign \alui_l_r_alui$next $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alui_l_r_alui$next 1'1
assign \alu_n_ready_i \alu_l_q_alu
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:327"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327"
cell $and $88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_103
assign \alu_l_r_alu$next \alu_l_r_alu
assign \alu_l_r_alu$next $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \alu_l_r_alu$next 1'1
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $90
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { \busy_o \busy_o \busy_o \busy_o }
connect \Y $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163"
cell $not $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
connect \Y $91
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B { 1'1 1'1 $91 1'1 }
connect \Y $93
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $not $96
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A \rdmaskn
connect \Y $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
wire width 4 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:340"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340"
cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \rd__rel $97
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $101
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
wire width 1 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:343"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343"
cell $and $104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $103
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $106
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { $99 $101 $103 }
connect \Y $105
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
wire width 3 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:344"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
cell $and $108
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_108
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 4 \dest2_o
process $group_109
assign \dest2_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 2 \dest3_o
process $group_110
assign \dest3_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
switch { \wr__go [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:348"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.opc_l"
-module \opc_l$63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
+module \opc_l$77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_opc
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_opc $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_opc $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.src_l"
-module \src_l$64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l"
+module \src_l$78
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 input 2 \s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 input 3 \r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 output 4 \q_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 3 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_src
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 3 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 3
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 3'000
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \r_src
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \q_src $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \qn_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 3 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \qn_src $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 3 \qlq_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 3 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.alu_l"
-module \alu_l$65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l"
+module \alu_l$79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_alu
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_alu $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_alu $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.adr_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l"
module \adr_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_adr
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_adr
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_adr $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_adr $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.lod_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l"
module \lod_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 output 4 \qn_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 5 \q_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_lod
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_lod
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_lod $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_lod $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.sto_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l"
module \sto_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_sto
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_sto
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_sto $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_sto $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.wri_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l"
module \wri_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_wri
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_wri
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_wri $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_wri $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.upd_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l"
module \upd_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_upd
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_upd
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_upd $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_upd $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0.rst_l"
-module \rst_l$66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l"
+module \rst_l$80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_rst
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \q_rst $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_rst $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus.ldst0"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
module \ldst0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 0 \ad__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 1 \ad__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 2 \st__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 3 \st__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 4 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 5 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 7 input 6 \oper_i__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 64 input 7 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 8 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 9 \oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 10 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 11 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 4 input 12 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 13 \oper_i__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 14 \oper_i__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 input 15 \oper_i__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 16 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 17 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 3 input 18 \rdmaskn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 19 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 21 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 22 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 input 23 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 output 24 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 2 input 25 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 26 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 27 \ea
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 28 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
wire width 1 output 29 \load_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:113"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
wire width 1 output 30 \stwd_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 31 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
wire width 1 output 32 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
wire width 1 output 33 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire width 4 output 34 \ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 output 35 \ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 output 35 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 36 \ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
wire width 1 input 37 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
wire width 1 input 38 \ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 39 \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 40 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 41 \ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 42 \ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \opc_l_s_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \opc_l_q_opc
- cell \opc_l$63 \opc_l
+ cell \opc_l$77 \opc_l
connect \rst \rst
connect \clk \clk
connect \s_opc \opc_l_s_opc
connect \r_opc \opc_l_r_opc
connect \q_opc \opc_l_q_opc
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \src_l_s_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 3 \src_l_s_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \src_l_r_src
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 3 \src_l_r_src$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \src_l_q_src
- cell \src_l$64 \src_l
+ cell \src_l$78 \src_l
connect \rst \rst
connect \clk \clk
connect \s_src \src_l_s_src
connect \r_src \src_l_r_src
connect \q_src \src_l_q_src
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \alu_l_s_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_r_alu
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \alu_l_q_alu
- cell \alu_l$65 \alu_l
+ cell \alu_l$79 \alu_l
connect \rst \rst
connect \clk \clk
connect \s_alu \alu_l_s_alu
connect \r_alu \alu_l_r_alu
connect \q_alu \alu_l_q_alu
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \adr_l_s_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \adr_l_r_adr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \adr_l_r_adr$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \adr_l_q_adr
cell \adr_l \adr_l
connect \rst \rst
connect \r_adr \adr_l_r_adr
connect \q_adr \adr_l_q_adr
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \lod_l_s_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \lod_l_r_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \lod_l_qn_lod
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \lod_l_q_lod
cell \lod_l \lod_l
connect \rst \rst
connect \qn_lod \lod_l_qn_lod
connect \q_lod \lod_l_q_lod
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \sto_l_s_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \sto_l_r_sto
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \sto_l_q_sto
cell \sto_l \sto_l
connect \rst \rst
connect \r_sto \sto_l_r_sto
connect \q_sto \sto_l_q_sto
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \wri_l_s_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \wri_l_r_wri
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \wri_l_r_wri$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \wri_l_q_wri
cell \wri_l \wri_l
connect \rst \rst
connect \r_wri \wri_l_r_wri
connect \q_wri \wri_l_q_wri
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \upd_l_s_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \upd_l_s_upd$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \upd_l_r_upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \upd_l_r_upd$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \upd_l_q_upd
cell \upd_l \upd_l
connect \rst \rst
connect \r_upd \upd_l_r_upd
connect \q_upd \upd_l_q_upd
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \rst_l_s_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \rst_l_r_rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rst_l_q_rst
- cell \rst_l$66 \rst_l
+ cell \rst_l$80 \rst_l
connect \rst \rst
connect \clk \clk
connect \s_rst \rst_l_s_rst
connect \r_rst \rst_l_r_rst
connect \q_rst \rst_l_q_rst
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288"
wire width 1 \reset_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292"
cell $or $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_i $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:284"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:284"
wire width 1 \reset_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274"
wire width 1 \wr_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:293"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:293"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
cell $or $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_o $3
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:285"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285"
wire width 1 \reset_w
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:294"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:294"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_w $5
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:286"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286"
wire width 1 \reset_u
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_u $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:290"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290"
wire width 1 \reset_s
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:296"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:296"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_s $9
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
wire width 3 \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:297"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
wire width 3 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:297"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \reset_r $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:287"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287"
wire width 1 \reset_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:298"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:298"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \reset_a $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
wire width 1 \p_st_go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
wire width 1 \p_st_go$next
process $group_7
assign \p_st_go$next \p_st_go
process $group_8
assign \opc_l_s_opc$next \opc_l_s_opc
assign \opc_l_s_opc$next \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_s_opc$next 1'0
process $group_9
assign \opc_l_r_opc$next \opc_l_r_opc
assign \opc_l_r_opc$next \reset_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \opc_l_r_opc$next 1'1
process $group_10
assign \src_l_s_src$next \src_l_s_src
assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_s_src$next 3'000
process $group_11
assign \src_l_r_src$next \src_l_r_src
assign \src_l_r_src$next \reset_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \src_l_r_src$next 3'111
assign \alu_l_s_alu \reset_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:268"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
wire width 1 \alu_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:268"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
wire width 1 \alu_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:267"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267"
wire width 1 \alu_valid
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
cell $not $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \alu_valid
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $15
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:272"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272"
wire width 1 \rda_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \rda_any
connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
wire width 1 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_15
assign \adr_l_r_adr$next \adr_l_r_adr
assign \adr_l_r_adr$next \reset_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \adr_l_r_adr$next 1'1
assign \lod_l_s_lod \reset_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:270"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
wire width 1 \ld_ok
process $group_17
assign \lod_l_r_lod 1'1
assign \wri_l_s_wri \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:342"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
wire width 2 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:100"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:342"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
wire width 2 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:342"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
cell $or $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_19
assign \wri_l_r_wri$next \wri_l_r_wri
assign \wri_l_r_wri$next $23 [0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \wri_l_r_wri$next 1'1
process $group_20
assign \upd_l_s_upd$next \upd_l_s_upd
assign \upd_l_s_upd$next \reset_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \upd_l_s_upd$next 1'0
process $group_21
assign \upd_l_r_upd$next \upd_l_r_upd
assign \upd_l_r_upd$next \reset_u
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \upd_l_r_upd$next 1'1
sync posedge \clk
update \upd_l_r_upd \upd_l_r_upd$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:269"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
wire width 1 \addr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264"
wire width 1 \op_is_st
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:349"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:349"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:349"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:349"
cell $and $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \sto_l_s_sto $26
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
wire width 1 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
cell $or $29
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rst_l_r_rst \issue_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 7 \oper_l__insn_type$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 64 \oper_l__imm_data__imm$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__imm_data__imm_ok$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__zero_a$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__is_signed$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 4 \oper_l__data_len$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__byte_reverse$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__sign_extend$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:36"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36"
wire width 1 \oper_l__update$next
process $group_26
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__byte_reverse$next \oper_l__byte_reverse
assign \oper_l__sign_extend$next \oper_l__sign_extend
assign \oper_l__update$next \oper_l__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_l__update$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 7 \oper_r__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 4 \oper_r__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
wire width 1 \oper_r__update
process $group_36
assign \oper_r__insn_type 7'0000000
assign \oper_r__byte_reverse 1'0
assign \oper_r__sign_extend 1'0
assign \oper_r__update 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \issue_i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } { \oper_l__update \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \ldo_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \ldo_r$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:278"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
wire width 64 \ldd_o
process $group_46
assign \ldo_r$next \ldo_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \ld_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \ldo_r$next \ldd_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
sync posedge \clk
update \ldo_r \ldo_r$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:361"
wire width 64 \ldd_r
process $group_47
assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \ld_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \ldd_r \ldd_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \ldd_r \ldo_r
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r0_l$next
process $group_48
assign \src_r0_l$next \src_r0_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0_l$next \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
sync posedge \clk
update \src_r0_l \src_r0_l$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
wire width 64 \src_r0
process $group_49
assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r0 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \src_r0 \src_r0_l
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r1_l$next
process $group_50
assign \src_r1_l$next \src_r1_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1_l$next \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
sync posedge \clk
update \src_r1_l \src_r1_l$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
wire width 64 \src_r1
process $group_51
assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [1] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r1 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \src_r1 \src_r1_l
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r2_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \src_r2_l$next
process $group_52
assign \src_r2_l$next \src_r2_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2_l$next \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
sync posedge \clk
update \src_r2_l \src_r2_l$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:368"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
wire width 64 \src_r2
process $group_53
assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \src_l_q_src [2] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \src_r2 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \src_r2 \src_r2_l
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \ea_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
wire width 64 \ea_r$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277"
wire width 64 \alu_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:277"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277"
wire width 64 \alu_o$next
process $group_54
assign \ea_r$next \ea_r
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \alu_l_q_alu }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \ea_r$next \alu_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
end
sync init
sync posedge \clk
update \ea_r \ea_r$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:373"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
wire width 64 \addr_r
process $group_55
assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
switch { \alu_l_q_alu }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
case 1'1
assign \addr_r \alu_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
case
assign \addr_r \ea_r
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:378"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
wire width 64 \src1_or_z
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:379"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379"
wire width 64 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:379"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379"
cell $mux $31
parameter \WIDTH 64
connect \A \src_r0
assign \src1_or_z $30
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:383"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383"
wire width 64 \src2_or_imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:384"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
wire width 64 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:384"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
cell $mux $33
parameter \WIDTH 64
connect \A \src_r1
assign \src2_or_imm $32
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:387"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
wire width 65 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:387"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
wire width 65 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:387"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
cell $add $36
parameter \A_SIGNED 0
parameter \A_WIDTH 64
sync posedge \clk
update \alu_ok \alu_ok$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:391"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391"
wire width 1 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:391"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391"
cell $eq $38
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \op_is_st $37
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:263"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:263"
wire width 1 \op_is_ld
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:392"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:392"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
cell $eq $40
parameter \A_SIGNED 0
parameter \A_WIDTH 7
assign \op_is_ld $39
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:394"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:394"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394"
cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \load_mem_o $41
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
wire width 1 $43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \stwd_mem_o $43
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108"
wire width 1 \ld_o
process $group_64
assign \ld_o 1'0
assign \ld_o \op_is_ld
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:109"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109"
wire width 1 \st_o
process $group_65
assign \st_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 3 $45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { \busy_o \busy_o \busy_o }
connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 2 $47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
cell $not $48
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a }
connect \Y $47
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 3 $49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $47
connect \Y $49
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 3 $51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
cell $not $52
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \rdmaskn
connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
wire width 3 $53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $51
connect \Y $53
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
wire width 1 $55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $55
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
wire width 1 $57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
cell $and $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rd__rel [2] $57
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413"
wire width 1 $59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rda_any $59
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
wire width 1 $61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
wire width 1 $62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
cell $or $63
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rd__rel [1]
connect \Y $62
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
cell $not $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $62
connect \Y $61
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
wire width 1 $65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \alu_valid $65
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:273"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
wire width 1 \rd_done
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
wire width 1 $67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
cell $not $68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \rd__rel [2]
connect \Y $67
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
wire width 1 $69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
cell $and $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \rd_done $69
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
wire width 1 $71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
cell $and $72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \adr_l_q_adr
connect \Y $71
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
wire width 1 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
cell $and $74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ad__rel $73
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
wire width 1 $75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
cell $and $76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $75
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
wire width 1 $77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
cell $and $78
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rd_done
connect \Y $77
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
wire width 1 $79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
cell $and $80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_st
connect \Y $79
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:429"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
wire width 1 $81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:429"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
cell $and $82
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \st__rel $81
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
wire width 1 $83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
cell $and $84
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \wri_l_q_wri
connect \Y $83
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
wire width 1 $85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $85
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
wire width 1 $87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
cell $and $88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \lod_l_qn_lod
connect \Y $87
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
wire width 1 $89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
cell $and $90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_ld
connect \Y $89
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
wire width 1 $91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
cell $and $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $91
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
wire width 1 $93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $93
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
wire width 1 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
cell $and $96
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \oper_r__update
connect \Y $95
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:437"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
wire width 1 $97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:437"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr__rel [1] $97
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:271"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
wire width 1 \wr_any
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
wire width 1 $99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
cell $or $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \p_st_go
connect \Y $99
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
wire width 1 $101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
cell $or $102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \wr__go [0]
connect \Y $101
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
wire width 1 $103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:440"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
cell $or $104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \wr_any $103
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $and $106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $105
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $and $108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $107
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $or $111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \wr__rel [0]
connect \Y $110
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $112
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $or $113
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \wr__rel [1]
connect \Y $112
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $not $114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $112
connect \Y $109
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
wire width 1 $115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:442"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
cell $and $116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $109
connect \Y $115
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:443"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
wire width 1 $117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:443"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
cell $or $118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_st
connect \Y $117
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:443"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
wire width 1 $119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:443"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
cell $and $120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \done_o \wr_reset
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest1_o
process $group_77
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
end
process $group_78
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:451"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
switch { \wr__go [0] }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:451"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
case 1'1
assign \dest1_o \ldd_r
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest2_o
process $group_79
assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000
assign \ea \dest2_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
wire width 1 $121
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_80
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
switch { $121 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
case 1'1
assign \dest2_o \addr_r
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 2 \wrmask
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:461"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
wire width 3 $123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:461"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
wire width 3 $124
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:461"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
cell $and $125
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \wrmask $123 [1:0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:468"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468"
wire width 1 $126
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:468"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468"
cell $and $127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ldst_port0_is_ld_i $126
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
wire width 1 $128
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
cell $and $129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ldst_port0_data_len \oper_i__data_len
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+ wire width 96 $130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+ cell $pos $131
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 96
+ connect \A \addr_r
+ connect \Y $130
+ end
process $group_85
- assign \ldst_port0_addr_i 12'000000000000
- assign \ldst_port0_addr_i \addr_r [11:0]
+ assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \ldst_port0_addr_i $130
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:473"
- wire width 1 $130
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:473"
- cell $or $131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
+ wire width 1 $132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
+ cell $or $133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lod_l_q_lod
connect \B \sto_l_q_sto
- connect \Y $130
+ connect \Y $132
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:473"
- wire width 1 $132
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:473"
- cell $and $133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
+ wire width 1 $134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
+ cell $and $135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_ok
- connect \B $130
- connect \Y $132
+ connect \B $132
+ connect \Y $134
end
process $group_86
assign \ldst_port0_addr_i_ok 1'0
- assign \ldst_port0_addr_i_ok $132
+ assign \ldst_port0_addr_i_ok $134
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106"
wire width 1 \addr_exc_o
process $group_87
assign \addr_exc_o 1'0
assign \addr_ok \ldst_port0_addr_ok_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:11"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
wire width 64 \lddata_r
process $group_89
assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
switch { \oper_i__byte_reverse }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
case 1'1
assign \ldd_o \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:480"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:480"
case
assign \ldd_o \lddata_r
end
end
process $group_90
assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
switch { \oper_i__byte_reverse }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:480"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:480"
case
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:12"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
switch \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0001
assign \lddata_r [7:0] \ldst_port0_ld_data_o [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0010
assign \lddata_r [7:0] \ldst_port0_ld_data_o [15:8]
assign \lddata_r [15:8] \ldst_port0_ld_data_o [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0100
assign \lddata_r [7:0] \ldst_port0_ld_data_o [31:24]
assign \lddata_r [15:8] \ldst_port0_ld_data_o [23:16]
assign \lddata_r [23:16] \ldst_port0_ld_data_o [15:8]
assign \lddata_r [31:24] \ldst_port0_ld_data_o [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'1000
assign \lddata_r [7:0] \ldst_port0_ld_data_o [63:56]
assign \lddata_r [15:8] \ldst_port0_ld_data_o [55:48]
assign \ld_ok \ldst_port0_ld_data_o_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:11"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
wire width 64 \stdata_r
process $group_92
assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
switch { \oper_i__byte_reverse }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
case 1'1
assign \ldst_port0_st_data_i \src_r2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:491"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
case
assign \ldst_port0_st_data_i \stdata_r
end
end
process $group_93
assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
switch { \oper_i__byte_reverse }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:491"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
case
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:12"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
switch \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0001
assign \stdata_r [7:0] \src_r2 [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0010
assign \stdata_r [7:0] \src_r2 [15:8]
assign \stdata_r [15:8] \src_r2 [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'0100
assign \stdata_r [7:0] \src_r2 [31:24]
assign \stdata_r [15:8] \src_r2 [23:16]
assign \stdata_r [23:16] \src_r2 [15:8]
assign \stdata_r [31:24] \src_r2 [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/byterev.py:14"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
case 4'1000
assign \stdata_r [7:0] \src_r2 [63:56]
assign \stdata_r [15:8] \src_r2 [55:48]
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fus"
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module \fus
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 0 \ad__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 1 \ad__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 2 \st__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 3 \st__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 4 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 5 \clk
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 input 6 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 input 7 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 input 8 \oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 9 \oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 10 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 11 \oper_i__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 12 \oper_i__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 13 \oper_i__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 14 \oper_i__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 15 \oper_i__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 16 \oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 17 \oper_i__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 3 input 18 \oper_i__write_cr__data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 19 \oper_i__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 input 20 \oper_i__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 21 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 22 \oper_i__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 23 \oper_i__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 24 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 25 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 input 26 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 32 input 27 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 28 \oper_i__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 input 29 \oper_i__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
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wire width 1 input 30 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 31 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 4 input 32 \rdmaskn
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 input 33 \oper_i__insn_type$1
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 input 34 \oper_i__fn_unit$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 input 35 \oper_i__insn$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
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wire width 1 input 36 \oper_i__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 input 37 \oper_i__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 38 \issue_i$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 39 \busy_o$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 6 input 40 \rdmaskn$6
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
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wire width 7 input 41 \oper_i__insn_type$7
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 10 input 42 \oper_i__fn_unit$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 64 input 43 \oper_i__imm_data__imm$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 1 input 44 \oper_i__imm_data__imm_ok$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 1 input 45 \oper_i__lk$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 1 input 46 \oper_i__is_32bit$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
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wire width 32 input 47 \oper_i__insn$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
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wire width 1 input 48 \issue_i$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
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wire width 1 output 49 \busy_o$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
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wire width 4 input 50 \rdmaskn$16
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
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wire width 7 input 51 \oper_i__insn_type$17
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
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wire width 10 input 52 \oper_i__fn_unit$18
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
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+ wire width 6 input 59 \rdmaskn$23
+ attribute \enum_base_type "InternalOp"
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+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
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+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
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+ attribute \enum_value_0011100 "OP_DCBZ"
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+ attribute \enum_value_0100011 "OP_ISEL"
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+ attribute \enum_value_0101001 "OP_MADDLD"
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+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 7 input 60 \oper_i__insn_type$24
+ attribute \enum_base_type "Function"
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+ attribute \enum_value_0000000010 "ALU"
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+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
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+ wire width 10 input 61 \oper_i__fn_unit$25
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+ wire width 1 input 63 \oper_i__imm_data__imm_ok$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 64 \oper_i__lk$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 65 \oper_i__rc__rc$29
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 67 \oper_i__oe__oe$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 68 \oper_i__oe__oe_ok$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 69 \oper_i__invert_a$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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- wire width 2 input 62 \oper_i__input_carry$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 63 \oper_i__invert_out$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 64 \oper_i__write_cr__data$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 66 \oper_i__output_carry$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 68 \oper_i__is_signed$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 69 \oper_i__data_len$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 70 \oper_i__insn$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 71 \issue_i$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 72 \busy_o$38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 2 input 73 \rdmaskn$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 2 input 71 \oper_i__input_carry$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 72 \oper_i__invert_out$36
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+ wire width 3 input 73 \oper_i__write_cr__data$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 input 74 \oper_i__write_cr__ok$38
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+ wire width 1 input 77 \oper_i__is_signed$41
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+ wire width 32 input 79 \oper_i__insn$43
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+ wire width 1 input 80 \issue_i$44
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+ wire width 1 output 81 \busy_o$45
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+ wire width 2 input 82 \rdmaskn$46
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 74 \oper_i__insn_type$40
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 7 input 83 \oper_i__insn_type$47
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 10 input 75 \oper_i__fn_unit$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 76 \oper_i__imm_data__imm$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 77 \oper_i__imm_data__imm_ok$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 78 \oper_i__rc__rc$44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 79 \oper_i__rc__rc_ok$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 80 \oper_i__oe__oe$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 81 \oper_i__oe__oe_ok$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 82 \oper_i__write_cr__data$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 83 \oper_i__write_cr__ok$49
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+ wire width 10 input 84 \oper_i__fn_unit$48
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+ wire width 64 input 85 \oper_i__imm_data__imm$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 input 86 \oper_i__imm_data__imm_ok$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 input 87 \oper_i__rc__rc$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 input 89 \oper_i__oe__oe$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 input 90 \oper_i__oe__oe_ok$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 3 input 91 \oper_i__write_cr__data$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 input 92 \oper_i__write_cr__ok$56
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 84 \oper_i__input_carry$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 85 \oper_i__output_carry$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 86 \oper_i__input_cr$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 87 \oper_i__output_cr$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 88 \oper_i__is_32bit$54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 89 \oper_i__is_signed$55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 90 \oper_i__insn$56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 91 \issue_i$57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 92 \busy_o$58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 93 \rdmaskn$59
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+ wire width 1 input 96 \oper_i__output_cr$60
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+ wire width 32 input 99 \oper_i__insn$63
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+ wire width 1 input 100 \issue_i$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 101 \busy_o$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
+ wire width 4 input 102 \rdmaskn$66
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 input 94 \oper_i__insn_type$60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 64 input 95 \oper_i__imm_data__imm$61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 96 \oper_i__imm_data__imm_ok$62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 97 \oper_i__zero_a$63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 98 \oper_i__is_32bit$64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 99 \oper_i__is_signed$65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 input 100 \oper_i__data_len$66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 101 \oper_i__byte_reverse$67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 102 \oper_i__sign_extend$68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 103 \oper_i__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 104 \issue_i$69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 105 \busy_o$70
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 3 input 106 \rdmaskn$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 108 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 109 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 110 \rd__rel$72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 input 111 \rd__go$73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 112 \src1_i$74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 113 \rd__rel$75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 input 114 \rd__go$76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 115 \src1_i$77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 116 \rd__rel$78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 117 \rd__go$79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 118 \src1_i$80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 119 \rd__rel$81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 120 \rd__go$82
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 121 \src1_i$83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 122 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 123 \src2_i$84
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 124 \src2_i$85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 125 \src2_i$86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 126 \src2_i$87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 127 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 128 \src3_i$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 1 input 129 \src3_i$89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 130 \src4_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 131 \src4_i$90
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 32 input 132 \src3_i$91
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 133 \src4_i$92
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 134 \rd__rel$93
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 135 \rd__go$94
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 136 \src3_i$95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 137 \src5_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 138 \src6_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 139 \src1_i$96
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 140 \src2_i$97
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 141 \src4_i$98
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 142 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 143 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 input 144 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 145 \o_ok$99
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 146 \wr__rel$100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 147 \wr__go$101
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 148 \o_ok$102
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 149 \wr__rel$103
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 150 \wr__go$104
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 151 \o_ok$105
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 152 \wr__rel$106
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 153 \wr__go$107
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 154 \wr__rel$108
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 input 155 \wr__go$109
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 156 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 157 \o$110
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 158 \o$111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 159 \o$112
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 160 \o$113
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 161 \ea
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 162 \full_cr_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 32 output 163 \full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 164 \cr_a_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 165 \cr_a_ok$114
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 166 \cr_a_ok$115
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 167 \cr_a_ok$116
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 168 \cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 169 \cr_a$117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 170 \cr_a$118
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 171 \cr_a$119
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 172 \xer_ca_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 173 \xer_ca_ok$120
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 174 \xer_ca_ok$121
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 175 \xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 176 \xer_ca$122
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 177 \xer_ca$123
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 178 \xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 179 \xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 180 \xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 181 \xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 182 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 183 \wr__rel$124
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 184 \wr__go$125
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 185 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 186 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 187 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 188 \nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 189 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 190 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 191 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 192 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 193 \go_die_i$126
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 194 \shadown_i$127
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 195 \dest1_o$128
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 196 \go_die_i$129
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 197 \shadown_i$130
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 198 \dest1_o$131
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 199 \go_die_i$132
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 200 \shadown_i$133
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 201 \dest1_o$134
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 202 \go_die_i$135
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 203 \shadown_i$136
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 204 \dest1_o$137
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 205 \go_die_i$138
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 206 \load_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 207 \stwd_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 208 \shadown_i$139
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 output 209 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 210 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 output 211 \ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 output 212 \ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 213 \ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 input 214 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
- wire width 1 input 215 \ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 216 \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 217 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 218 \ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 219 \ldst_port0_st_data_i_ok
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 7 input 103 \oper_i__insn_type$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 64 input 104 \oper_i__imm_data__imm$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 105 \oper_i__imm_data__imm_ok$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 106 \oper_i__zero_a$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 107 \oper_i__is_32bit$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 108 \oper_i__is_signed$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 4 input 109 \oper_i__data_len$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 110 \oper_i__byte_reverse$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 111 \oper_i__sign_extend$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 input 112 \oper_i__update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 input 113 \issue_i$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 114 \busy_o$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
+ wire width 3 input 115 \rdmaskn$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 116 \rd__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 input 117 \rd__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 118 \src1_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 119 \rd__rel$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 input 120 \rd__go$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 121 \src1_i$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 122 \rd__rel$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 input 123 \rd__go$83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 124 \src1_i$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 125 \rd__rel$85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 input 126 \rd__go$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 127 \src1_i$87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 128 \rd__rel$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 input 129 \rd__go$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 130 \src1_i$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 131 \rd__rel$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 132 \rd__go$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 133 \src1_i$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 134 \src2_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 135 \src2_i$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 136 \src2_i$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 137 \src2_i$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 138 \src2_i$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 139 \src2_i$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 140 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 141 \src3_i$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 1 input 142 \src3_i$100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 2 input 143 \src4_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 2 input 144 \src4_i$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 32 input 145 \src3_i$102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 4 input 146 \src4_i$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 147 \rd__rel$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 input 148 \rd__go$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 4 input 149 \src3_i$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 4 input 150 \src5_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 4 input 151 \src6_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 152 \src1_i$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 153 \src3_i$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 154 \src2_i$109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 155 \src4_i$110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 156 \src4_i$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 157 \src5_i$112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 158 \src6_i$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 159 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 160 \wr__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 input 161 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 162 \o_ok$114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 163 \wr__rel$115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 164 \wr__go$116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 165 \o_ok$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 166 \wr__rel$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 input 167 \wr__go$119
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 168 \o_ok$120
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 169 \wr__rel$121
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 170 \wr__go$122
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 171 \o_ok$123
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 172 \wr__rel$124
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 173 \wr__go$125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 174 \wr__rel$126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 input 175 \wr__go$127
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 176 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 177 \o$128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 178 \o$129
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 179 \o$130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 180 \o$131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 181 \o$132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 182 \ea
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 183 \full_cr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 32 output 184 \full_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 185 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 186 \cr_a_ok$133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 187 \cr_a_ok$134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 188 \cr_a_ok$135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 189 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 190 \cr_a$136
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 191 \cr_a$137
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 192 \cr_a$138
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 193 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 194 \xer_ca_ok$139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 195 \xer_ca_ok$140
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 196 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 197 \xer_ca$141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 198 \xer_ca$142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 199 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 200 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 201 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 202 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 203 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 204 \wr__rel$143
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 205 \wr__go$144
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 206 \spr1_ok$145
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 207 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 208 \spr1$146
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 209 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 210 \spr2_ok$147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 211 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 212 \spr2$148
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 213 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 214 \nia_ok$149
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 215 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 216 \nia$150
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 217 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 218 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 219 \go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 220 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 221 \dest1_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 222 \go_die_i$151
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 223 \shadown_i$152
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 224 \dest1_o$153
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 225 \go_die_i$154
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 226 \shadown_i$155
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 227 \dest1_o$156
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 228 \go_die_i$157
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 229 \shadown_i$158
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 230 \dest1_o$159
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 231 \go_die_i$160
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 232 \shadown_i$161
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 233 \dest1_o$162
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 234 \go_die_i$163
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 235 \shadown_i$164
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 236 \dest1_o$165
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 237 \go_die_i$166
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
+ wire width 1 output 238 \load_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
+ wire width 1 output 239 \stwd_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 240 \shadown_i$167
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 241 \ldst_port0_is_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 242 \ldst_port0_is_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 243 \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 output 244 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 245 \ldst_port0_addr_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 246 \ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 input 247 \ldst_port0_addr_ok_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 248 \ldst_port0_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 249 \ldst_port0_ld_data_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 250 \ldst_port0_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 251 \ldst_port0_st_data_i_ok
cell \alu0 \alu0
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type
- connect \oper_i__fn_unit \oper_i__fn_unit
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok
- connect \oper_i__lk \oper_i__lk
- connect \oper_i__rc__rc \oper_i__rc__rc
- connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok
- connect \oper_i__oe__oe \oper_i__oe__oe
- connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok
- connect \oper_i__invert_a \oper_i__invert_a
- connect \oper_i__zero_a \oper_i__zero_a
- connect \oper_i__invert_out \oper_i__invert_out
- connect \oper_i__write_cr__data \oper_i__write_cr__data
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok
- connect \oper_i__input_carry \oper_i__input_carry
- connect \oper_i__output_carry \oper_i__output_carry
- connect \oper_i__input_cr \oper_i__input_cr
- connect \oper_i__output_cr \oper_i__output_cr
- connect \oper_i__is_32bit \oper_i__is_32bit
- connect \oper_i__is_signed \oper_i__is_signed
- connect \oper_i__data_len \oper_i__data_len
- connect \oper_i__insn \oper_i__insn
- connect \oper_i__byte_reverse \oper_i__byte_reverse
- connect \oper_i__sign_extend \oper_i__sign_extend
- connect \issue_i \issue_i
- connect \busy_o \busy_o
- connect \rdmaskn \rdmaskn
- connect \rd__rel \rd__rel
- connect \rd__go \rd__go
- connect \src1_i \src1_i
- connect \src2_i \src2_i
- connect \src3_i \src3_i$89
- connect \src4_i \src4_i
- connect \o_ok \o_ok
- connect \wr__rel \wr__rel
- connect \wr__go \wr__go
- connect \o \o
- connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
- connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
- connect \xer_ov_ok \xer_ov_ok
- connect \xer_ov \xer_ov
- connect \xer_so_ok \xer_so_ok
- connect \xer_so \xer_so
- connect \go_die_i \go_die_i
- connect \shadown_i \shadown_i
- connect \dest1_o \dest1_o
+ connect \oper_i__insn_type \oper_i__insn_type
+ connect \oper_i__fn_unit \oper_i__fn_unit
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok
+ connect \oper_i__lk \oper_i__lk
+ connect \oper_i__rc__rc \oper_i__rc__rc
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok
+ connect \oper_i__oe__oe \oper_i__oe__oe
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok
+ connect \oper_i__invert_a \oper_i__invert_a
+ connect \oper_i__zero_a \oper_i__zero_a
+ connect \oper_i__invert_out \oper_i__invert_out
+ connect \oper_i__write_cr__data \oper_i__write_cr__data
+ connect \oper_i__write_cr__ok \oper_i__write_cr__ok
+ connect \oper_i__input_carry \oper_i__input_carry
+ connect \oper_i__output_carry \oper_i__output_carry
+ connect \oper_i__input_cr \oper_i__input_cr
+ connect \oper_i__output_cr \oper_i__output_cr
+ connect \oper_i__is_32bit \oper_i__is_32bit
+ connect \oper_i__is_signed \oper_i__is_signed
+ connect \oper_i__data_len \oper_i__data_len
+ connect \oper_i__insn \oper_i__insn
+ connect \oper_i__byte_reverse \oper_i__byte_reverse
+ connect \oper_i__sign_extend \oper_i__sign_extend
+ connect \issue_i \issue_i
+ connect \busy_o \busy_o
+ connect \rdmaskn \rdmaskn
+ connect \rd__rel \rd__rel
+ connect \rd__go \rd__go
+ connect \src1_i \src1_i
+ connect \src2_i \src2_i
+ connect \src3_i \src3_i$100
+ connect \src4_i \src4_i
+ connect \o_ok \o_ok
+ connect \wr__rel \wr__rel
+ connect \wr__go \wr__go
+ connect \o \o
+ connect \cr_a_ok \cr_a_ok
+ connect \cr_a \cr_a
+ connect \xer_ca_ok \xer_ca_ok
+ connect \xer_ca \xer_ca
+ connect \xer_ov_ok \xer_ov_ok
+ connect \xer_ov \xer_ov
+ connect \xer_so_ok \xer_so_ok
+ connect \xer_so \xer_so
+ connect \go_die_i \go_die_i
+ connect \shadown_i \shadown_i
+ connect \dest1_o \dest1_o
+ end
+ cell \cr0 \cr0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$1
+ connect \oper_i__fn_unit \oper_i__fn_unit$2
+ connect \oper_i__insn \oper_i__insn$3
+ connect \oper_i__read_cr_whole \oper_i__read_cr_whole
+ connect \oper_i__write_cr_whole \oper_i__write_cr_whole
+ connect \issue_i \issue_i$4
+ connect \busy_o \busy_o$5
+ connect \rdmaskn \rdmaskn$6
+ connect \rd__rel \rd__rel$79
+ connect \rd__go \rd__go$80
+ connect \src1_i \src1_i$81
+ connect \src2_i \src2_i$94
+ connect \src3_i \src3_i$102
+ connect \src4_i \src4_i$103
+ connect \src5_i \src5_i
+ connect \src6_i \src6_i
+ connect \o_ok \o_ok$114
+ connect \wr__rel \wr__rel$115
+ connect \wr__go \wr__go$116
+ connect \o \o$128
+ connect \full_cr_ok \full_cr_ok
+ connect \full_cr \full_cr
+ connect \cr_a_ok \cr_a_ok$133
+ connect \cr_a \cr_a$136
+ connect \go_die_i \go_die_i$151
+ connect \shadown_i \shadown_i$152
+ connect \dest1_o \dest1_o$153
+ end
+ cell \branch0 \branch0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$7
+ connect \oper_i__fn_unit \oper_i__fn_unit$8
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$9
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$10
+ connect \oper_i__lk \oper_i__lk$11
+ connect \oper_i__is_32bit \oper_i__is_32bit$12
+ connect \oper_i__insn \oper_i__insn$13
+ connect \issue_i \issue_i$14
+ connect \busy_o \busy_o$15
+ connect \rdmaskn \rdmaskn$16
+ connect \rd__rel \rd__rel$104
+ connect \rd__go \rd__go$105
+ connect \src3_i \src3_i$106
+ connect \src1_i \src1_i$107
+ connect \src2_i \src2_i$109
+ connect \src4_i \src4_i$111
+ connect \spr1_ok \spr1_ok
+ connect \wr__rel \wr__rel$143
+ connect \wr__go \wr__go$144
+ connect \spr1 \spr1
+ connect \spr2_ok \spr2_ok
+ connect \spr2 \spr2
+ connect \nia_ok \nia_ok
+ connect \nia \nia
+ connect \go_die_i \go_die_i$154
+ connect \shadown_i \shadown_i$155
+ connect \dest1_o \dest1_o$156
+ end
+ cell \trap0 \trap0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$17
+ connect \oper_i__fn_unit \oper_i__fn_unit$18
+ connect \oper_i__insn \oper_i__insn$19
+ connect \oper_i__is_32bit \oper_i__is_32bit$20
+ connect \oper_i__traptype \oper_i__traptype
+ connect \oper_i__trapaddr \oper_i__trapaddr
+ connect \issue_i \issue_i$21
+ connect \busy_o \busy_o$22
+ connect \rdmaskn \rdmaskn$23
+ connect \rd__rel \rd__rel$82
+ connect \rd__go \rd__go$83
+ connect \src1_i \src1_i$84
+ connect \src2_i \src2_i$95
+ connect \src3_i \src3_i$108
+ connect \src4_i \src4_i$110
+ connect \src5_i \src5_i$112
+ connect \src6_i \src6_i$113
+ connect \o_ok \o_ok$117
+ connect \wr__rel \wr__rel$118
+ connect \wr__go \wr__go$119
+ connect \o \o$129
+ connect \spr1_ok \spr1_ok$145
+ connect \spr1 \spr1$146
+ connect \spr2_ok \spr2_ok$147
+ connect \spr2 \spr2$148
+ connect \nia_ok \nia_ok$149
+ connect \nia \nia$150
+ connect \msr_ok \msr_ok
+ connect \msr \msr
+ connect \go_die_i \go_die_i$157
+ connect \shadown_i \shadown_i$158
+ connect \dest1_o \dest1_o$159
+ end
+ cell \logical0 \logical0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$24
+ connect \oper_i__fn_unit \oper_i__fn_unit$25
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$26
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$27
+ connect \oper_i__lk \oper_i__lk$28
+ connect \oper_i__rc__rc \oper_i__rc__rc$29
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$30
+ connect \oper_i__oe__oe \oper_i__oe__oe$31
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$32
+ connect \oper_i__invert_a \oper_i__invert_a$33
+ connect \oper_i__zero_a \oper_i__zero_a$34
+ connect \oper_i__input_carry \oper_i__input_carry$35
+ connect \oper_i__invert_out \oper_i__invert_out$36
+ connect \oper_i__write_cr__data \oper_i__write_cr__data$37
+ connect \oper_i__write_cr__ok \oper_i__write_cr__ok$38
+ connect \oper_i__output_carry \oper_i__output_carry$39
+ connect \oper_i__is_32bit \oper_i__is_32bit$40
+ connect \oper_i__is_signed \oper_i__is_signed$41
+ connect \oper_i__data_len \oper_i__data_len$42
+ connect \oper_i__insn \oper_i__insn$43
+ connect \issue_i \issue_i$44
+ connect \busy_o \busy_o$45
+ connect \rdmaskn \rdmaskn$46
+ connect \rd__rel \rd__rel$85
+ connect \rd__go \rd__go$86
+ connect \src1_i \src1_i$87
+ connect \src2_i \src2_i$96
+ connect \o_ok \o_ok$120
+ connect \wr__rel \wr__rel$121
+ connect \wr__go \wr__go$122
+ connect \o \o$130
+ connect \cr_a_ok \cr_a_ok$134
+ connect \cr_a \cr_a$137
+ connect \xer_ca_ok \xer_ca_ok$139
+ connect \xer_ca \xer_ca$141
+ connect \go_die_i \go_die_i$160
+ connect \shadown_i \shadown_i$161
+ connect \dest1_o \dest1_o$162
+ end
+ cell \shiftrot0 \shiftrot0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$47
+ connect \oper_i__fn_unit \oper_i__fn_unit$48
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$49
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$50
+ connect \oper_i__rc__rc \oper_i__rc__rc$51
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$52
+ connect \oper_i__oe__oe \oper_i__oe__oe$53
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$54
+ connect \oper_i__write_cr__data \oper_i__write_cr__data$55
+ connect \oper_i__write_cr__ok \oper_i__write_cr__ok$56
+ connect \oper_i__input_carry \oper_i__input_carry$57
+ connect \oper_i__output_carry \oper_i__output_carry$58
+ connect \oper_i__input_cr \oper_i__input_cr$59
+ connect \oper_i__output_cr \oper_i__output_cr$60
+ connect \oper_i__is_32bit \oper_i__is_32bit$61
+ connect \oper_i__is_signed \oper_i__is_signed$62
+ connect \oper_i__insn \oper_i__insn$63
+ connect \issue_i \issue_i$64
+ connect \busy_o \busy_o$65
+ connect \rdmaskn \rdmaskn$66
+ connect \rd__rel \rd__rel$88
+ connect \rd__go \rd__go$89
+ connect \src1_i \src1_i$90
+ connect \src2_i \src2_i$97
+ connect \src3_i \src3_i
+ connect \src4_i \src4_i$101
+ connect \o_ok \o_ok$123
+ connect \wr__rel \wr__rel$124
+ connect \wr__go \wr__go$125
+ connect \o \o$131
+ connect \cr_a_ok \cr_a_ok$135
+ connect \cr_a \cr_a$138
+ connect \xer_ca_ok \xer_ca_ok$140
+ connect \xer_ca \xer_ca$142
+ connect \go_die_i \go_die_i$163
+ connect \shadown_i \shadown_i$164
+ connect \dest1_o \dest1_o$165
+ end
+ cell \ldst0 \ldst0
+ connect \ad__go \ad__go
+ connect \ad__rel \ad__rel
+ connect \st__go \st__go
+ connect \st__rel \st__rel
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$67
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$68
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$69
+ connect \oper_i__zero_a \oper_i__zero_a$70
+ connect \oper_i__is_32bit \oper_i__is_32bit$71
+ connect \oper_i__is_signed \oper_i__is_signed$72
+ connect \oper_i__data_len \oper_i__data_len$73
+ connect \oper_i__byte_reverse \oper_i__byte_reverse$74
+ connect \oper_i__sign_extend \oper_i__sign_extend$75
+ connect \oper_i__update \oper_i__update
+ connect \issue_i \issue_i$76
+ connect \busy_o \busy_o$77
+ connect \rdmaskn \rdmaskn$78
+ connect \rd__rel \rd__rel$91
+ connect \rd__go \rd__go$92
+ connect \src1_i \src1_i$93
+ connect \src2_i \src2_i$98
+ connect \src3_i \src3_i$99
+ connect \wr__rel \wr__rel$126
+ connect \wr__go \wr__go$127
+ connect \o \o$132
+ connect \ea \ea
+ connect \go_die_i \go_die_i$166
+ connect \load_mem_o \load_mem_o
+ connect \stwd_mem_o \stwd_mem_o
+ connect \shadown_i \shadown_i$167
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i
+ connect \ldst_port0_data_len \ldst_port0_data_len
+ connect \ldst_port0_addr_i \ldst_port0_addr_i
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active"
+module \st_active
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 3 \q_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \r_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_st_active
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_st_active
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_st_active
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_st_active
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_st_active 1'0
+ assign \q_st_active $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_st_active
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_st_active 1'0
+ assign \qn_st_active $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_st_active
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_st_active 1'0
+ assign \qlq_st_active $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active"
+module \ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 3 \q_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \r_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_ld_active
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_ld_active
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_ld_active
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_ld_active
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_ld_active 1'0
+ assign \q_ld_active $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_ld_active
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_ld_active 1'0
+ assign \qn_ld_active $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_ld_active
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_ld_active 1'0
+ assign \qlq_ld_active $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l"
+module \reset_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 4 \q_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_reset
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_reset
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ process $group_1
+ assign \q_reset 1'0
+ assign \q_reset \q_int
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_reset
+ connect \Y $7
+ end
+ process $group_2
+ assign \qn_reset 1'0
+ assign \qn_reset $7
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_reset
+ connect \B \q_int
+ connect \Y $9
+ end
+ process $group_3
+ assign \qlq_reset 1'0
+ assign \qlq_reset $9
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l"
+module \adrok_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 output 4 \qn_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 5 \q_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_addr_acked
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_addr_acked
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_addr_acked
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_addr_acked
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_addr_acked 1'0
+ assign \q_addr_acked $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_addr_acked
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_addr_acked 1'0
+ assign \qn_addr_acked $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_addr_acked
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_addr_acked 1'0
+ assign \qlq_addr_acked $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l"
+module \busy_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 4 \q_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_busy
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_busy
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_busy
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_busy
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_busy 1'0
+ assign \q_busy $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_busy
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_busy 1'0
+ assign \qn_busy $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_busy
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_busy 1'0
+ assign \qlq_busy $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l"
+module \cyc_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \r_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 4 \q_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_cyc
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_cyc
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ process $group_1
+ assign \q_cyc 1'0
+ assign \q_cyc \q_int
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_cyc
+ connect \Y $7
+ end
+ process $group_2
+ assign \qn_cyc 1'0
+ assign \qn_cyc $7
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_cyc
+ connect \B \q_int
+ connect \Y $9
+ end
+ process $group_3
+ assign \qlq_cyc 1'0
+ assign \qlq_cyc $9
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp"
+module \lenexp
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:129"
+ wire width 4 input 0 \len_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
+ wire width 4 input 1 \addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+ wire width 64 output 2 \lexp_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:133"
+ wire width 176 output 3 \rexp_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:147"
+ wire width 17 \binlen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+ wire width 21 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+ wire width 20 $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+ cell $sshl $3
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 20
+ connect \A 5'00001
+ connect \B \len_i
+ connect \Y $2
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+ wire width 21 $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+ cell $sub $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 20
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 21
+ connect \A $2
+ connect \B 1'1
+ connect \Y $4
+ end
+ connect $1 $4
+ process $group_0
+ assign \binlen 17'00000000000000000
+ assign \binlen $1 [16:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+ wire width 64 $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+ wire width 32 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+ cell $sshl $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 17
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 32
+ connect \A \binlen
+ connect \B \addr_i
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+ cell $pos $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 32
+ parameter \Y_WIDTH 64
+ connect \A $7
+ connect \Y $6
+ end
+ process $group_1
+ assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \lexp_o $6
+ sync init
+ end
+ process $group_2
+ assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0]
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l"
+module \valid_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 2 \s_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 3 \q_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \r_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_valid
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_valid
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_valid
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_valid
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_valid 1'0
+ assign \q_valid $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_valid
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_valid 1'0
+ assign \qn_valid $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_valid
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_valid 1'0
+ assign \qlq_valid $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem"
+module \pimem
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 input 2 \ldst_port0_is_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 3 \ldst_port0_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 input 4 \ldst_port0_is_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 input 5 \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 48 input 6 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 7 \ldst_port0_addr_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+ wire width 8 output 8 \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+ wire width 48 output 9 \x_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 10 \ldst_port0_addr_ok_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 input 11 \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 12 \ldst_port0_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 13 \ldst_port0_ld_data_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+ wire width 1 input 14 \x_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 15 \ldst_port0_st_data_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 16 \ldst_port0_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+ wire width 64 output 17 \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 18 \ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+ wire width 1 output 19 \x_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+ wire width 1 output 20 \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+ wire width 1 output 21 \m_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+ wire width 1 output 22 \x_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \st_active_s_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \st_active_q_st_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \st_active_r_st_active
+ cell \st_active \st_active
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_st_active \st_active_s_st_active
+ connect \q_st_active \st_active_q_st_active
+ connect \r_st_active \st_active_r_st_active
end
- cell \cr0 \cr0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \ld_active_s_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \ld_active_q_ld_active
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \ld_active_r_ld_active
+ cell \ld_active \ld_active
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$1
- connect \oper_i__fn_unit \oper_i__fn_unit$2
- connect \oper_i__insn \oper_i__insn$3
- connect \oper_i__read_cr_whole \oper_i__read_cr_whole
- connect \oper_i__write_cr_whole \oper_i__write_cr_whole
- connect \issue_i \issue_i$4
- connect \busy_o \busy_o$5
- connect \rdmaskn \rdmaskn$6
- connect \rd__rel \rd__rel$72
- connect \rd__go \rd__go$73
- connect \src1_i \src1_i$74
- connect \src2_i \src2_i$84
- connect \src3_i \src3_i$91
- connect \src4_i \src4_i$92
- connect \src5_i \src5_i
- connect \src6_i \src6_i
- connect \o_ok \o_ok$99
- connect \wr__rel \wr__rel$100
- connect \wr__go \wr__go$101
- connect \o \o$110
- connect \full_cr_ok \full_cr_ok
- connect \full_cr \full_cr
- connect \cr_a_ok \cr_a_ok$114
- connect \cr_a \cr_a$117
- connect \go_die_i \go_die_i$126
- connect \shadown_i \shadown_i$127
- connect \dest1_o \dest1_o$128
+ connect \s_ld_active \ld_active_s_ld_active
+ connect \q_ld_active \ld_active_q_ld_active
+ connect \r_ld_active \ld_active_r_ld_active
end
- cell \branch0 \branch0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \reset_l_s_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \reset_l_r_reset
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \reset_l_q_reset
+ cell \reset_l \reset_l
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$7
- connect \oper_i__fn_unit \oper_i__fn_unit$8
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$9
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$10
- connect \oper_i__lk \oper_i__lk$11
- connect \oper_i__is_32bit \oper_i__is_32bit$12
- connect \oper_i__insn \oper_i__insn$13
- connect \issue_i \issue_i$14
- connect \busy_o \busy_o$15
- connect \rdmaskn \rdmaskn$16
- connect \rd__rel \rd__rel$93
- connect \rd__go \rd__go$94
- connect \src3_i \src3_i$95
- connect \src1_i \src1_i$96
- connect \src2_i \src2_i$97
- connect \src4_i \src4_i$98
- connect \spr1_ok \spr1_ok
- connect \wr__rel \wr__rel$124
- connect \wr__go \wr__go$125
- connect \spr1 \spr1
- connect \spr2_ok \spr2_ok
- connect \spr2 \spr2
- connect \nia_ok \nia_ok
- connect \nia \nia
- connect \go_die_i \go_die_i$129
- connect \shadown_i \shadown_i$130
- connect \dest1_o \dest1_o$131
+ connect \s_reset \reset_l_s_reset
+ connect \r_reset \reset_l_r_reset
+ connect \q_reset \reset_l_q_reset
end
- cell \logical0 \logical0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \adrok_l_s_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \adrok_l_s_addr_acked$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \adrok_l_r_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \adrok_l_qn_addr_acked
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \adrok_l_q_addr_acked
+ cell \adrok_l \adrok_l
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$17
- connect \oper_i__fn_unit \oper_i__fn_unit$18
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$19
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$20
- connect \oper_i__lk \oper_i__lk$21
- connect \oper_i__rc__rc \oper_i__rc__rc$22
- connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$23
- connect \oper_i__oe__oe \oper_i__oe__oe$24
- connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$25
- connect \oper_i__invert_a \oper_i__invert_a$26
- connect \oper_i__zero_a \oper_i__zero_a$27
- connect \oper_i__input_carry \oper_i__input_carry$28
- connect \oper_i__invert_out \oper_i__invert_out$29
- connect \oper_i__write_cr__data \oper_i__write_cr__data$30
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok$31
- connect \oper_i__output_carry \oper_i__output_carry$32
- connect \oper_i__is_32bit \oper_i__is_32bit$33
- connect \oper_i__is_signed \oper_i__is_signed$34
- connect \oper_i__data_len \oper_i__data_len$35
- connect \oper_i__insn \oper_i__insn$36
- connect \issue_i \issue_i$37
- connect \busy_o \busy_o$38
- connect \rdmaskn \rdmaskn$39
- connect \rd__rel \rd__rel$75
- connect \rd__go \rd__go$76
- connect \src1_i \src1_i$77
- connect \src2_i \src2_i$85
- connect \o_ok \o_ok$102
- connect \wr__rel \wr__rel$103
- connect \wr__go \wr__go$104
- connect \o \o$111
- connect \cr_a_ok \cr_a_ok$115
- connect \cr_a \cr_a$118
- connect \xer_ca_ok \xer_ca_ok$120
- connect \xer_ca \xer_ca$122
- connect \go_die_i \go_die_i$132
- connect \shadown_i \shadown_i$133
- connect \dest1_o \dest1_o$134
+ connect \s_addr_acked \adrok_l_s_addr_acked
+ connect \r_addr_acked \adrok_l_r_addr_acked
+ connect \qn_addr_acked \adrok_l_qn_addr_acked
+ connect \q_addr_acked \adrok_l_q_addr_acked
end
- cell \shiftrot0 \shiftrot0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \busy_l_s_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \busy_l_r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \busy_l_q_busy
+ cell \busy_l \busy_l
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$40
- connect \oper_i__fn_unit \oper_i__fn_unit$41
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$42
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$43
- connect \oper_i__rc__rc \oper_i__rc__rc$44
- connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$45
- connect \oper_i__oe__oe \oper_i__oe__oe$46
- connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$47
- connect \oper_i__write_cr__data \oper_i__write_cr__data$48
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok$49
- connect \oper_i__input_carry \oper_i__input_carry$50
- connect \oper_i__output_carry \oper_i__output_carry$51
- connect \oper_i__input_cr \oper_i__input_cr$52
- connect \oper_i__output_cr \oper_i__output_cr$53
- connect \oper_i__is_32bit \oper_i__is_32bit$54
- connect \oper_i__is_signed \oper_i__is_signed$55
- connect \oper_i__insn \oper_i__insn$56
- connect \issue_i \issue_i$57
- connect \busy_o \busy_o$58
- connect \rdmaskn \rdmaskn$59
- connect \rd__rel \rd__rel$78
- connect \rd__go \rd__go$79
- connect \src1_i \src1_i$80
- connect \src2_i \src2_i$86
- connect \src3_i \src3_i
- connect \src4_i \src4_i$90
- connect \o_ok \o_ok$105
- connect \wr__rel \wr__rel$106
- connect \wr__go \wr__go$107
- connect \o \o$112
- connect \cr_a_ok \cr_a_ok$116
- connect \cr_a \cr_a$119
- connect \xer_ca_ok \xer_ca_ok$121
- connect \xer_ca \xer_ca$123
- connect \go_die_i \go_die_i$135
- connect \shadown_i \shadown_i$136
- connect \dest1_o \dest1_o$137
+ connect \s_busy \busy_l_s_busy
+ connect \r_busy \busy_l_r_busy
+ connect \q_busy \busy_l_q_busy
end
- cell \ldst0 \ldst0
- connect \ad__go \ad__go
- connect \ad__rel \ad__rel
- connect \st__go \st__go
- connect \st__rel \st__rel
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \cyc_l_s_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \cyc_l_r_cyc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \cyc_l_q_cyc
+ cell \cyc_l \cyc_l
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$60
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$61
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$62
- connect \oper_i__zero_a \oper_i__zero_a$63
- connect \oper_i__is_32bit \oper_i__is_32bit$64
- connect \oper_i__is_signed \oper_i__is_signed$65
- connect \oper_i__data_len \oper_i__data_len$66
- connect \oper_i__byte_reverse \oper_i__byte_reverse$67
- connect \oper_i__sign_extend \oper_i__sign_extend$68
- connect \oper_i__update \oper_i__update
- connect \issue_i \issue_i$69
- connect \busy_o \busy_o$70
- connect \rdmaskn \rdmaskn$71
- connect \rd__rel \rd__rel$81
- connect \rd__go \rd__go$82
- connect \src1_i \src1_i$83
- connect \src2_i \src2_i$87
- connect \src3_i \src3_i$88
- connect \wr__rel \wr__rel$108
- connect \wr__go \wr__go$109
- connect \o \o$113
- connect \ea \ea
- connect \go_die_i \go_die_i$138
- connect \load_mem_o \load_mem_o
- connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i \shadown_i$139
- connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
- connect \ldst_port0_is_st_i \ldst_port0_is_st_i
- connect \ldst_port0_data_len \ldst_port0_data_len
- connect \ldst_port0_addr_i \ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
- connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
- connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
- connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i \ldst_port0_st_data_i
- connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+ connect \s_cyc \cyc_l_s_cyc
+ connect \r_cyc \cyc_l_r_cyc
+ connect \q_cyc \cyc_l_q_cyc
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.mem"
-module \mem
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 5 input 1 \mem_r_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 5 input 2 \mem_w_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 64 output 3 \mem_r_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 64 input 4 \mem_w_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 8 input 5 \mem_w_en
- memory width 64 size 32 \mem
- cell $meminit $1
- parameter \MEMID "\\mem"
- parameter \ABITS 6
- parameter \WIDTH 64
- parameter \WORDS 32
- parameter \PRIORITY 0
- connect \ADDR 6'000000
- connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- end
- cell $memrd \rdport
- parameter \MEMID "\\mem"
- parameter \ABITS 5
- parameter \WIDTH 64
- parameter \CLK_ENABLE 1
- parameter \CLK_POLARITY 1
- parameter \TRANSPARENT 1
- connect \CLK \clk
- connect \EN 1'1
- connect \ADDR \mem_r_addr
- connect \DATA \mem_r_data
- end
- cell $memwr \wrport
- parameter \MEMID "\\mem"
- parameter \ABITS 5
- parameter \WIDTH 64
- parameter \CLK_ENABLE 1
- parameter \CLK_POLARITY 1
- parameter \PRIORITY 0
- connect \CLK \clk
- connect \EN { { \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] \mem_w_en [7] } { \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] \mem_w_en [6] } { \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] \mem_w_en [5] } { \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] \mem_w_en [4] } { \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] \mem_w_en [3] } { \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] \mem_w_en [2] } { \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] \mem_w_en [1] } { \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] \mem_w_en [0] } }
- connect \ADDR \mem_w_addr
- connect \DATA \mem_w_data
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:129"
+ wire width 4 \lenexp_len_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
+ wire width 4 \lenexp_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+ wire width 64 \lenexp_lexp_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:133"
+ wire width 176 \lenexp_rexp_o
+ cell \lenexp \lenexp
+ connect \len_i \lenexp_len_i
+ connect \addr_i \lenexp_addr_i
+ connect \lexp_o \lenexp_lexp_o
+ connect \rexp_o \lenexp_rexp_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \valid_l_s_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \valid_l_q_valid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \valid_l_r_valid
+ cell \valid_l \valid_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_valid \valid_l_s_valid
+ connect \q_valid \valid_l_q_valid
+ connect \r_valid \valid_l_r_valid
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.port0.busy_l"
-module \busy_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 3 \r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 4 \q_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+ cell $or $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_busy
+ connect \A \ldst_port0_st_data_i_ok
+ connect \B \ldst_port0_ld_data_o_ok
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ process $group_0
+ assign \cyc_l_s_cyc 1'0
+ assign \cyc_l_s_cyc 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+ switch { $1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+ case 1'1
+ assign \cyc_l_s_cyc 1'1
+ end
+ sync init
+ end
+ process $group_1
+ assign \cyc_l_r_cyc 1'1
+ assign \cyc_l_r_cyc 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+ switch { \cyc_l_q_cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+ case 1'1
+ assign \cyc_l_r_cyc 1'1
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
+ connect \A \ldst_port0_addr_i_ok
+ connect \B \adrok_l_qn_addr_acked
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ process $group_2
+ assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked
+ assign \adrok_l_s_addr_acked$next 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ switch { $3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ case 1'1
+ assign \adrok_l_s_addr_acked$next 1'1
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ switch { \ldst_port0_addr_i_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+ switch { \adrok_l_qn_addr_acked }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+ case 1'1
+ assign \adrok_l_s_addr_acked$next 1'1
+ end
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \adrok_l_s_addr_acked$next 1'0
+ end
+ sync init
+ update \adrok_l_s_addr_acked 1'0
+ sync posedge \clk
+ update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+ wire width 1 \reset_delay
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+ wire width 1 \reset_delay$next
+ process $group_3
+ assign \adrok_l_r_addr_acked 1'1
+ assign \adrok_l_r_addr_acked 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+ switch { \reset_delay }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+ case 1'1
+ assign \adrok_l_r_addr_acked 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ case 1'1
+ assign \adrok_l_r_addr_acked 1'1
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:176"
+ wire width 1 \lds
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
+ cell $and $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_busy
+ connect \A \ldst_port0_is_ld_i
+ connect \B \ldst_port0_busy_o
connect \Y $5
end
- process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \q_int$next 1'0
- end
+ process $group_4
+ assign \lds 1'0
+ assign \lds $5
sync init
- update \q_int 1'0
- sync posedge \clk
- update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:177"
+ wire width 1 \sts
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $not $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
+ cell $and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_busy
+ connect \A \ldst_port0_is_st_i
+ connect \B \ldst_port0_busy_o
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $and $10
+ process $group_5
+ assign \sts 1'0
+ assign \sts $7
+ sync init
+ end
+ process $group_6
+ assign \ld_active_s_ld_active 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+ switch { \sts \lds }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+ case 2'-1
+ assign \ld_active_s_ld_active 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
+ case 2'1-
+ end
+ sync init
+ end
+ process $group_7
+ assign \st_active_s_st_active 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+ switch { \sts \lds }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
+ case 2'1-
+ assign \st_active_s_st_active 1'1
+ end
+ sync init
+ end
+ process $group_8
+ assign \lenexp_len_i 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ assign \lenexp_len_i \ldst_port0_data_len
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ assign \lenexp_len_i \ldst_port0_data_len
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ wire width 4 $9
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ cell $pos $10
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $7
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 4
+ connect \A \ldst_port0_addr_i [2:0]
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $or $12
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ wire width 4 $11
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ cell $pos $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $9
- connect \B \s_busy
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 4
+ connect \A \ldst_port0_addr_i [2:0]
connect \Y $11
end
- process $group_1
- assign \q_busy 1'0
- assign \q_busy $11
+ process $group_9
+ assign \lenexp_addr_i 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ assign \lenexp_addr_i $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ assign \lenexp_addr_i $11
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_busy
+ connect \A \ldst_port0_addr_i_ok
+ connect \B \adrok_l_qn_addr_acked
connect \Y $13
end
- process $group_2
- assign \qn_busy 1'0
- assign \qn_busy $13
+ process $group_10
+ assign \valid_l_s_valid 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ switch { $13 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ case 1'1
+ assign \valid_l_s_valid 1'1
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ switch { \ldst_port0_addr_i_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ case 1'1
+ assign \valid_l_s_valid 1'1
+ end
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ cell $and $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_busy
- connect \B \q_int
+ connect \A \ldst_port0_addr_i_ok
+ connect \B \adrok_l_qn_addr_acked
connect \Y $15
end
- process $group_3
- assign \qlq_busy 1'0
- assign \qlq_busy $15
+ process $group_11
+ assign \x_mask_i 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ switch { $15 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ case 1'1
+ assign \x_mask_i \lenexp_lexp_o [7:0]
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ switch { \ldst_port0_addr_i_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ case 1'1
+ assign \x_mask_i \lenexp_lexp_o [7:0]
+ end
+ end
sync init
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.port0.cyc_l"
-module \cyc_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 3 \r_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 4 \q_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_cyc
- connect \Y $1
+ connect \A \ldst_port0_addr_i_ok
+ connect \B \adrok_l_qn_addr_acked
+ connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $and $4
+ process $group_12
+ assign \x_addr_i 48'000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ switch { $17 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ case 1'1
+ assign \x_addr_i \ldst_port0_addr_i
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ switch { \ldst_port0_addr_i_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ case 1'1
+ assign \x_addr_i \ldst_port0_addr_i
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
- connect \Y $3
+ connect \A \ldst_port0_addr_i_ok
+ connect \B \adrok_l_qn_addr_acked
+ connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
+ process $group_13
+ assign \ldst_port0_addr_ok_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ switch { \ld_active_q_ld_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ switch { $19 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+ case 1'1
+ assign \ldst_port0_addr_ok_o 1'1
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ switch { \st_active_q_st_active }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ switch { \ldst_port0_addr_i_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+ switch { \adrok_l_qn_addr_acked }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+ case 1'1
+ assign \ldst_port0_addr_ok_o 1'1
+ end
+ end
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_cyc
- connect \Y $5
+ connect \A \ld_active_q_ld_active
+ connect \B \adrok_l_q_addr_acked
+ connect \Y $21
end
- process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+ cell $not $24
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_busy_o
+ connect \Y $23
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ wire width 1 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ cell $and $26
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \st_active_q_st_active
+ connect \B \ldst_port0_st_data_i_ok
+ connect \Y $25
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
+ cell $not $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_busy_o
+ connect \Y $27
+ end
+ process $group_14
+ assign \reset_l_s_reset 1'0
+ assign \reset_l_s_reset 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ switch { $21 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
case 1'1
- assign \q_int$next 1'0
+ assign \reset_l_s_reset $23
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ switch { $25 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ case 1'1
+ assign \reset_l_s_reset $27
end
sync init
- update \q_int 1'0
- sync posedge \clk
- update \q_int \q_int$next
end
- process $group_1
- assign \q_cyc 1'0
- assign \q_cyc \q_int
+ process $group_15
+ assign \reset_l_r_reset 1'1
+ assign \reset_l_r_reset 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ case 1'1
+ assign \reset_l_r_reset 1'1
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
+ wire width 64 \lddata
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+ wire width 176 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
+ wire width 176 $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
+ cell $and $31
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 176
+ parameter \Y_WIDTH 176
+ connect \A \m_ld_data_o
+ connect \B \lenexp_rexp_o
+ connect \Y $30
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+ wire width 8 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+ cell $mul $33
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 8
+ connect \A \lenexp_addr_i
+ connect \B 4'1000
+ connect \Y $32
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+ wire width 176 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+ cell $sshr $35
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 176
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 176
+ connect \A $30
+ connect \B $32
+ connect \Y $34
+ end
+ connect $29 $34
+ process $group_16
+ assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \lddata $29 [63:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ wire width 1 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ cell $and $37
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_cyc
- connect \Y $7
+ connect \A \ld_active_q_ld_active
+ connect \B \adrok_l_q_addr_acked
+ connect \Y $36
end
- process $group_2
- assign \qn_cyc 1'0
- assign \qn_cyc $7
+ process $group_17
+ assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ switch { $36 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ case 1'1
+ assign \ldst_port0_ld_data_o \lddata
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ wire width 1 $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ cell $and $39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_cyc
- connect \B \q_int
- connect \Y $9
+ connect \A \ld_active_q_ld_active
+ connect \B \adrok_l_q_addr_acked
+ connect \Y $38
end
- process $group_3
- assign \qlq_cyc 1'0
- assign \qlq_cyc $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+ cell $not $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_busy_o
+ connect \Y $40
+ end
+ process $group_18
+ assign \ldst_port0_ld_data_o_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ switch { $38 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+ case 1'1
+ assign \ldst_port0_ld_data_o_ok $40
+ end
sync init
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.port0"
-module \port0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 input 2 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:112"
- wire width 1 output 3 \ldst_port0_busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 input 4 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 5 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 6 \ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 input 7 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \busy_l_s_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \busy_l_r_busy
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \busy_l_q_busy
- cell \busy_l \busy_l
- connect \rst \rst
- connect \clk \clk
- connect \s_busy \busy_l_s_busy
- connect \r_busy \busy_l_r_busy
- connect \q_busy \busy_l_q_busy
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232"
+ wire width 64 \stdata
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ wire width 1 $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ cell $and $43
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \st_active_q_st_active
+ connect \B \ldst_port0_st_data_i_ok
+ connect \Y $42
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \cyc_l_s_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \cyc_l_r_cyc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \cyc_l_q_cyc
- cell \cyc_l \cyc_l
- connect \rst \rst
- connect \clk \clk
- connect \s_cyc \cyc_l_s_cyc
- connect \r_cyc \cyc_l_r_cyc
- connect \q_cyc \cyc_l_q_cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+ wire width 319 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+ wire width 8 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+ cell $mul $46
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 8
+ connect \A \lenexp_addr_i
+ connect \B 4'1000
+ connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:150"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:150"
- cell $or $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+ wire width 319 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+ cell $sshl $48
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 319
+ connect \A \ldst_port0_st_data_i
+ connect \B $45
+ connect \Y $47
+ end
+ connect $44 $47
+ process $group_19
+ assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ switch { $42 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ case 1'1
+ assign \stdata $44 [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ wire width 1 $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_st_data_i_ok
- connect \B \ldst_port0_ld_data_o_ok
- connect \Y $1
+ connect \A \st_active_q_st_active
+ connect \B \ldst_port0_st_data_i_ok
+ connect \Y $49
+ end
+ process $group_20
+ assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ switch { $49 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+ case 1'1
+ assign \x_st_data_i \stdata
+ end
+ sync init
+ end
+ process $group_21
+ assign \reset_delay$next \reset_delay
+ assign \reset_delay$next \reset_l_q_reset
+ sync init
+ update \reset_delay 1'0
+ sync posedge \clk
+ update \reset_delay \reset_delay$next
end
- process $group_0
- assign \cyc_l_s_cyc 1'0
- assign \cyc_l_s_cyc 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:150"
- switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:150"
+ process $group_22
+ assign \ld_active_r_ld_active 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
case 1'1
- assign \cyc_l_s_cyc 1'1
+ assign \ld_active_r_ld_active 1'1
end
sync init
end
- process $group_1
- assign \cyc_l_r_cyc 1'1
- assign \cyc_l_r_cyc 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:153"
- switch { \cyc_l_q_cyc }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:153"
+ process $group_23
+ assign \st_active_r_st_active 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
case 1'1
- assign \cyc_l_r_cyc 1'1
+ assign \st_active_r_st_active 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:142"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:142"
- cell $or $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+ cell $or $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
connect \B \ldst_port0_is_st_i
- connect \Y $3
+ connect \Y $51
end
- process $group_2
+ process $group_24
assign \busy_l_s_busy 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:142"
- switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:142"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+ switch { $51 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
case 1'1
assign \busy_l_s_busy 1'1
end
sync init
end
- process $group_3
+ process $group_25
assign \busy_l_r_busy 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
switch { \ldst_port0_addr_exc_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
case 1'1
assign \busy_l_r_busy 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
switch { \cyc_l_q_cyc }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:153"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
case 1'1
assign \busy_l_r_busy 1'1
end
sync init
end
- process $group_4
+ process $group_26
assign \ldst_port0_busy_o 1'0
assign \ldst_port0_busy_o \busy_l_q_busy
sync init
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.st_active"
-module \st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 3 \q_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 4 \r_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r_st_active
- connect \Y $1
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $and $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
- connect \Y $3
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_st_active
- connect \Y $5
- end
- process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \q_int$next 1'0
- end
+ process $group_27
+ assign \x_ld_i 1'0
+ assign \x_ld_i \ldst_port0_is_ld_i
sync init
- update \q_int 1'0
- sync posedge \clk
- update \q_int \q_int$next
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $not $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r_st_active
- connect \Y $7
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $and $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $7
- connect \Y $9
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $or $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $9
- connect \B \s_st_active
- connect \Y $11
end
- process $group_1
- assign \q_st_active 1'0
- assign \q_st_active $11
+ process $group_28
+ assign \x_st_i 1'0
+ assign \x_st_i \ldst_port0_is_st_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_st_active
- connect \Y $13
+ process $group_29
+ assign \m_valid_i 1'0
+ assign \m_valid_i \valid_l_q_valid
+ sync init
end
- process $group_2
- assign \qn_st_active 1'0
- assign \qn_st_active $13
+ process $group_30
+ assign \x_valid_i 1'0
+ assign \x_valid_i \valid_l_q_valid
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
+ wire width 1 $53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
+ cell $not $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_st_active
- connect \B \q_int
- connect \Y $15
+ connect \A \ldst_port0_busy_o
+ connect \Y $53
end
- process $group_3
- assign \qlq_st_active 1'0
- assign \qlq_st_active $15
+ process $group_31
+ assign \valid_l_r_valid 1'1
+ assign \valid_l_r_valid $53
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.ld_active"
-module \ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l"
+module \idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 3 \q_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 4 \r_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 output 2 \q_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 input 3 \s_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \r_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_ld_active
+ connect \A \r_idx_l
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $3
- connect \B \s_ld_active
+ connect \B \s_idx_l
connect \Y $5
end
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
sync posedge \clk
update \q_int \q_int$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_ld_active
+ connect \A \r_idx_l
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $9
- connect \B \s_ld_active
+ connect \B \s_idx_l
connect \Y $11
end
process $group_1
- assign \q_ld_active 1'0
- assign \q_ld_active $11
+ assign \q_idx_l 1'0
+ assign \q_idx_l $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \qn_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_ld_active
+ connect \A \q_idx_l
connect \Y $13
end
process $group_2
- assign \qn_ld_active 1'0
- assign \qn_ld_active $13
+ assign \qn_idx_l 1'0
+ assign \qn_idx_l $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qlq_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_ld_active
+ connect \A \q_idx_l
connect \B \q_int
connect \Y $15
end
process $group_3
- assign \qlq_ld_active 1'0
- assign \qlq_ld_active $15
+ assign \qlq_idx_l 1'0
+ assign \qlq_idx_l $15
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.reset_l"
-module \reset_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l"
+module \reset_l$82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 input 2 \s_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 input 3 \r_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 output 4 \q_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65"
wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \r_reset
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
process $group_0
assign \q_int$next \q_int
assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \q_int$next 1'0
assign \q_reset \q_int
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \qn_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \qn_reset $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
wire width 1 \qlq_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.adrok_l"
-module \adrok_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 3 \r_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 output 4 \qn_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 5 \q_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r_addr_acked
- connect \Y $1
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $and $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
- connect \Y $3
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_addr_acked
- connect \Y $5
- end
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick"
+module \pick
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
+ wire width 1 input 0 \i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
+ wire width 1 output 1 \o
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
+ wire width 1 output 2 \n
process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
+ assign \o 1'0
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
+ switch { \i }
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
case 1'1
- assign \q_int$next 1'0
+ assign \o 1'0
end
- sync init
- update \q_int 1'0
- sync posedge \clk
- update \q_int \q_int$next
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $not $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r_addr_acked
- connect \Y $7
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $and $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $7
- connect \Y $9
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $or $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $9
- connect \B \s_addr_acked
- connect \Y $11
- end
- process $group_1
- assign \q_addr_acked 1'0
- assign \q_addr_acked $11
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \q_addr_acked
- connect \Y $13
- end
- process $group_2
- assign \qn_addr_acked 1'0
- assign \qn_addr_acked $13
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $16
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
+ cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_addr_acked
- connect \B \q_int
- connect \Y $15
- end
- process $group_3
- assign \qlq_addr_acked 1'0
- assign \qlq_addr_acked $15
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem.lenexp"
-module \lenexp
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:129"
- wire width 4 input 0 \len_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:130"
- wire width 4 input 1 \addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:133"
- wire width 176 output 2 \rexp_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:131"
- wire width 64 output 3 \lexp_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:147"
- wire width 17 \binlen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:149"
- wire width 21 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:149"
- wire width 20 $2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:149"
- cell $sshl $3
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 20
- connect \A 5'00001
- connect \B \len_i
- connect \Y $2
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:149"
- wire width 21 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:149"
- cell $sub $5
- parameter \A_SIGNED 0
- parameter \A_WIDTH 20
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 21
- connect \A $2
- connect \B 1'1
- connect \Y $4
- end
- connect $1 $4
- process $group_0
- assign \binlen 17'00000000000000000
- assign \binlen $1 [16:0]
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:150"
- wire width 64 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:150"
- wire width 32 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $sshl $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 17
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 32
- connect \A \binlen
- connect \B \addr_i
- connect \Y $7
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:150"
- cell $pos $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \Y_WIDTH 64
- connect \A $7
- connect \Y $6
+ connect \A \i
+ connect \B 1'0
+ connect \Y $1
end
process $group_1
- assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \lexp_o $6
- sync init
- end
- process $group_2
- assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0]
+ assign \n 1'0
+ assign \n $1
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.pimem"
-module \pimem
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0"
+module \l0$81
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
wire width 1 input 2 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:112"
- wire width 1 output 3 \ldst_port0_busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 input 4 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 input 5 \ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 input 6 \ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 7 \ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 input 3 \ldst_port0_is_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 input 4 \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 input 5 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 6 \ldst_port0_addr_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 output 7 \ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
wire width 1 output 8 \ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 9 \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 10 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 11 \ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 12 \ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 input 13 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 5 \mem_mem_r_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 5 \mem_mem_w_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 64 \mem_mem_r_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 64 \mem_mem_w_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 8 \mem_mem_w_en
- cell \mem \mem
- connect \clk \clk
- connect \mem_r_addr \mem_mem_r_addr
- connect \mem_w_addr \mem_mem_w_addr
- connect \mem_r_data \mem_mem_r_data
- connect \mem_w_data \mem_mem_w_data
- connect \mem_w_en \mem_mem_w_en
- end
- cell \port0 \port0
- connect \rst \rst
- connect \clk \clk
- connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
- connect \ldst_port0_busy_o \ldst_port0_busy_o
- connect \ldst_port0_is_st_i \ldst_port0_is_st_i
- connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
- connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \st_active_s_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \st_active_q_st_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \st_active_r_st_active
- cell \st_active \st_active
- connect \rst \rst
- connect \clk \clk
- connect \s_st_active \st_active_s_st_active
- connect \q_st_active \st_active_q_st_active
- connect \r_st_active \st_active_r_st_active
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \ld_active_s_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \ld_active_q_ld_active
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \ld_active_r_ld_active
- cell \ld_active \ld_active
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 11 \ldst_port0_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 12 \ldst_port0_st_data_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 13 \ldst_port0_is_ld_i$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 input 14 \ldst_port0_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 15 \ldst_port0_is_st_i$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 16 \ldst_port0_data_len$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 48 output 17 \ldst_port0_addr_i$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 18 \ldst_port0_addr_i_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 input 19 \ldst_port0_addr_ok_o$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 20 \ldst_port0_ld_data_o$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 21 \ldst_port0_ld_data_o_ok$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 22 \ldst_port0_st_data_i_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 23 \ldst_port0_st_data_i$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 24 \ldst_port0_addr_exc_o$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 output 25 \ldst_port0_go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 input 26 \ldst_port0_go_die_i$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 27 \ldst_port0_busy_o$13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \idx_l_q_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
+ wire width 1 \idx_l_s_idx_l
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \idx_l_r_idx_l
+ cell \idx_l \idx_l
connect \rst \rst
connect \clk \clk
- connect \s_ld_active \ld_active_s_ld_active
- connect \q_ld_active \ld_active_q_ld_active
- connect \r_ld_active \ld_active_r_ld_active
+ connect \q_idx_l \idx_l_q_idx_l
+ connect \s_idx_l \idx_l_s_idx_l
+ connect \r_idx_l \idx_l_r_idx_l
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57"
wire width 1 \reset_l_s_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \reset_l_r_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \reset_l_q_reset
- cell \reset_l \reset_l
+ cell \reset_l$82 \reset_l
connect \rst \rst
connect \clk \clk
connect \s_reset \reset_l_s_reset
connect \r_reset \reset_l_r_reset
connect \q_reset \reset_l_q_reset
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \adrok_l_s_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \adrok_l_s_addr_acked$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \adrok_l_r_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \adrok_l_qn_addr_acked
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \adrok_l_q_addr_acked
- cell \adrok_l \adrok_l
- connect \rst \rst
- connect \clk \clk
- connect \s_addr_acked \adrok_l_s_addr_acked
- connect \r_addr_acked \adrok_l_r_addr_acked
- connect \qn_addr_acked \adrok_l_qn_addr_acked
- connect \q_addr_acked \adrok_l_q_addr_acked
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:129"
- wire width 4 \lenexp_len_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:130"
- wire width 4 \lenexp_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:133"
- wire width 176 \lenexp_rexp_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/scoreboard/addr_match.py:131"
- wire width 64 \lenexp_lexp_o
- cell \lenexp \lenexp
- connect \len_i \lenexp_len_i
- connect \addr_i \lenexp_addr_i
- connect \rexp_o \lenexp_rexp_o
- connect \lexp_o \lenexp_lexp_o
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
+ wire width 1 \pick_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
+ wire width 1 \pick_o
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
+ wire width 1 \pick_n
+ cell \pick \pick
+ connect \i \pick_i
+ connect \o \pick_o
+ connect \n \pick_n
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:246"
- wire width 1 \lds
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:249"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:249"
- cell $and $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:221"
+ wire width 1 $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:221"
+ cell $or $15
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ldst_port0_is_ld_i
- connect \B \ldst_port0_busy_o
- connect \Y $1
+ connect \B \ldst_port0_is_st_i
+ connect \Y $14
end
process $group_0
- assign \lds 1'0
- assign \lds $1
+ assign \pick_i 1'0
+ assign \pick_i { $14 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:247"
- wire width 1 \sts
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:250"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:250"
- cell $and $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 1 \idx_l$16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38"
+ wire width 1 \idx_l$16$next
+ process $group_1
+ assign \idx_l$16$next \idx_l$16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign \idx_l$16$next \pick_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \idx_l$16$next 1'0
+ end
+ sync init
+ update \idx_l$16 1'0
+ sync posedge \clk
+ update \idx_l$16 \idx_l$16$next
+ end
+ process $group_2
+ assign { } 0'0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ case 1'1
+ assign { } {}
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42"
+ case
+ assign { } {}
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_is_st_i
- connect \B \ldst_port0_busy_o
- connect \Y $3
+ connect \A \pick_n
+ connect \Y $17
end
- process $group_1
- assign \sts 1'0
- assign \sts $3
+ process $group_3
+ assign \idx_l_s_idx_l 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+ switch { $17 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+ case 1'1
+ assign \idx_l_s_idx_l 1'1
+ end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- cell $and $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+ cell $not $20
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_addr_i_ok
- connect \B \adrok_l_qn_addr_acked
- connect \Y $5
+ connect \A \ldst_port0_busy_o
+ connect \Y $19
end
- process $group_2
- assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked
- assign \adrok_l_s_addr_acked$next 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- switch { \ld_active_q_ld_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
+ process $group_4
+ assign \reset_l_s_reset 1'0
+ assign \reset_l_s_reset 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+ switch { $19 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
case 1'1
- assign \adrok_l_s_addr_acked$next 1'1
+ assign \reset_l_s_reset 1'1
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- switch { \st_active_q_st_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
+ sync init
+ end
+ process $group_5
+ assign \reset_l_r_reset 1'1
+ assign \reset_l_r_reset 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
- switch { \ldst_port0_addr_i_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:293"
- switch { \adrok_l_qn_addr_acked }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:293"
- case 1'1
- assign \adrok_l_s_addr_acked$next 1'1
- end
+ assign \reset_l_r_reset 1'1
+ end
+ sync init
+ end
+ process $group_6
+ assign \ldst_port0_is_ld_i$1 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:115"
+ switch { }
+ case 0'
+ assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
+ sync init
+ end
+ process $group_7
+ assign \ldst_port0_is_st_i$2 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \adrok_l_s_addr_acked$next 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:116"
+ switch { }
+ case 0'
+ assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i
+ end
end
sync init
- update \adrok_l_s_addr_acked 1'0
- sync posedge \clk
- update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:330"
- wire width 1 \reset_delay
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:330"
- wire width 1 \reset_delay$next
- process $group_3
- assign \adrok_l_r_addr_acked 1'1
- assign \adrok_l_r_addr_acked 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:332"
- switch { \reset_delay }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:332"
+ process $group_8
+ assign \ldst_port0_data_len$3 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \adrok_l_r_addr_acked 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:117"
+ switch { }
+ case 0'
+ assign \ldst_port0_data_len$3 \ldst_port0_data_len
+ end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
+ sync init
+ end
+ process $group_9
+ assign \ldst_port0_go_die_i 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \adrok_l_r_addr_acked 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118"
+ switch { }
+ case 0'
+ assign \ldst_port0_go_die_i \ldst_port0_go_die_i$12
+ end
end
sync init
end
- process $group_4
- assign \ld_active_s_ld_active 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:264"
- switch { \sts \lds }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:264"
- case 2'-1
- assign \ld_active_s_ld_active 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:266"
- case 2'1-
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+ wire width 96 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+ wire width 96 $22
+ connect $22 \ldst_port0_addr_i
+ process $group_10
+ assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+ switch { }
+ case 0'
+ assign \ldst_port0_addr_i$4 $22 [47:0]
+ end
end
sync init
end
- process $group_5
- assign \st_active_s_st_active 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:264"
- switch { \sts \lds }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:264"
- case 2'-1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:266"
- case 2'1-
- assign \st_active_s_st_active 1'1
+ process $group_11
+ assign \ldst_port0_addr_i_ok$5 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120"
+ switch { }
+ case 0'
+ assign \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok
+ end
end
sync init
end
- process $group_6
- assign \lenexp_len_i 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- switch { \ld_active_q_ld_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
+ process $group_12
+ assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ldst_port0_st_data_i_ok$9 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \lenexp_len_i \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121"
+ switch { }
+ case 0'
+ assign { \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i$10 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
+ end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- switch { \st_active_q_st_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
+ sync init
+ end
+ process $group_14
+ assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ldst_port0_ld_data_o_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \lenexp_len_i \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122"
+ switch { }
+ case 0'
+ assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o$7 }
+ end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
- wire width 4 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 4
- connect \A \ldst_port0_addr_i [2:0]
- connect \Y $7
+ process $group_16
+ assign \ldst_port0_busy_o$13 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
+ switch { }
+ case 0'
+ assign \ldst_port0_busy_o$13 \ldst_port0_busy_o
+ end
+ end
+ sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
- wire width 4 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 4
- connect \A \ldst_port0_addr_i [2:0]
- connect \Y $9
+ process $group_17
+ assign \ldst_port0_addr_ok_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124"
+ switch { }
+ case 0'
+ assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
+ end
+ end
+ sync init
end
- process $group_7
- assign \lenexp_addr_i 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- switch { \ld_active_q_ld_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
+ process $group_18
+ assign \ldst_port0_addr_exc_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+ switch { \idx_l_q_idx_l }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
case 1'1
- assign \lenexp_addr_i $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125"
+ switch { }
+ case 0'
+ assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
+ end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- switch { \st_active_q_st_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:251"
+ wire width 1 \reset_delay
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:251"
+ wire width 1 \reset_delay$next
+ process $group_19
+ assign \reset_delay$next \reset_delay
+ assign \reset_delay$next \reset_l_q_reset
+ sync init
+ update \reset_delay 1'0
+ sync posedge \clk
+ update \reset_delay \reset_delay$next
+ end
+ process $group_20
+ assign \idx_l_r_idx_l 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+ switch { \reset_l_q_reset }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
case 1'1
- assign \lenexp_addr_i $9
+ assign \idx_l_r_idx_l 1'1
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- cell $and $12
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem"
+module \lsmem
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+ wire width 8 input 2 \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+ wire width 48 input 3 \x_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 output 4 \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 \m_ld_data_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+ wire width 1 output 5 \x_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+ wire width 64 input 6 \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+ wire width 1 input 7 \x_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+ wire width 1 input 8 \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+ wire width 1 input 9 \m_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+ wire width 1 input 10 \x_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 11 \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 \dbus__cyc$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 1 input 12 \x_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 13 \dbus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 14 \dbus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 15 \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 \dbus__stb$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 input 16 \dbus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 45 output 17 \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 45 \dbus__adr$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 8 output 18 \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 8 \dbus__sel$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 19 \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 \dbus__we$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 output 20 \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 \dbus__dat_w$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+ wire width 1 input 21 \m_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+ wire width 1 output 22 \m_load_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+ wire width 1 \m_load_err_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+ wire width 1 output 23 \m_store_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+ wire width 1 \m_store_err_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+ wire width 45 output 24 \m_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+ wire width 45 \m_badaddr_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+ wire width 1 output 25 \m_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_addr_i_ok
- connect \B \adrok_l_qn_addr_acked
- connect \Y $11
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $1
end
- process $group_8
- assign \mem_mem_r_addr 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- switch { \ld_active_q_ld_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- switch { $11 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- case 1'1
- assign \mem_mem_r_addr \ldst_port0_addr_i [11:3] [4:0]
- end
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $1
+ connect \B \x_valid_i
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_stall_i
+ connect \Y $5
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B $5
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbus__ack
+ connect \B \dbus__err
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $not $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_valid_i
+ connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- cell $and $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_addr_i_ok
- connect \B \adrok_l_qn_addr_acked
+ connect \A $9
+ connect \B $11
connect \Y $13
end
- process $group_9
- assign \ldst_port0_addr_ok_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- switch { \ld_active_q_ld_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:274"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
+ process $group_0
+ assign \dbus__cyc$next \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $7 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
switch { $13 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:279"
- case 1'1
- assign \ldst_port0_addr_ok_o 1'1
- end
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- switch { \st_active_q_st_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
- switch { \ldst_port0_addr_i_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:293"
- switch { \adrok_l_qn_addr_acked }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:293"
- case 1'1
- assign \ldst_port0_addr_ok_o 1'1
- end
+ assign \dbus__cyc$next 1'0
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__cyc$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
end
- sync init
- end
- process $group_10
- assign \mem_mem_w_addr 5'00000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
- switch { \st_active_q_st_active }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:286"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
- switch { \ldst_port0_addr_i_ok }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:291"
- case 1'1
- assign \mem_mem_w_addr \ldst_port0_addr_i [11:3] [4:0]
- end
+ assign \dbus__cyc$next 1'0
end
sync init
+ update \dbus__cyc 1'0
+ sync posedge \clk
+ update \dbus__cyc \dbus__cyc$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- cell $and $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ld_active_q_ld_active
- connect \B \adrok_l_q_addr_acked
+ connect \A \x_ld_i
+ connect \B \x_st_i
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
cell $and $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \st_active_q_st_active
- connect \B \ldst_port0_st_data_i_ok
+ connect \A $15
+ connect \B \x_valid_i
connect \Y $17
end
- process $group_11
- assign \reset_l_s_reset 1'0
- assign \reset_l_s_reset 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- case 1'1
- assign \reset_l_s_reset 1'1
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- case 1'1
- assign \reset_l_s_reset 1'1
- end
- sync init
- end
- process $group_12
- assign \reset_l_r_reset 1'1
- assign \reset_l_r_reset 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- case 1'1
- assign \reset_l_r_reset 1'1
- end
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:308"
- wire width 64 \lddata
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- cell $and $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ld_active_q_ld_active
- connect \B \adrok_l_q_addr_acked
+ connect \A \x_stall_i
connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:312"
- wire width 176 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:311"
- wire width 176 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:311"
- cell $and $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $22
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 176
- parameter \Y_WIDTH 176
- connect \A \mem_mem_r_data
- connect \B \lenexp_rexp_o
- connect \Y $22
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $17
+ connect \B $19
+ connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:312"
- wire width 8 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:312"
- cell $mul $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $24
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 8
- connect \A \lenexp_addr_i
- connect \B 4'1000
- connect \Y $24
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbus__ack
+ connect \B \dbus__err
+ connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:312"
- wire width 176 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:312"
- cell $sshr $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $not $26
parameter \A_SIGNED 0
- parameter \A_WIDTH 176
- parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 176
- connect \A $22
- connect \B $24
- connect \Y $26
- end
- connect $21 $26
- process $group_13
- assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- case 1'1
- assign \lddata $21 [63:0]
- end
- sync init
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_valid_i
+ connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- wire width 1 $28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- cell $and $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ld_active_q_ld_active
- connect \B \adrok_l_q_addr_acked
- connect \Y $28
+ connect \A $23
+ connect \B $25
+ connect \Y $27
end
- process $group_14
- assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- switch { $28 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
+ process $group_1
+ assign \dbus__stb$next \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $21 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ switch { $27 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ case 1'1
+ assign \dbus__stb$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__stb$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- assign \ldst_port0_ld_data_o \lddata
+ assign \dbus__stb$next 1'0
end
sync init
+ update \dbus__stb 1'0
+ sync posedge \clk
+ update \dbus__stb \dbus__stb$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- wire width 1 $30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- cell $and $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ld_active_q_ld_active
- connect \B \adrok_l_q_addr_acked
- connect \Y $30
- end
- process $group_15
- assign \ldst_port0_ld_data_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- switch { $30 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:305"
- case 1'1
- assign \ldst_port0_ld_data_o_ok 1'1
- end
- sync init
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $29
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:321"
- wire width 64 \stdata
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- wire width 1 $32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- cell $and $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \st_active_q_st_active
- connect \B \ldst_port0_st_data_i_ok
- connect \Y $32
+ connect \A $29
+ connect \B \x_valid_i
+ connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:322"
- wire width 319 $34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:322"
- wire width 8 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:322"
- cell $mul $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $34
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_stall_i
+ connect \Y $33
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 8
- connect \A \lenexp_addr_i
- connect \B 4'1000
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $31
+ connect \B $33
connect \Y $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:322"
- wire width 319 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:322"
- cell $sshl $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $38
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 319
- connect \A \ldst_port0_st_data_i
- connect \B $35
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbus__ack
+ connect \B \dbus__err
connect \Y $37
end
- connect $34 $37
- process $group_16
- assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- switch { $32 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- case 1'1
- assign \stdata $34 [63:0]
- end
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
wire width 1 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- cell $and $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \st_active_q_st_active
- connect \B \ldst_port0_st_data_i_ok
+ connect \A \m_valid_i
connect \Y $39
end
- process $group_17
- assign \mem_mem_w_data 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- switch { $39 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- case 1'1
- assign \mem_mem_w_data \stdata
- end
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
wire width 1 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- cell $and $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ cell $or $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \st_active_q_st_active
- connect \B \ldst_port0_st_data_i_ok
+ connect \A $37
+ connect \B $39
connect \Y $41
end
- process $group_18
- assign \mem_mem_w_en 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- switch { $41 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:318"
- case 1'1
- assign \mem_mem_w_en \lenexp_lexp_o [7:0]
- end
- sync init
- end
- process $group_19
- assign \reset_delay$next \reset_delay
- assign \reset_delay$next \reset_l_q_reset
- sync init
- update \reset_delay 1'0
- sync posedge \clk
- update \reset_delay \reset_delay$next
- end
- process $group_20
- assign \ld_active_r_ld_active 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- case 1'1
- assign \ld_active_r_ld_active 1'1
+ process $group_2
+ assign \m_ld_data_o$next \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $35 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ switch { $41 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+ case 1'1
+ assign \m_ld_data_o$next \dbus__dat_r
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
end
- sync init
- end
- process $group_21
- assign \st_active_r_st_active 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:336"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- assign \st_active_r_st_active 1'1
+ assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
+ update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \m_ld_data_o \m_ld_data_o$next
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.l0.idx_l"
-module \idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 2 \q_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 3 \s_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 4 \r_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_idx_l
- connect \Y $1
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $43
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $and $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
- connect \Y $3
+ connect \A $43
+ connect \B \x_valid_i
+ connect \Y $45
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $48
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_stall_i
+ connect \Y $47
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_idx_l
- connect \Y $5
+ connect \A $45
+ connect \B $47
+ connect \Y $49
end
- process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_3
+ assign \dbus__adr$next \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $49 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__adr$next \x_addr_i [47:3]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
+ assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \q_int$next 1'0
+ assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
end
sync init
- update \q_int 1'0
+ update \dbus__adr 45'000000000000000000000000000000000000000000000
sync posedge \clk
- update \q_int \q_int$next
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $not $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \r_idx_l
- connect \Y $7
+ update \dbus__adr \dbus__adr$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $and $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $7
- connect \Y $9
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $51
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:71"
- cell $or $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $9
- connect \B \s_idx_l
- connect \Y $11
- end
- process $group_1
- assign \q_idx_l 1'0
- assign \q_idx_l $11
- sync init
+ connect \A $51
+ connect \B \x_valid_i
+ connect \Y $53
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- wire width 1 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_idx_l
- connect \Y $13
- end
- process $group_2
- assign \qn_idx_l 1'0
- assign \qn_idx_l $13
- sync init
+ connect \A \x_stall_i
+ connect \Y $55
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_idx_l
- connect \B \q_int
- connect \Y $15
+ connect \A $53
+ connect \B $55
+ connect \Y $57
end
- process $group_3
- assign \qlq_idx_l 1'0
- assign \qlq_idx_l $15
+ process $group_4
+ assign \dbus__sel$next \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $57 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__sel$next \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
+ assign \dbus__sel$next 8'00000000
+ assign \dbus__sel$next 8'00000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \dbus__sel$next 8'00000000
+ end
sync init
+ update \dbus__sel 8'00000000
+ sync posedge \clk
+ update \dbus__sel \dbus__sel$next
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.l0.reset_l"
-module \reset_l$68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 input 2 \s_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 3 \r_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 output 4 \q_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:65"
- wire width 1 \q_int$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $not $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \r_reset
- connect \Y $1
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $59
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $and $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_int
- connect \B $1
- connect \Y $3
+ connect \A $59
+ connect \B \x_valid_i
+ connect \Y $61
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:67"
- cell $or $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $64
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \x_stall_i
+ connect \Y $63
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $3
- connect \B \s_reset
- connect \Y $5
+ connect \A $61
+ connect \B $63
+ connect \Y $65
end
- process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_5
+ assign \dbus__we$next \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $65 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__we$next \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+ case
+ assign \dbus__we$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \q_int$next 1'0
+ assign \dbus__we$next 1'0
end
sync init
- update \q_int 1'0
+ update \dbus__we 1'0
sync posedge \clk
- update \q_int \q_int$next
- end
- process $group_1
- assign \q_reset 1'0
- assign \q_reset \q_int
- sync init
+ update \dbus__we \dbus__we$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:60"
- wire width 1 \qn_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:72"
- cell $not $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $or $68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_reset
- connect \Y $7
- end
- process $group_2
- assign \qn_reset 1'0
- assign \qn_reset $7
- sync init
+ connect \A \x_ld_i
+ connect \B \x_st_i
+ connect \Y $67
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:61"
- wire width 1 \qlq_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- wire width 1 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:73"
- cell $or $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \q_reset
- connect \B \q_int
- connect \Y $9
- end
- process $group_3
- assign \qlq_reset 1'0
- assign \qlq_reset $9
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.l0.pick"
-module \pick
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:75"
- wire width 1 input 0 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:76"
- wire width 1 output 1 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:77"
- wire width 1 output 2 \n
- process $group_0
- assign \o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:82"
- switch { \i }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:82"
- case 1'1
- assign \o 1'0
- end
- sync init
+ connect \A $67
+ connect \B \x_valid_i
+ connect \Y $69
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:84"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:84"
- cell $eq $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $not $72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \i
- connect \B 1'0
- connect \Y $1
- end
- process $group_1
- assign \n 1'0
- assign \n $1
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0.l0"
-module \l0$67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 input 2 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 input 3 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 input 4 \ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 input 5 \ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 6 \ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 output 7 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
- wire width 1 output 8 \ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 9 \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 10 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 11 \ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 12 \ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 output 13 \ldst_port0_is_ld_i$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:112"
- wire width 1 input 14 \ldst_port0_busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 15 \ldst_port0_is_st_i$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 output 16 \ldst_port0_data_len$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 output 17 \ldst_port0_addr_i$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 18 \ldst_port0_addr_i_ok$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
- wire width 1 input 19 \ldst_port0_addr_ok_o$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 20 \ldst_port0_ld_data_o$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 21 \ldst_port0_ld_data_o_ok$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 22 \ldst_port0_st_data_i_ok$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 23 \ldst_port0_st_data_i$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 input 24 \ldst_port0_addr_exc_o$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \idx_l_q_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \idx_l_s_idx_l
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \idx_l_r_idx_l
- cell \idx_l \idx_l
- connect \rst \rst
- connect \clk \clk
- connect \q_idx_l \idx_l_q_idx_l
- connect \s_idx_l \idx_l_s_idx_l
- connect \r_idx_l \idx_l_r_idx_l
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:57"
- wire width 1 \reset_l_s_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:58"
- wire width 1 \reset_l_r_reset
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:59"
- wire width 1 \reset_l_q_reset
- cell \reset_l$68 \reset_l
- connect \rst \rst
- connect \clk \clk
- connect \s_reset \reset_l_s_reset
- connect \r_reset \reset_l_r_reset
- connect \q_reset \reset_l_q_reset
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:75"
- wire width 1 \pick_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:76"
- wire width 1 \pick_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/lib/coding.py:77"
- wire width 1 \pick_n
- cell \pick \pick
- connect \i \pick_i
- connect \o \pick_o
- connect \n \pick_n
+ connect \A \x_stall_i
+ connect \Y $71
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:221"
- wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:221"
- cell $or $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ wire width 1 $73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ cell $and $74
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_is_ld_i
- connect \B \ldst_port0_is_st_i
- connect \Y $12
- end
- process $group_0
- assign \pick_i 1'0
- assign \pick_i { $12 }
- sync init
+ connect \A $69
+ connect \B $71
+ connect \Y $73
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
- wire width 1 \idx_l$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:38"
- wire width 1 \idx_l$14$next
- process $group_1
- assign \idx_l$14$next \idx_l$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
- case 1'1
- assign \idx_l$14$next \pick_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
+ process $group_6
+ assign \dbus__dat_w$next \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ switch { $73 \dbus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+ case 2'1-
+ assign \dbus__dat_w$next \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
case
+ assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \idx_l$14$next 1'0
+ assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \idx_l$14 1'0
+ update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \idx_l$14 \idx_l$14$next
- end
- process $group_2
- assign { } 0'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:39"
- case 1'1
- assign { } {}
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/latch.py:42"
- case
- assign { } {}
- end
- sync init
+ update \dbus__dat_w \dbus__dat_w$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:237"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:237"
- cell $not $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ wire width 1 $75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ cell $and $76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \pick_n
- connect \Y $15
+ connect \A \dbus__cyc
+ connect \B \dbus__err
+ connect \Y $75
end
- process $group_3
- assign \idx_l_s_idx_l 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:237"
- switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:237"
- case 1'1
- assign \idx_l_s_idx_l 1'1
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ cell $not $78
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_stall_i
+ connect \Y $77
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:247"
- wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:247"
- cell $not $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+ wire width 1 $79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+ cell $not $80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \ldst_port0_busy_o
- connect \Y $17
+ connect \A \dbus__we
+ connect \Y $79
end
- process $group_4
- assign \reset_l_s_reset 1'0
- assign \reset_l_s_reset 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:247"
- switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:247"
- case 1'1
- assign \reset_l_s_reset 1'1
- end
+ process $group_7
+ assign \m_load_err_o$next \m_load_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ switch { $77 $75 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ case 2'-1
+ assign \m_load_err_o$next $79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ case 2'1-
+ assign \m_load_err_o$next 1'0
end
- sync init
- end
- process $group_5
- assign \reset_l_r_reset 1'1
- assign \reset_l_r_reset 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:255"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:255"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- assign \reset_l_r_reset 1'1
+ assign \m_load_err_o$next 1'0
end
sync init
+ update \m_load_err_o 1'0
+ sync posedge \clk
+ update \m_load_err_o \m_load_err_o$next
end
- process $group_6
- assign \ldst_port0_is_ld_i$1 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:164"
- switch { }
- case 0'
- assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i
- end
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ wire width 1 $81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ cell $and $82
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbus__cyc
+ connect \B \dbus__err
+ connect \Y $81
end
- process $group_7
- assign \ldst_port0_is_st_i$2 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:165"
- switch { }
- case 0'
- assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i
- end
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ cell $not $84
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_stall_i
+ connect \Y $83
end
process $group_8
- assign \ldst_port0_data_len$3 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:166"
- switch { }
- case 0'
- assign \ldst_port0_data_len$3 \ldst_port0_data_len
- end
- end
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:113"
- wire width 1 \ldst_port0_go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:113"
- wire width 1 \ldst_port0_go_die_i$19
- process $group_9
- assign \ldst_port0_go_die_i 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:167"
- switch { }
- case 0'
- assign \ldst_port0_go_die_i \ldst_port0_go_die_i$19
- end
- end
- sync init
- end
- process $group_10
- assign \ldst_port0_addr_i$4 12'000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:168"
- switch { }
- case 0'
- assign \ldst_port0_addr_i$4 \ldst_port0_addr_i
- end
+ assign \m_store_err_o$next \m_store_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ switch { $83 $81 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ case 2'-1
+ assign \m_store_err_o$next \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ case 2'1-
+ assign \m_store_err_o$next 1'0
end
- sync init
- end
- process $group_11
- assign \ldst_port0_addr_i_ok$5 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:169"
- switch { }
- case 0'
- assign \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok
- end
+ assign \m_store_err_o$next 1'0
end
sync init
+ update \m_store_err_o 1'0
+ sync posedge \clk
+ update \m_store_err_o \m_store_err_o$next
end
- process $group_12
- assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ldst_port0_st_data_i_ok$9 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:170"
- switch { }
- case 0'
- assign { \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i$10 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
- end
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ wire width 1 $85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ cell $and $86
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \dbus__cyc
+ connect \B \dbus__err
+ connect \Y $85
end
- process $group_14
- assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ldst_port0_ld_data_o_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:171"
- switch { }
- case 0'
- assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o$7 }
- end
- end
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ wire width 1 $87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ cell $not $88
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_stall_i
+ connect \Y $87
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:112"
- wire width 1 \ldst_port0_busy_o$20
- process $group_16
- assign \ldst_port0_busy_o$20 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:172"
- switch { }
- case 0'
- assign \ldst_port0_busy_o$20 \ldst_port0_busy_o
- end
+ process $group_9
+ assign \m_badaddr_o$next \m_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ switch { $87 $85 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+ case 2'-1
+ assign \m_badaddr_o$next \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+ case 2'1-
end
- sync init
- end
- process $group_17
- assign \ldst_port0_addr_ok_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:173"
- switch { }
- case 0'
- assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
- end
+ assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000
end
sync init
+ update \m_badaddr_o 45'000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \m_badaddr_o \m_badaddr_o$next
end
- process $group_18
- assign \ldst_port0_addr_exc_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- switch { \idx_l_q_idx_l }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:245"
- case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:174"
- switch { }
- case 0'
- assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
- end
- end
+ process $group_10
+ assign \x_busy_o 1'0
+ assign \x_busy_o \dbus__cyc
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:251"
- wire width 1 \reset_delay
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:251"
- wire width 1 \reset_delay$next
- process $group_19
- assign \reset_delay$next \reset_delay
- assign \reset_delay$next \reset_l_q_reset
- sync init
- update \reset_delay 1'0
- sync posedge \clk
- update \reset_delay \reset_delay$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+ cell $or $90
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \m_load_err_o
+ connect \B \m_store_err_o
+ connect \Y $89
end
- process $group_20
- assign \idx_l_r_idx_l 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:255"
- switch { \reset_l_q_reset }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/l0_cache.py:255"
+ process $group_11
+ assign \m_busy_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+ switch { $89 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
case 1'1
- assign \idx_l_r_idx_l 1'1
+ assign \m_busy_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
+ case
+ assign \m_busy_o \dbus__cyc
end
sync init
end
- connect \ldst_port0_go_die_i$19 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.l0"
+attribute \nmigen.hierarchy "test_issuer.core.l0"
module \l0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
wire width 1 input 2 \ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
wire width 1 input 3 \ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
wire width 4 input 4 \ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 input 5 \ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 input 5 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 6 \ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
wire width 1 output 7 \ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
wire width 1 output 8 \ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 9 \ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 10 \ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 11 \ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 12 \ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 \pimem_ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:112"
- wire width 1 \pimem_ldst_port0_busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 \pimem_ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 \pimem_ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 \pimem_ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pimem_ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
- wire width 1 \pimem_ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pimem_ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pimem_ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pimem_ldst_port0_st_data_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pimem_ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 \pimem_ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 13 \ldst_port0_is_ld_i$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 14 \ldst_port0_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 15 \ldst_port0_is_st_i$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 16 \ldst_port0_data_len$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 48 output 17 \ldst_port0_addr_i$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 18 \ldst_port0_addr_i_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+ wire width 8 output 19 \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+ wire width 48 output 20 \x_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 21 \ldst_port0_addr_ok_o$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 output 22 \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 23 \ldst_port0_ld_data_o$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 24 \ldst_port0_ld_data_o_ok$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+ wire width 1 output 25 \x_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 26 \ldst_port0_st_data_i_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 27 \ldst_port0_st_data_i$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+ wire width 64 output 28 \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 29 \ldst_port0_addr_exc_o$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+ wire width 1 output 30 \x_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+ wire width 1 output 31 \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+ wire width 1 output 32 \m_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+ wire width 1 output 33 \x_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 output 34 \ldst_port0_go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 input 35 \ldst_port0_go_die_i$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 36 \ldst_port0_busy_o$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 37 \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 1 input 38 \x_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 39 \dbus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 40 \dbus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 41 \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 input 42 \dbus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 45 output 43 \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 8 output 44 \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 45 \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 output 46 \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+ wire width 1 input 47 \m_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+ wire width 1 output 48 \m_load_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+ wire width 1 output 49 \m_store_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+ wire width 45 output 50 \m_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+ wire width 1 output 51 \m_busy_o
cell \pimem \pimem
connect \rst \rst
connect \clk \clk
- connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i
- connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
- connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i
- connect \ldst_port0_data_len \pimem_ldst_port0_data_len
- connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
- connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o
- connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
- connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
- connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
- end
- cell \l0$67 \l0
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$1
+ connect \ldst_port0_busy_o \ldst_port0_busy_o
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i$2
+ connect \ldst_port0_data_len \ldst_port0_data_len$3
+ connect \ldst_port0_addr_i \ldst_port0_addr_i$4
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$5
+ connect \x_mask_i \x_mask_i
+ connect \x_addr_i \x_addr_i
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
+ connect \m_ld_data_o \m_ld_data_o
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$7
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$8
+ connect \x_busy_o \x_busy_o
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$9
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i$10
+ connect \x_st_data_i \x_st_data_i
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
+ connect \x_ld_i \x_ld_i
+ connect \x_st_i \x_st_i
+ connect \m_valid_i \m_valid_i
+ connect \x_valid_i \x_valid_i
+ end
+ cell \l0$81 \l0
connect \rst \rst
connect \clk \clk
connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
connect \ldst_port0_st_data_i \ldst_port0_st_data_i
connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
- connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i
- connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
- connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i
- connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len
- connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok
- connect \ldst_port0_addr_ok_o$6 \pimem_ldst_port0_addr_ok_o
- connect \ldst_port0_ld_data_o$7 \pimem_ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok$8 \pimem_ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i_ok$9 \pimem_ldst_port0_st_data_i_ok
- connect \ldst_port0_st_data_i$10 \pimem_ldst_port0_st_data_i
- connect \ldst_port0_addr_exc_o$11 \pimem_ldst_port0_addr_exc_o
- end
- connect \pimem_ldst_port0_addr_exc_o 1'0
+ connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$1
+ connect \ldst_port0_busy_o \ldst_port0_busy_o
+ connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$2
+ connect \ldst_port0_data_len$3 \ldst_port0_data_len$3
+ connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$4
+ connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$5
+ connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$6
+ connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$7
+ connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$8
+ connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$9
+ connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$10
+ connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$11
+ connect \ldst_port0_go_die_i \ldst_port0_go_die_i
+ connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$12
+ connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$13
+ end
+ cell \lsmem \lsmem
+ connect \rst \rst
+ connect \clk \clk
+ connect \x_mask_i \x_mask_i
+ connect \x_addr_i \x_addr_i
+ connect \m_ld_data_o \m_ld_data_o
+ connect \x_busy_o \x_busy_o
+ connect \x_st_data_i \x_st_data_i
+ connect \x_ld_i \x_ld_i
+ connect \x_st_i \x_st_i
+ connect \m_valid_i \m_valid_i
+ connect \x_valid_i \x_valid_i
+ connect \dbus__cyc \dbus__cyc
+ connect \x_stall_i \x_stall_i
+ connect \dbus__ack \dbus__ack
+ connect \dbus__err \dbus__err
+ connect \dbus__stb \dbus__stb
+ connect \dbus__dat_r \dbus__dat_r
+ connect \dbus__adr \dbus__adr
+ connect \dbus__sel \dbus__sel
+ connect \dbus__we \dbus__we
+ connect \dbus__dat_w \dbus__dat_w
+ connect \m_stall_i \m_stall_i
+ connect \m_load_err_o \m_load_err_o
+ connect \m_store_err_o \m_store_err_o
+ connect \m_badaddr_o \m_badaddr_o
+ connect \m_busy_o \m_busy_o
+ end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_0"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
module \reg_0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src20__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src30__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_1"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_1"
module \reg_1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src21__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src31__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_2"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_2"
module \reg_2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src22__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src32__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_3"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_3"
module \reg_3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src23__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src23__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src33__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src33__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest13__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest13__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest23__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest23__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src13__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src23__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src33__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_4"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_4"
module \reg_4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src24__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src24__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src34__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src34__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest14__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest14__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest24__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest24__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src14__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src24__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src34__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_5"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_5"
module \reg_5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src25__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src25__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src35__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src35__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest15__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest15__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest25__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest25__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src15__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src25__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src35__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_6"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_6"
module \reg_6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src26__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src26__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src36__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src36__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest16__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest16__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest26__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest26__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src16__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src26__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src36__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_7"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_7"
module \reg_7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src27__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src27__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src37__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src37__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest17__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest17__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest27__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest27__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src17__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src27__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src37__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_8"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_8"
module \reg_8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src18__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src18__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src28__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src28__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src38__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src38__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest18__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest18__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest28__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest28__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src18__data_o \dest18__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src18__data_o \dest28__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src18__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src28__data_o \dest18__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src28__data_o \dest28__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src28__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src38__data_o \dest18__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src38__data_o \dest28__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src38__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest18__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest18__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest28__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest28__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_9"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_9"
module \reg_9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src19__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src19__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src29__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src29__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src39__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src39__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest19__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest19__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest29__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest29__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src19__data_o \dest19__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src19__data_o \dest29__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src19__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src29__data_o \dest19__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src29__data_o \dest29__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src29__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src39__data_o \dest19__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src39__data_o \dest29__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src39__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest19__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest19__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest29__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest29__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_10"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_10"
module \reg_10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src110__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src110__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src210__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src210__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src310__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src310__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest110__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest110__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest210__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest210__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src110__data_o \dest110__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src110__data_o \dest210__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src110__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src210__data_o \dest110__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src210__data_o \dest210__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src210__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src310__data_o \dest110__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src310__data_o \dest210__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src310__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest110__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest110__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest210__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest210__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_11"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
module \reg_11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src111__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src111__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src211__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src211__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src311__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src311__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest111__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest111__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest211__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest211__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src111__data_o \dest111__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src111__data_o \dest211__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src111__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src211__data_o \dest111__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src211__data_o \dest211__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src211__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src311__data_o \dest111__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src311__data_o \dest211__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src311__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest111__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest111__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest211__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest211__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_12"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_12"
module \reg_12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src112__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src112__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src212__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src212__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src312__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src312__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest112__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest112__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest212__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest212__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src112__data_o \dest112__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src112__data_o \dest212__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src112__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src212__data_o \dest112__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src212__data_o \dest212__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src212__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src312__data_o \dest112__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src312__data_o \dest212__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src312__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest112__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest112__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest212__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest212__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_13"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_13"
module \reg_13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src113__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src113__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src213__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src213__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src313__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src313__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest113__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest113__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest213__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest213__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src113__data_o \dest113__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src113__data_o \dest213__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src113__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src213__data_o \dest113__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src213__data_o \dest213__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src213__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src313__data_o \dest113__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src313__data_o \dest213__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src313__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest113__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest113__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest213__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest213__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_14"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
module \reg_14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src114__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src114__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src214__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src214__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src314__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src314__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest114__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest114__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest214__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest214__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src114__data_o \dest114__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src114__data_o \dest214__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src114__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src214__data_o \dest114__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src214__data_o \dest214__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src214__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src314__data_o \dest114__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src314__data_o \dest214__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src314__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest114__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest114__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest214__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest214__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_15"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_15"
module \reg_15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src115__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src115__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src215__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src215__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src315__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src315__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest115__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest115__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest215__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest215__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src115__data_o \dest115__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src115__data_o \dest215__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src115__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src215__data_o \dest115__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src215__data_o \dest215__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src215__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src315__data_o \dest115__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src315__data_o \dest215__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src315__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest115__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest115__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest215__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest215__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_16"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_16"
module \reg_16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src116__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src116__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src216__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src216__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src316__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src316__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest116__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest116__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest216__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest216__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src116__data_o \dest116__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src116__data_o \dest216__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src116__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src216__data_o \dest116__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src216__data_o \dest216__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src216__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src316__data_o \dest116__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src316__data_o \dest216__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src316__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest116__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest116__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest216__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest216__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_17"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
module \reg_17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src117__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src117__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src217__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src217__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src317__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src317__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest117__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest117__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest217__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest217__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src117__data_o \dest117__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src117__data_o \dest217__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src117__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src217__data_o \dest117__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src217__data_o \dest217__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src217__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src317__data_o \dest117__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src317__data_o \dest217__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src317__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest117__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest117__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest217__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest217__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_18"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_18"
module \reg_18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src118__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src118__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src218__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src218__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src318__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src318__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest118__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest118__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest218__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest218__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src118__data_o \dest118__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src118__data_o \dest218__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src118__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src218__data_o \dest118__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src218__data_o \dest218__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src218__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src318__data_o \dest118__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src318__data_o \dest218__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src318__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest118__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest118__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest218__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest218__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_19"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_19"
module \reg_19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src119__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src119__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src219__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src219__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src319__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src319__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest119__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest119__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest219__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest219__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src119__data_o \dest119__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src119__data_o \dest219__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src119__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src219__data_o \dest119__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src219__data_o \dest219__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src219__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src319__data_o \dest119__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src319__data_o \dest219__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src319__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest119__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest119__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest219__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest219__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_20"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
module \reg_20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src120__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src120__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src220__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src220__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src320__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src320__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest120__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest120__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest220__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest220__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src120__data_o \dest120__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src120__data_o \dest220__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src120__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src220__data_o \dest120__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src220__data_o \dest220__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src220__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src320__data_o \dest120__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src320__data_o \dest220__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src320__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest120__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest120__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest220__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest220__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_21"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_21"
module \reg_21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src121__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src121__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src221__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src221__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src321__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src321__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest121__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest121__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest221__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest221__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src121__data_o \dest121__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src121__data_o \dest221__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src121__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src221__data_o \dest121__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src221__data_o \dest221__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src221__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src321__data_o \dest121__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src321__data_o \dest221__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src321__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest121__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest121__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest221__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest221__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_22"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_22"
module \reg_22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src122__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src122__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src222__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src222__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src322__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src322__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest122__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest122__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest222__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest222__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src122__data_o \dest122__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src122__data_o \dest222__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src122__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src222__data_o \dest122__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src222__data_o \dest222__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src222__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src322__data_o \dest122__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src322__data_o \dest222__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src322__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest122__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest122__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest222__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest222__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_23"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
module \reg_23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src123__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src123__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src223__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src223__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src323__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src323__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest123__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest123__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest223__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest223__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src123__data_o \dest123__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src123__data_o \dest223__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src123__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src223__data_o \dest123__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src223__data_o \dest223__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src223__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src323__data_o \dest123__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src323__data_o \dest223__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src323__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest123__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest123__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest223__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest223__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_24"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_24"
module \reg_24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src124__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src124__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src224__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src224__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src324__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src324__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest124__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest124__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest224__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest224__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src124__data_o \dest124__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src124__data_o \dest224__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src124__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src224__data_o \dest124__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src224__data_o \dest224__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src224__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src324__data_o \dest124__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src324__data_o \dest224__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src324__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest124__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest124__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest224__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest224__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_25"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_25"
module \reg_25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src125__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src125__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src225__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src225__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src325__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src325__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest125__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest125__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest225__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest225__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src125__data_o \dest125__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src125__data_o \dest225__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src125__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src225__data_o \dest125__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src225__data_o \dest225__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src225__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src325__data_o \dest125__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src325__data_o \dest225__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src325__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest125__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest125__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest225__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest225__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_26"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
module \reg_26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src126__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src126__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src226__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src226__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src326__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src326__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest126__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest126__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest226__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest226__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src126__data_o \dest126__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src126__data_o \dest226__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src126__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src226__data_o \dest126__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src226__data_o \dest226__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src226__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src326__data_o \dest126__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src326__data_o \dest226__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src326__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest126__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest126__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest226__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest226__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_27"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_27"
module \reg_27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src127__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src127__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src227__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src227__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src327__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src327__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest127__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest127__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest227__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest227__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src127__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src127__data_o \dest127__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src127__data_o \dest227__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src127__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src127__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src227__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src227__data_o \dest127__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src227__data_o \dest227__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src227__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src227__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src327__data_o \dest127__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src327__data_o \dest227__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src327__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src327__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest127__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest127__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest227__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest227__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_28"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_28"
module \reg_28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src128__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src128__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src228__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src228__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src328__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src328__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest128__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest128__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest228__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest228__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src128__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src128__data_o \dest128__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src128__data_o \dest228__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src128__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src128__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src228__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src228__data_o \dest128__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src228__data_o \dest228__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src228__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src228__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src328__data_o \dest128__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src328__data_o \dest228__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src328__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src328__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest128__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest128__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest228__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest228__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_29"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_29"
module \reg_29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src129__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src129__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src229__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src229__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src329__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src329__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest129__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest129__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest229__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest229__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src129__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src129__data_o \dest129__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src129__data_o \dest229__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src129__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src129__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src229__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src229__data_o \dest129__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src229__data_o \dest229__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src229__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src229__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src329__data_o \dest129__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src329__data_o \dest229__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src329__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src329__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest129__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest129__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest229__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest229__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_30"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_30"
module \reg_30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src130__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src130__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src230__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src230__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src330__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src330__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest130__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest130__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest230__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest230__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src130__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src130__data_o \dest130__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src130__data_o \dest230__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src130__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src130__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src230__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src230__data_o \dest130__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src230__data_o \dest230__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src230__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src230__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src330__data_o \dest130__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src330__data_o \dest230__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src330__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src330__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest130__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest130__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest230__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest230__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int.reg_31"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_31"
module \reg_31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src131__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src131__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src231__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src231__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src331__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src331__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest131__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \dest131__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest231__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \dest231__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src131__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src131__data_o \dest131__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src131__data_o \dest231__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src131__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src131__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src231__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src231__data_o \dest131__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src231__data_o \dest231__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src231__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src231__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src331__data_o \dest131__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src331__data_o \dest231__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src331__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src331__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_6
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest131__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest131__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest231__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest231__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.int"
+attribute \nmigen.hierarchy "test_issuer.core.int"
module \int
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 2 \src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 4 \src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 6 \src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 8 \wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 9 \data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 10 \wen$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 11 \data_i$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
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wire width 64 \reg_0_src10__data_o
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assign { \reg_31_src131__ren \reg_30_src130__ren \reg_29_src129__ren \reg_28_src128__ren \reg_27_src127__ren \reg_26_src126__ren \reg_25_src125__ren \reg_24_src124__ren \reg_23_src123__ren \reg_22_src122__ren \reg_21_src121__ren \reg_20_src120__ren \reg_19_src119__ren \reg_18_src118__ren \reg_17_src117__ren \reg_16_src116__ren \reg_15_src115__ren \reg_14_src114__ren \reg_13_src113__ren \reg_12_src112__ren \reg_11_src111__ren \reg_10_src110__ren \reg_9_src19__ren \reg_8_src18__ren \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
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end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $54
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
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connect \Y $55
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $55
connect \Y $57
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $57
connect \Y $59
end
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $64
parameter \A_SIGNED 0
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assign { \reg_31_src231__ren \reg_30_src230__ren \reg_29_src229__ren \reg_28_src228__ren \reg_27_src227__ren \reg_26_src226__ren \reg_25_src225__ren \reg_24_src224__ren \reg_23_src223__ren \reg_22_src222__ren \reg_21_src221__ren \reg_20_src220__ren \reg_19_src219__ren \reg_18_src218__ren \reg_17_src217__ren \reg_16_src216__ren \reg_15_src215__ren \reg_14_src214__ren \reg_13_src213__ren \reg_12_src212__ren \reg_11_src211__ren \reg_10_src210__ren \reg_9_src29__ren \reg_8_src28__ren \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $66
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_1_src21__data_o
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end
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wire width 64 $67
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
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end
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wire width 64 $69
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $67
connect \Y $69
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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parameter \A_SIGNED 0
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connect \B \reg_5_src25__data_o
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wire width 64 $73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $74
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_7_src27__data_o
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assign { \reg_31_src331__ren \reg_30_src330__ren \reg_29_src329__ren \reg_28_src328__ren \reg_27_src327__ren \reg_26_src326__ren \reg_25_src325__ren \reg_24_src324__ren \reg_23_src323__ren \reg_22_src322__ren \reg_21_src321__ren \reg_20_src320__ren \reg_19_src319__ren \reg_18_src318__ren \reg_17_src317__ren \reg_16_src316__ren \reg_15_src315__ren \reg_14_src314__ren \reg_13_src313__ren \reg_12_src312__ren \reg_11_src311__ren \reg_10_src310__ren \reg_9_src39__ren \reg_8_src38__ren \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
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cell $or $152
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connect \Y $151
end
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cell $or $154
parameter \A_SIGNED 0
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connect \B $151
connect \Y $153
end
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cell $or $156
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connect \Y $155
end
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cell $or $158
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connect \Y $157
end
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cell $or $160
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connect \Y $159
end
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cell $or $162
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connect \B $159
connect \Y $161
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $164
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connect \Y $163
end
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wire width 64 $165
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $166
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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connect \Y $165
end
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wire width 64 $167
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $168
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $165
connect \Y $167
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
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wire width 64 $169
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $170
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $167
connect \Y $169
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
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wire width 64 $171
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $172
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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connect \Y $171
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
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wire width 64 $173
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $174
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parameter \A_WIDTH 64
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connect \Y $173
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
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wire width 64 $175
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $176
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $173
connect \Y $175
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
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wire width 64 $177
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $178
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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connect \Y $177
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
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wire width 64 $179
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $180
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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connect \Y $179
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
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wire width 64 $181
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $182
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $179
connect \Y $181
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
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wire width 64 $183
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $184
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $181
connect \Y $183
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 64 $185
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $186
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $183
connect \Y $185
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 64 $187
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $188
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_0"
-module \reg_0$69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
+module \reg_0$83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r0__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r0__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w0__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src10__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src10__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src20__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src20__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src20__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src30__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src30__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src30__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r0__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r0__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r0__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_1"
-module \reg_1$70
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
+module \reg_1$84
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w1__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src11__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src11__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src21__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src21__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src21__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src31__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src31__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src31__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r1__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r1__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r1__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_2"
-module \reg_2$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
+module \reg_2$85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w2__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src12__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src12__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src22__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src22__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src22__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src32__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src32__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src32__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r2__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r2__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r2__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_3"
-module \reg_3$72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
+module \reg_3$86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src23__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src23__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src33__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src33__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest13__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest13__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest23__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest23__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w3__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w3__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src13__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \w3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src13__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src13__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src23__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \w3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src23__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src23__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src33__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \w3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src33__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src33__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r3__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r3__data_o \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r3__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r3__data_o \w3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r3__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r3__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_4"
-module \reg_4$73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
+module \reg_4$87
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src24__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src24__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src34__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src34__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest14__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest14__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest24__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest24__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r4__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r4__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w4__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w4__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src14__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \w4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src14__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src14__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src24__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \w4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src24__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src24__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src34__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \w4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src34__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src34__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r4__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r4__data_o \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r4__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r4__data_o \w4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r4__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r4__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_5"
-module \reg_5$74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
+module \reg_5$88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src25__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src25__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src35__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src35__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest15__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest15__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest25__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest25__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r5__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r5__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w5__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w5__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src15__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \w5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src15__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src15__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src25__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \w5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src25__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src25__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src35__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \w5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src35__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src35__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r5__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r5__data_o \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r5__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r5__data_o \w5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r5__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r5__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_6"
-module \reg_6$75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
+module \reg_6$89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src26__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src26__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src36__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src36__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest16__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest16__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest26__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest26__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r6__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r6__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w6__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w6__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src16__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \w6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src16__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src16__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src26__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \w6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src26__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src26__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src36__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \w6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src36__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src36__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r6__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r6__data_o \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r6__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r6__data_o \w6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r6__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r6__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr.reg_7"
-module \reg_7$76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7"
+module \reg_7$90
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 3 \src17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src27__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src27__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src37__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src37__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest17__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 9 \dest17__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest27__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 11 \dest27__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 12 \r7__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 13 \r7__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 14 \w7__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \w7__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 4 \reg$next
process $group_1
assign \src17__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \w7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src17__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src17__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src27__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \w7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src27__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src27__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src37__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \w7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src37__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src37__data_o 4'0000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r7__data_o 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r7__data_o \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r7__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r7__data_o \w7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r7__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r7__data_o 4'0000
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 4'0000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.cr"
+attribute \nmigen.hierarchy "test_issuer.core.cr"
module \cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 2 \full_rd__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 output 3 \full_rd__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 4 \src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 5 \src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 6 \src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 7 \src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 8 \src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 output 9 \src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 10 \full_wr__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 input 11 \full_wr__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 12 \wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 input 13 \data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_dest10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_r0__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_r0__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_0_w0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$69 \reg_0
+ cell \reg_0$83 \reg_0
connect \rst \rst
connect \clk \clk
connect \src10__ren \reg_0_src10__ren
connect \w0__data_i \reg_0_w0__data_i
connect \w0__wen \reg_0_w0__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_dest11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_r1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_r1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_1_w1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$70 \reg_1
+ cell \reg_1$84 \reg_1
connect \rst \rst
connect \clk \clk
connect \src11__ren \reg_1_src11__ren
connect \w1__data_i \reg_1_w1__data_i
connect \w1__wen \reg_1_w1__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_dest12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_r2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_r2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_2_w2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$71 \reg_2
+ cell \reg_2$85 \reg_2
connect \rst \rst
connect \clk \clk
connect \src12__ren \reg_2_src12__ren
connect \w2__data_i \reg_2_w2__data_i
connect \w2__wen \reg_2_w2__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_src13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src23__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_src23__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src33__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_src33__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_dest13__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_dest13__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_dest23__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_dest23__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_r3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_r3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_3_w3__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_w3__wen
- cell \reg_3$72 \reg_3
+ cell \reg_3$86 \reg_3
connect \rst \rst
connect \clk \clk
connect \src13__ren \reg_3_src13__ren
connect \w3__data_i \reg_3_w3__data_i
connect \w3__wen \reg_3_w3__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_src14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src24__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_src24__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src34__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_src34__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_dest14__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_dest14__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_dest24__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_dest24__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_r4__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_r4__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_4_w4__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_w4__wen
- cell \reg_4$73 \reg_4
+ cell \reg_4$87 \reg_4
connect \rst \rst
connect \clk \clk
connect \src14__ren \reg_4_src14__ren
connect \w4__data_i \reg_4_w4__data_i
connect \w4__wen \reg_4_w4__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_src15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src25__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_src25__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src35__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_src35__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_dest15__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_dest15__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_dest25__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_dest25__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_r5__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_r5__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_5_w5__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_w5__wen
- cell \reg_5$74 \reg_5
+ cell \reg_5$88 \reg_5
connect \rst \rst
connect \clk \clk
connect \src15__ren \reg_5_src15__ren
connect \w5__data_i \reg_5_w5__data_i
connect \w5__wen \reg_5_w5__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_src16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src26__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_src26__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src36__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_src36__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_dest16__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_dest16__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_dest26__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_dest26__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_r6__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_r6__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_6_w6__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_w6__wen
- cell \reg_6$75 \reg_6
+ cell \reg_6$89 \reg_6
connect \rst \rst
connect \clk \clk
connect \src16__ren \reg_6_src16__ren
connect \w6__data_i \reg_6_w6__data_i
connect \w6__wen \reg_6_w6__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_src17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src27__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_src27__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src37__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_src37__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_dest17__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_dest17__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_dest27__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_dest27__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_r7__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_r7__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \reg_7_w7__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_w7__wen
- cell \reg_7$76 \reg_7
+ cell \reg_7$90 \reg_7
connect \rst \rst
connect \clk \clk
connect \src17__ren \reg_7_src17__ren
assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src11__data_o
connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $4
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src13__data_o
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $3
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src15__data_o
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src17__data_o
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $9
connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src21__data_o
connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $18
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src23__data_o
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $20
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $17
connect \Y $19
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src25__data_o
connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $24
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src27__data_o
connect \Y $23
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $26
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $23
connect \Y $25
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $28
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $30
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src31__data_o
connect \Y $29
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $32
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src33__data_o
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $34
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $31
connect \Y $33
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src35__data_o
connect \Y $35
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 4 $37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src37__data_o
connect \Y $37
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $40
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $37
connect \Y $39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 4 $41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $42
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \reg_7_dest17__data_i \data_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \wen$43
process $group_43
assign \reg_0_dest20__wen 1'0
assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$43
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \data_i$44
process $group_51
assign \reg_0_dest20__data_i 4'0000
connect \data_i$44 4'0000
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.xer.reg_0"
-module \reg_0$77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0"
+module \reg_0$91
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 3 \src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 5 \src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 7 \src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 9 \dest10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 11 \dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \dest30__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 13 \dest30__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 14 \r0__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \r0__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 16 \w0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w0__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg$next
process $group_1
assign \src10__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src10__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src20__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src20__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src20__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src30__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src30__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src30__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r0__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r0__data_o \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r0__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r0__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 2'00
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.xer.reg_1"
-module \reg_1$78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1"
+module \reg_1$92
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 3 \src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 5 \src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 7 \src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 9 \dest11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 11 \dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \dest31__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 13 \dest31__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 14 \r1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \r1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 16 \w1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w1__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg$next
process $group_1
assign \src11__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src11__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src21__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src21__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src21__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src31__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src31__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src31__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r1__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r1__data_o \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r1__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r1__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 2'00
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.xer.reg_2"
-module \reg_2$79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2"
+module \reg_2$93
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 3 \src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 5 \src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 7 \src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \dest12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 9 \dest12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 11 \dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \dest32__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 13 \dest32__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 14 \r2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 15 \r2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 16 \w2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 17 \w2__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 2 \reg$next
process $group_1
assign \src12__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src12__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src22__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src22__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src22__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src32__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src32__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src32__data_o 2'00
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \r2__data_o 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \r2__data_o \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \r2__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \r2__data_o 2'00
end
end
process $group_8
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \w2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \w2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 2'00
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.xer"
+attribute \nmigen.hierarchy "test_issuer.core.xer"
module \xer
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 input 2 \src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 3 \src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 input 4 \src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 output 5 \src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 input 6 \wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 7 \data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 input 8 \wen$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 9 \data_i$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 input 10 \wen$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 input 11 \data_i$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_dest10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest30__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_dest30__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_r0__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_r0__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_0_w0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$77 \reg_0
+ cell \reg_0$91 \reg_0
connect \rst \rst
connect \clk \clk
connect \src10__ren \reg_0_src10__ren
connect \w0__data_i \reg_0_w0__data_i
connect \w0__wen \reg_0_w0__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_dest11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest31__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_dest31__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_r1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_r1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_1_w1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$78 \reg_1
+ cell \reg_1$92 \reg_1
connect \rst \rst
connect \clk \clk
connect \src11__ren \reg_1_src11__ren
connect \w1__data_i \reg_1_w1__data_i
connect \w1__wen \reg_1_w1__wen
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_dest12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest32__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_dest32__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_r2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_r2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \reg_2_w2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$79 \reg_2
+ cell \reg_2$93 \reg_2
connect \rst \rst
connect \clk \clk
connect \src12__ren \reg_2_src12__ren
assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 2 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src12__data_o
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 2 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 2 $9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src22__data_o
connect \Y $9
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 2 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \src2__data_o $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \src3__ren
process $group_8
assign \reg_0_src30__ren 1'0
assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 2 $13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src32__data_o
connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 2 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \reg_2_dest32__data_i \data_i$2
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 6 \full_rd__data_o
process $group_30
assign \full_rd__data_o 6'000000
assign \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \full_rd__ren
process $group_31
assign \reg_0_r0__ren 1'0
assign { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 6 \full_wr__data_i
process $group_34
assign \reg_0_w0__data_i 2'00
assign { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \full_wr__wen
process $group_37
assign \reg_0_w0__wen 1'0
connect \full_wr__wen 3'000
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_0"
-module \reg_0$80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0"
+module \reg_0$94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src40__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src40__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia0__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest30__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest30__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest40__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest40__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr10__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src10__data_o \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src10__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src20__data_o \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src20__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src30__data_o \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src30__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src40__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src40__data_o \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src40__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src40__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src40__data_o \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src40__data_o \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src40__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src40__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd10__data_o \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd10__data_o \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd10__data_o \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd10__data_o \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd10__data_o \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd10__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia0__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia0__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest20__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest20__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest30__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest30__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest40__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest40__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr10__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_1"
-module \reg_1$81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
+module \reg_1$95
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src41__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src41__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia1__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest31__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest31__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest41__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest41__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr11__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src11__data_o \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src11__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src21__data_o \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src21__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src31__data_o \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src31__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src41__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src41__data_o \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src41__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src41__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src41__data_o \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src41__data_o \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src41__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src41__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd11__data_o \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd11__data_o \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd11__data_o \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd11__data_o \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd11__data_o \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd11__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia1__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia1__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest21__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest21__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest31__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest31__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest41__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest41__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr11__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_2"
-module \reg_2$82
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
+module \reg_2$96
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src42__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src42__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia2__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest32__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest32__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest42__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest42__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr12__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src12__data_o \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src12__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src22__data_o \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src22__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src32__data_o \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src32__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src42__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src42__data_o \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src42__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src42__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src42__data_o \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src42__data_o \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src42__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src42__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd12__data_o \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd12__data_o \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd12__data_o \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd12__data_o \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd12__data_o \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd12__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia2__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia2__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest22__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest22__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest32__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest32__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest42__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest42__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr12__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_3"
-module \reg_3$83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
+module \reg_3$97
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src23__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src23__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src33__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src33__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src43__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src43__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia3__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia3__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest23__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest23__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest33__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest33__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest43__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest43__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr13__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr13__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src13__data_o \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src13__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src23__data_o \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src23__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src33__data_o \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src33__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src43__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src43__data_o \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src43__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src43__data_o \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src43__data_o \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src43__data_o \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src43__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src43__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd13__data_o \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd13__data_o \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd13__data_o \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd13__data_o \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd13__data_o \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd13__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia3__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia3__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest23__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest23__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest33__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest33__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest43__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest43__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr13__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_4"
-module \reg_4$84
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
+module \reg_4$98
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src24__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src24__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src34__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src34__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src44__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src44__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia4__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia4__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest24__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest24__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest34__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest34__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest44__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest44__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr14__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr14__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src14__data_o \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src14__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src24__data_o \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src24__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src34__data_o \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src34__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src44__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src44__data_o \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src44__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src44__data_o \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src44__data_o \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src44__data_o \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src44__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src44__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd14__data_o \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd14__data_o \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd14__data_o \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd14__data_o \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd14__data_o \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd14__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia4__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia4__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest24__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest24__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest34__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest34__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest44__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest44__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr14__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_5"
-module \reg_5$85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5"
+module \reg_5$99
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src25__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src25__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src35__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src35__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src45__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src45__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia5__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia5__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest25__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest25__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest35__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest35__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest45__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest45__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr15__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr15__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src15__data_o \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src15__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src25__data_o \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src25__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src35__data_o \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src35__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src45__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src45__data_o \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src45__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src45__data_o \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src45__data_o \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src45__data_o \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src45__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src45__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd15__data_o \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd15__data_o \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd15__data_o \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd15__data_o \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd15__data_o \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd15__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia5__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia5__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest25__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest25__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest35__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest35__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest45__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest45__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr15__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_6"
-module \reg_6$86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6"
+module \reg_6$100
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src26__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src26__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src36__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src36__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src46__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src46__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia6__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia6__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest26__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest26__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest36__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest36__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest46__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest46__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr16__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr16__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src16__data_o \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src16__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src26__data_o \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src26__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src36__data_o \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src36__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src46__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src46__data_o \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src46__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src46__data_o \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src46__data_o \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src46__data_o \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src46__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src46__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd16__data_o \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd16__data_o \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd16__data_o \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd16__data_o \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd16__data_o \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd16__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia6__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia6__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest26__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest26__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest36__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest36__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest46__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest46__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr16__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast.reg_7"
-module \reg_7$87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7"
+module \reg_7$101
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 2 \src17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 3 \src17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 4 \src27__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \src27__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 6 \src37__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 7 \src37__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 8 \src47__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 9 \src47__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 10 \d_rd17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 11 \d_rd17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 12 \nia7__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \nia7__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 14 \dest27__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 15 \dest27__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 16 \dest37__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 17 \dest37__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 18 \dest47__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 19 \dest47__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 input 20 \d_wr17__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 21 \d_wr17__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $3
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:55"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src17__data_o \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src17__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $9
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_2
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $8 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$7 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$7 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src27__data_o \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src27__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $15 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$14 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$14 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src37__data_o \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src37__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_6
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $22 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$21 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $24
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_7
assign \src47__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src47__data_o \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src47__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src47__data_o \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src47__data_o \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \src47__data_o \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \src47__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \src47__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:61"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_8
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $29 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
assign \wr_detect$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \wr_detect$28 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
wire width 1 $31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B 1'1
connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
wire width 1 $33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_9
assign \d_rd17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $31 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd17__data_o \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd17__data_o \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd17__data_o \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd17__data_o \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
assign \d_rd17__data_o \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $33 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:67"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
assign \d_rd17__data_o \reg
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:71"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
assign \d_rd17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
process $group_10
assign \reg$next \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia7__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \nia7__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest27__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest27__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest37__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest37__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \dest47__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \dest47__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \d_wr17__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
case 1'1
assign \reg$next \d_wr17__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.fast"
+attribute \nmigen.hierarchy "test_issuer.core.fast"
module \fast
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 0 \d_rd1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 1 \d_rd1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 2 \fast_nia_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 3 \wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 4 \data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 5 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 6 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 7 \src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 8 \src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 9 \src4__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 10 \src4__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 11 \src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 12 \src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 13 \wen$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 14 \data_i$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 15 \wen$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 16 \data_i$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \data_i$5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 13 \src2__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 output 14 \src2__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 15 \wen$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 16 \data_i$2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 17 \wen$3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 18 \data_i$4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 19 \data_i$5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 20 \wen$6
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 21 \data_i$7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_src10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src20__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_src20__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src30__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_src30__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src40__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_src40__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_d_rd10__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_d_rd10__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_nia0__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_nia0__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest20__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_dest20__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest30__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_dest30__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_dest40__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_dest40__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_d_wr10__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_d_wr10__data_i
- cell \reg_0$80 \reg_0
+ cell \reg_0$94 \reg_0
connect \rst \rst
connect \clk \clk
connect \src10__ren \reg_0_src10__ren
connect \d_wr10__wen \reg_0_d_wr10__wen
connect \d_wr10__data_i \reg_0_d_wr10__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_src11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src21__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_src21__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src31__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_src31__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_src41__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_src41__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_d_rd11__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_d_rd11__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_nia1__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_nia1__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest21__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_dest21__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest31__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_dest31__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_dest41__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_dest41__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_d_wr11__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_d_wr11__data_i
- cell \reg_1$81 \reg_1
+ cell \reg_1$95 \reg_1
connect \rst \rst
connect \clk \clk
connect \src11__ren \reg_1_src11__ren
connect \d_wr11__wen \reg_1_d_wr11__wen
connect \d_wr11__data_i \reg_1_d_wr11__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_src12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src22__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_src22__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src32__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_src32__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_src42__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_src42__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_d_rd12__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_d_rd12__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_nia2__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_nia2__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest22__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_dest22__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest32__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_dest32__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_dest42__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_dest42__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_d_wr12__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_d_wr12__data_i
- cell \reg_2$82 \reg_2
+ cell \reg_2$96 \reg_2
connect \rst \rst
connect \clk \clk
connect \src12__ren \reg_2_src12__ren
connect \d_wr12__wen \reg_2_d_wr12__wen
connect \d_wr12__data_i \reg_2_d_wr12__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_src13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src23__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_src23__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src33__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_src33__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_src43__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_src43__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_d_rd13__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_d_rd13__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_nia3__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_nia3__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_dest23__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_dest23__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_dest33__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_dest33__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_dest43__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_dest43__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_d_wr13__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_d_wr13__data_i
- cell \reg_3$83 \reg_3
+ cell \reg_3$97 \reg_3
connect \rst \rst
connect \clk \clk
connect \src13__ren \reg_3_src13__ren
connect \d_wr13__wen \reg_3_d_wr13__wen
connect \d_wr13__data_i \reg_3_d_wr13__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_src14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src24__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_src24__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src34__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_src34__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_src44__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_src44__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_d_rd14__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_d_rd14__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_nia4__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_nia4__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_dest24__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_dest24__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_dest34__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_dest34__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_dest44__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_dest44__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_d_wr14__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_d_wr14__data_i
- cell \reg_4$84 \reg_4
+ cell \reg_4$98 \reg_4
connect \rst \rst
connect \clk \clk
connect \src14__ren \reg_4_src14__ren
connect \d_wr14__wen \reg_4_d_wr14__wen
connect \d_wr14__data_i \reg_4_d_wr14__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_src15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src25__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_src25__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src35__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_src35__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_src45__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_src45__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_d_rd15__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_d_rd15__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_nia5__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_nia5__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_dest25__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_dest25__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_dest35__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_dest35__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_dest45__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_dest45__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_d_wr15__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_d_wr15__data_i
- cell \reg_5$85 \reg_5
+ cell \reg_5$99 \reg_5
connect \rst \rst
connect \clk \clk
connect \src15__ren \reg_5_src15__ren
connect \d_wr15__wen \reg_5_d_wr15__wen
connect \d_wr15__data_i \reg_5_d_wr15__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_src16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src26__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_src26__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src36__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_src36__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_src46__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_src46__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_d_rd16__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_d_rd16__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_nia6__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_nia6__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_dest26__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_dest26__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_dest36__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_dest36__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_dest46__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_dest46__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_d_wr16__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_d_wr16__data_i
- cell \reg_6$86 \reg_6
+ cell \reg_6$100 \reg_6
connect \rst \rst
connect \clk \clk
connect \src16__ren \reg_6_src16__ren
connect \d_wr16__wen \reg_6_d_wr16__wen
connect \d_wr16__data_i \reg_6_d_wr16__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_src17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src27__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_src27__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src37__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_src37__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_src47__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_src47__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_d_rd17__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_d_rd17__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_nia7__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_nia7__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_dest27__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_dest27__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_dest37__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_dest37__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_dest47__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_dest47__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_d_wr17__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_d_wr17__data_i
- cell \reg_7$87 \reg_7
+ cell \reg_7$101 \reg_7
connect \rst \rst
connect \clk \clk
connect \src17__ren \reg_7_src17__ren
assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 64 $6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $7
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_0_src10__data_o
- connect \B \reg_1_src11__data_o
- connect \Y $6
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 64 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $9
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_2_src12__data_o
- connect \B \reg_3_src13__data_o
+ connect \A \reg_0_src10__data_o
+ connect \B \reg_1_src11__data_o
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 64 $10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $11
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $6
- connect \B $8
+ connect \A \reg_2_src12__data_o
+ connect \B \reg_3_src13__data_o
connect \Y $10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 64 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $13
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_4_src14__data_o
- connect \B \reg_5_src15__data_o
+ connect \A $8
+ connect \B $10
connect \Y $12
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 64 $14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $15
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_6_src16__data_o
- connect \B \reg_7_src17__data_o
+ connect \A \reg_4_src14__data_o
+ connect \B \reg_5_src15__data_o
connect \Y $14
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
wire width 64 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $17
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $12
- connect \B $14
+ connect \A \reg_6_src16__data_o
+ connect \B \reg_7_src17__data_o
connect \Y $16
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
wire width 64 $18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $19
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $10
+ connect \A $14
connect \B $16
connect \Y $18
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 64 $20
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $12
+ connect \B $18
+ connect \Y $20
+ end
process $group_8
assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1__data_o $18
+ assign \src1__data_o $20
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \src2__ren
process $group_9
assign \reg_0_src20__ren 1'0
assign \reg_1_src21__ren 1'0
assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 64 $20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $21
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
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parameter \A_SIGNED 0
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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cell $or $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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cell $or $27
parameter \A_SIGNED 0
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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wire width 64 $28
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $29
parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \Y $30
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wire width 64 $32
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $33
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \B $30
connect \Y $32
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $35
+ parameter \A_SIGNED 0
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+ connect \A $26
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process $group_17
assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
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sync init
end
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assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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parameter \A_SIGNED 0
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $43
parameter \A_SIGNED 0
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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wire width 64 $44
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \Y $44
end
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wire width 64 $46
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
cell $or $47
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \B $44
connect \Y $46
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $49
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process $group_26
assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
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sync init
end
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assign { \reg_7_src47__ren \reg_6_src46__ren \reg_5_src45__ren \reg_4_src44__ren \reg_3_src43__ren \reg_2_src42__ren \reg_1_src41__ren \reg_0_src40__ren } \src4__ren
sync init
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $51
parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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end
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wire width 64 $52
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cell $or $53
parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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cell $or $55
parameter \A_SIGNED 0
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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end
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wire width 64 $56
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $57
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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end
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wire width 64 $58
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parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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wire width 64 $60
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cell $or $61
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \B $58
connect \Y $60
end
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
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process $group_35
assign \src4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
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sync init
end
process $group_36
assign { \reg_7_d_rd17__ren \reg_6_d_rd16__ren \reg_5_d_rd15__ren \reg_4_d_rd14__ren \reg_3_d_rd13__ren \reg_2_d_rd12__ren \reg_1_d_rd11__ren \reg_0_d_rd10__ren } \d_rd1__ren
sync init
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+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
cell $or $65
parameter \A_SIGNED 0
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parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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end
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wire width 64 $66
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cell $or $67
parameter \A_SIGNED 0
parameter \A_WIDTH 64
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parameter \B_WIDTH 64
parameter \Y_WIDTH 64
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connect \Y $66
end
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wire width 64 $68
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parameter \Y_WIDTH 64
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wire width 64 $70
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parameter \Y_WIDTH 64
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parameter \Y_WIDTH 64
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parameter \A_SIGNED 0
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parameter \Y_WIDTH 64
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connect \Y $74
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 64 $76
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $77
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $68
+ connect \B $74
+ connect \Y $76
+ end
process $group_44
assign \d_rd1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \d_rd1__data_o $74
+ assign \d_rd1__data_o $76
sync init
end
process $group_45
assign \reg_7_nia7__data_i \data_i$5
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \wen$76
process $group_61
assign \reg_0_dest20__wen 1'0
assign \reg_1_dest21__wen 1'0
assign \reg_5_dest25__wen 1'0
assign \reg_6_dest26__wen 1'0
assign \reg_7_dest27__wen 1'0
- assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$76
+ assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$6
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \data_i$77
process $group_69
assign \reg_0_dest20__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_0_dest20__data_i \data_i$77
+ assign \reg_0_dest20__data_i \data_i$7
sync init
end
process $group_70
assign \reg_1_dest21__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_1_dest21__data_i \data_i$77
+ assign \reg_1_dest21__data_i \data_i$7
sync init
end
process $group_71
assign \reg_2_dest22__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_2_dest22__data_i \data_i$77
+ assign \reg_2_dest22__data_i \data_i$7
sync init
end
process $group_72
assign \reg_3_dest23__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_3_dest23__data_i \data_i$77
+ assign \reg_3_dest23__data_i \data_i$7
sync init
end
process $group_73
assign \reg_4_dest24__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_4_dest24__data_i \data_i$77
+ assign \reg_4_dest24__data_i \data_i$7
sync init
end
process $group_74
assign \reg_5_dest25__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_5_dest25__data_i \data_i$77
+ assign \reg_5_dest25__data_i \data_i$7
sync init
end
process $group_75
assign \reg_6_dest26__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_6_dest26__data_i \data_i$77
+ assign \reg_6_dest26__data_i \data_i$7
sync init
end
process $group_76
assign \reg_7_dest27__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \reg_7_dest27__data_i \data_i$77
+ assign \reg_7_dest27__data_i \data_i$7
sync init
end
process $group_77
assign \reg_7_d_wr17__data_i \data_i
sync init
end
- connect \src2__ren 8'00000000
- connect \wen$76 8'00000000
- connect \data_i$77 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.spr"
+attribute \nmigen.hierarchy "test_issuer.core.spr"
module \spr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:197"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:197"
wire width 1 \wr_detect
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \src__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \dest__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:201"
wire width 1 \addrmatch
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_0
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
switch { \src__ren }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
case 1'1
assign \wr_detect 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
switch { $1 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
case 1'1
assign \wr_detect 1'1
end
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 6 \dest__waddr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 6 \src__raddr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:202"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:202"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:202"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 6
end
process $group_1
assign \addrmatch 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
switch { \src__ren }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
case 1'1
assign \addrmatch $3
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \src__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
wire width 1 $5
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
cell $and $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \addrmatch
connect \Y $5
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \dest__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \wr_detect
connect \Y $7
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$9$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$10$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$11$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$12$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$13$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$14$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$15$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$16$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$17$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$18$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$19$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$20$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$21$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$22$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$23$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$24$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$25$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$26$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$27$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$28$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$29$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$30$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$31$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$32$next
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wire width 64 \reg$33$next
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wire width 64 \reg$34$next
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wire width 64 \reg$35$next
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wire width 64 \reg$36$next
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wire width 64 \reg$37$next
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wire width 64 \reg$38$next
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wire width 64 \reg$39$next
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wire width 64 \reg$40$next
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wire width 64 \reg$41$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$42$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$43$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$44$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$45$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$46$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$47$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$48$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$49$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$50$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$51$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$52$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$53$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$54$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$55$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$56$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$57$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$58$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$59$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$60$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$61$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$62$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$63$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$64$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$65$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$66$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$67$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$68$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$69$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$70
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$70$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$71$next
process $group_2
assign \src__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
switch { \src__ren }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
switch { $5 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
case 1'1
assign \src__data_o \dest__data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
switch { $7 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:207"
switch \src__raddr
case 6'000000
assign \src__data_o \reg
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
wire width 64 \reg$72$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:193"
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wire width 64 \reg$116$next
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process $group_3
assign \reg$next \reg
assign \reg$115$next \reg$115
assign \reg$116$next \reg$116
assign \reg$117$next \reg$117
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211"
switch { \dest__wen }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:211"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211"
case 1'1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/regfile/regfile.py:212"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:212"
switch \dest__waddr
case 6'000000
assign \reg$next \dest__data_i
assign \reg$71$next \dest__data_i
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
connect \dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_INT_ra"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra"
module \rdpick_INT_ra
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 5 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 5 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 6 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 6 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \i
+ connect \Y $1
+ end
+ process $group_0
+ assign \ni 6'000000
+ assign \ni $1
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t0
+ process $group_1
+ assign \t0 1'0
+ assign \t0 \i [0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $4
+ connect \Y $3
+ end
+ process $group_2
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $8
+ connect \Y $7
+ end
+ process $group_3
+ assign \t2 1'0
+ assign \t2 $7
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $12
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $13
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+ connect \Y $12
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $12
+ connect \Y $11
+ end
+ process $group_4
+ assign \t3 1'0
+ assign \t3 $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $17
parameter \A_SIGNED 0
parameter \A_WIDTH 5
- parameter \Y_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+ connect \Y $16
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $18
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $16
+ connect \Y $15
+ end
+ process $group_5
+ assign \t4 1'0
+ assign \t4 $15
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 1
+ connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+ connect \Y $20
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $22
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $20
+ connect \Y $19
+ end
+ process $group_6
+ assign \t5 1'0
+ assign \t5 $19
+ sync init
+ end
+ process $group_7
+ assign \o 6'000000
+ assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $24
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $23
+ end
+ process $group_8
+ assign \en_o 1'0
+ assign \en_o $23
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb"
+module \rdpick_INT_rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 output 0 \en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 6 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 6 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 5'00000
+ assign \ni 6'000000
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t1 $3
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $9
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t2 $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $13
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
connect \Y $12
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t3 $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $17
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
connect \Y $16
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t4 $15
sync init
end
- process $group_6
- assign \o 5'00000
- assign \o { \t4 \t3 \t2 \t1 \t0 }
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $19
- end
- process $group_7
- assign \en_o 1'0
- assign \en_o $19
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_INT_rb"
-module \rdpick_INT_rb
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
- wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 5 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 5 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 5
- connect \A \i
- connect \Y $1
- end
- process $group_0
- assign \ni 5'00000
- assign \ni $1
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t0
- process $group_1
- assign \t0 1'0
- assign \t0 \i [0]
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $5
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $4
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $4
- connect \Y $3
- end
- process $group_2
- assign \t1 1'0
- assign \t1 $3
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 1
- connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
- connect \Y $8
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $not $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $8
- connect \Y $7
- end
- process $group_3
- assign \t2 1'0
- assign \t2 $7
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $13
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 1
- connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
- connect \Y $12
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $not $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $12
- connect \Y $11
- end
- process $group_4
- assign \t3 1'0
- assign \t3 $11
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $17
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $21
parameter \A_SIGNED 0
- parameter \A_WIDTH 5
+ parameter \A_WIDTH 6
parameter \Y_WIDTH 1
- connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
- connect \Y $16
+ connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+ connect \Y $20
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
- cell $not $18
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $16
- connect \Y $15
+ connect \A $20
+ connect \Y $19
end
- process $group_5
- assign \t4 1'0
- assign \t4 $15
+ process $group_6
+ assign \t5 1'0
+ assign \t5 $19
sync init
end
- process $group_6
- assign \o 5'00000
- assign \o { \t4 \t3 \t2 \t1 \t0 }
+ process $group_7
+ assign \o 6'000000
+ assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $20
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $24
parameter \A_SIGNED 0
- parameter \A_WIDTH 5
+ parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $19
+ connect \Y $23
end
- process $group_7
+ process $group_8
assign \en_o 1'0
- assign \en_o $19
+ assign \en_o $23
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_INT_rc"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc"
module \rdpick_INT_rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 2 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 2 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \o { \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_XER_xer_so"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so"
module \rdpick_XER_xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_XER_xer_ca"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca"
module \rdpick_XER_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 2 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 2 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \o { \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_CR_full_cr"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr"
module \rdpick_CR_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_CR_cr_a"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a"
module \rdpick_CR_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 2 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 2 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \o { \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_CR_cr_b"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b"
module \rdpick_CR_cr_b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_CR_cr_c"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c"
module \rdpick_CR_cr_c
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_FAST_spr1"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_spr1"
module \rdpick_FAST_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 1'0
+ assign \ni 2'00
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
- assign \t0 \i
- sync init
- end
- process $group_2
- assign \o 1'0
- assign \o { \t0 }
+ assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \o
+ connect \A $4
connect \Y $3
end
+ process $group_2
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
assign \en_o 1'0
- assign \en_o $3
+ assign \en_o $7
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_FAST_spr2"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_spr2"
module \rdpick_FAST_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 1'0
+ assign \ni 2'00
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
- assign \t0 \i
+ assign \t0 \i [0]
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $4
+ connect \Y $3
+ end
process $group_2
- assign \o 1'0
- assign \o { \t0 }
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
+ process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
+ assign \en_o 1'0
+ assign \en_o $7
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_cia"
+module \rdpick_FAST_cia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 output 0 \en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
+ connect \A \i
+ connect \Y $1
+ end
+ process $group_0
+ assign \ni 2'00
+ assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t0
+ process $group_1
+ assign \t0 1'0
+ assign \t0 \i [0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \o
+ connect \A $4
connect \Y $3
end
+ process $group_2
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
assign \en_o 1'0
- assign \en_o $3
+ assign \en_o $7
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.rdpick_FAST_cia"
-module \rdpick_FAST_cia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_msr"
+module \rdpick_FAST_msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_INT_o"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o"
module \wrpick_INT_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 5 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 5 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 6 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 6 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 5
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 5'00000
+ assign \ni 6'000000
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t1 $3
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $9
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t2 $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $13
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
connect \Y $12
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t3 $11
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $17
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
connect \Y $16
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t4 $15
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 1
+ connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+ connect \Y $20
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $22
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $20
+ connect \Y $19
+ end
process $group_6
- assign \o 5'00000
- assign \o { \t4 \t3 \t2 \t1 \t0 }
+ assign \t5 1'0
+ assign \t5 $19
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $20
+ process $group_7
+ assign \o 6'000000
+ assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $24
parameter \A_SIGNED 0
- parameter \A_WIDTH 5
+ parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $19
+ connect \Y $23
end
- process $group_7
+ process $group_8
assign \en_o 1'0
- assign \en_o $19
+ assign \en_o $23
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_INT_o1"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o1"
module \wrpick_INT_o1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_CR_full_cr"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr"
module \wrpick_CR_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_CR_cr_a"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a"
module \wrpick_CR_cr_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 4 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 4 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 4 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 4 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t1 $3
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $9
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t2 $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $13
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
connect \Y $12
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \o { \t3 \t2 \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_XER_xer_ca"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca"
module \wrpick_XER_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 3 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 3 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 3 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 3 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \i [0] \ni [1] }
connect \Y $4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \t1 $3
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $reduce_bool $9
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
connect \Y $8
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:50"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \o { \t2 \t1 \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_XER_xer_ov"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov"
module \wrpick_XER_xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_XER_xer_so"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so"
module \wrpick_XER_xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_FAST_spr1"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_spr1"
module \wrpick_FAST_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 1'0
+ assign \ni 2'00
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
- assign \t0 \i
- sync init
- end
- process $group_2
- assign \o 1'0
- assign \o { \t0 }
+ assign \t0 \i [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \o
+ connect \A $4
connect \Y $3
end
+ process $group_2
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
assign \en_o 1'0
- assign \en_o $3
+ assign \en_o $7
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_FAST_spr2"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_spr2"
module \wrpick_FAST_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
- wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
- wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 1'0
+ assign \ni 2'00
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
- assign \t0 \i
+ assign \t0 \i [0]
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $4
+ connect \Y $3
+ end
process $group_2
- assign \o 1'0
- assign \o { \t0 }
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
+ process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
+ assign \en_o 1'0
+ assign \en_o $7
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_nia"
+module \wrpick_FAST_nia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 output 0 \en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 input 1 \i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
+ wire width 2 \ni
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ wire width 2 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
+ connect \A \i
+ connect \Y $1
+ end
+ process $group_0
+ assign \ni 2'00
+ assign \ni $1
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t0
+ process $group_1
+ assign \t0 1'0
+ assign \t0 \i [0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A { \i [0] \ni [1] }
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \o
+ connect \A $4
connect \Y $3
end
+ process $group_2
+ assign \t1 1'0
+ assign \t1 $3
+ sync init
+ end
process $group_3
+ assign \o 2'00
+ assign \o { \t1 \t0 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
+ cell $reduce_bool $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \o
+ connect \Y $7
+ end
+ process $group_4
assign \en_o 1'0
- assign \en_o $3
+ assign \en_o $7
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core.wrpick_FAST_nia"
-module \wrpick_FAST_nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_msr"
+module \wrpick_FAST_msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 input 1 \i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 output 2 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:42"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
wire width 1 \ni
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
wire width 1 $1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:43"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
assign \ni $1
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:45"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
wire width 1 \t0
process $group_1
assign \t0 1'0
assign \o { \t0 }
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
wire width 1 $3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:55"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
cell $reduce_bool $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.core"
+attribute \nmigen.hierarchy "test_issuer.core"
module \core
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 0 \ad__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 1 \ad__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 input 2 \st__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 1 output 3 \st__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 4 \d_rd1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 output 5 \d_rd1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32"
wire width 1 input 6 \valid
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75"
wire width 1 input 7 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:319"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
wire width 1 input 8 \bigendian
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
wire width 32 input 9 \raw_opcode_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 output 10 \fast_nia_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_nia_wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:74"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:76"
wire width 1 output 11 \corebusy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 input 12 \wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 input 13 \data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 14 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 15 \clk
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:34"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
wire width 10 output 16 \fn_unit
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 17 \oper_i__insn_type
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 7 output 17 \oper_i__insn_type
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+ wire width 7 output 18 \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 19 \imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 20 \imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 21 \oper_i__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+ wire width 1 output 22 \lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 23 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 24 \rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 25 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 26 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 27 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
+ wire width 1 output 28 \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
+ wire width 1 output 29 \zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 30 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
+ wire width 1 output 31 \invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 32 \cr_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 33 \cr_out_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 2 output 34 \oper_i__input_carry
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
+ wire width 2 output 35 \input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 36 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
+ wire width 1 output 37 \output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 38 \oper_i__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
+ wire width 1 output 39 \input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 40 \oper_i__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
+ wire width 1 output 41 \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 42 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
+ wire width 1 output 43 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 44 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
+ wire width 1 output 45 \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 4 output 46 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
+ wire width 4 output 47 \data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+ wire width 32 output 48 \insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 49 \oper_i__byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
+ wire width 1 output 50 \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ wire width 1 output 51 \oper_i__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
+ wire width 1 output 52 \sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 53 \issue_i$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 54 \busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 55 \reg1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 56 \reg2_ok
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:33"
- wire width 7 output 18 \insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 19 \imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 20 \imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 21 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:59"
- wire width 1 output 22 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 23 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 24 \rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 25 \oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 26 \oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 27 \oper_i__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:62"
- wire width 1 output 28 \invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:63"
- wire width 1 output 29 \zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 30 \oper_i__invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:64"
- wire width 1 output 31 \invert_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 32 \cr_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 33 \cr_out_ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 34 \oper_i__input_carry
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:65"
- wire width 2 output 35 \input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 36 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:66"
- wire width 1 output 37 \output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 38 \oper_i__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:67"
- wire width 1 output 39 \input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \oper_i__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:68"
- wire width 1 output 41 \output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 42 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:69"
- wire width 1 output 43 \is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 44 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:70"
- wire width 1 output 45 \is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 46 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:72"
- wire width 4 output 47 \data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:71"
- wire width 32 output 48 \insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \oper_i__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:73"
- wire width 1 output 50 \byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 51 \oper_i__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:74"
- wire width 1 output 52 \sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 53 \issue_i$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 54 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 55 \reg1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 56 \reg2_ok
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ wire width 7 output 57 \oper_i__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ wire width 10 output 58 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ wire width 32 output 59 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ wire width 1 output 60 \oper_i__read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+ wire width 1 output 61 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ wire width 1 output 62 \oper_i__write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ wire width 1 output 63 \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 64 \issue_i$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 65 \busy_o$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 66 \cr_in1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 67 \cr_in2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 68 \cr_in2_ok$5
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 7 output 57 \oper_i__insn_type$2
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ wire width 7 output 69 \oper_i__insn_type$6
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 10 output 58 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 32 output 59 \oper_i__insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 60 \oper_i__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:56"
- wire width 1 output 61 \read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 62 \oper_i__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:58"
- wire width 1 output 63 \write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 64 \issue_i$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 65 \busy_o$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 66 \cr_in1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 67 \cr_in2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 68 \cr_in2_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ wire width 10 output 70 \oper_i__fn_unit$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ wire width 1 output 71 \oper_i__lk$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ wire width 1 output 72 \oper_i__is_32bit$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ wire width 32 output 73 \oper_i__insn$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 74 \issue_i$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 75 \busy_o$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 76 \fast1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 77 \fast2_ok
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 output 69 \oper_i__insn_type$6
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 7 output 78 \oper_i__insn_type$13
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 10 output 70 \oper_i__fn_unit$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 71 \oper_i__lk$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 72 \oper_i__is_32bit$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 output 73 \oper_i__insn$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 74 \issue_i$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 75 \busy_o$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 76 \fast1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 77 \fast2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 output 79 \oper_i__fn_unit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 output 80 \oper_i__insn$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 output 81 \oper_i__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 output 82 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76"
+ wire width 4 input 83 \traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 output 84 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77"
+ wire width 13 output 85 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 86 \issue_i$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 87 \busy_o$18
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 78 \oper_i__insn_type$13
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 7 output 88 \oper_i__insn_type$19
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 10 output 79 \oper_i__fn_unit$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 80 \oper_i__lk$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 81 \oper_i__invert_a$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 10 output 89 \oper_i__fn_unit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 90 \oper_i__lk$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 91 \oper_i__invert_a$22
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 82 \oper_i__input_carry$17
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 83 \oper_i__invert_out$18
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 84 \oper_i__output_carry$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 85 \oper_i__is_32bit$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 86 \oper_i__is_signed$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 87 \oper_i__data_len$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 88 \issue_i$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 89 \busy_o$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 2 output 92 \oper_i__input_carry$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 93 \oper_i__invert_out$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 94 \oper_i__output_carry$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 95 \oper_i__is_32bit$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 96 \oper_i__is_signed$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 4 output 97 \oper_i__data_len$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 98 \issue_i$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 99 \busy_o$30
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 90 \oper_i__insn_type$25
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 7 output 100 \oper_i__insn_type$31
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 91 \oper_i__input_carry$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 92 \oper_i__output_carry$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 93 \oper_i__input_cr$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 94 \oper_i__output_cr$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 95 \oper_i__is_32bit$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 96 \oper_i__is_signed$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 97 \issue_i$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 98 \busy_o$33
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 99 \reg3_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 2 output 101 \oper_i__input_carry$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 102 \oper_i__output_carry$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 103 \oper_i__input_cr$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 104 \oper_i__output_cr$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 105 \oper_i__is_32bit$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 106 \oper_i__is_signed$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 107 \issue_i$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 108 \busy_o$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 109 \reg3_ok
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 output 100 \oper_i__insn_type$34
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 101 \oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 102 \oper_i__is_32bit$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 103 \oper_i__is_signed$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 output 104 \oper_i__data_len$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 105 \oper_i__byte_reverse$38
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 106 \oper_i__sign_extend$39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 107 \oper_i__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:75"
- wire width 1 output 108 \update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 109 \issue_i$40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 110 \busy_o$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 111 \reg1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 112 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 113 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 114 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 115 \rd__rel$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 116 \rd__go$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 117 \src1_i$44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 118 \rd__rel$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 119 \rd__go$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 120 \src1_i$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 121 \rd__rel$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 122 \rd__go$49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 123 \src1_i$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 124 \rd__rel$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 125 \rd__go$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 126 \src1_i$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 127 \reg2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 128 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 129 \src2_i$54
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 130 \src2_i$55
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 131 \src2_i$56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 132 \src2_i$57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 133 \reg3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 134 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 135 \cr_in1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 136 \rd__rel$58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 137 \rd__go$59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 138 \cr_in2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 139 \cr_in2$60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 140 \fast1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 141 \src1_i$61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 142 \fast2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 143 \src2_i$62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 144 \rego
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 145 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 146 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 7 output 110 \oper_i__insn_type$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 111 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 112 \oper_i__is_32bit$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 113 \oper_i__is_signed$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 4 output 114 \oper_i__data_len$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 115 \oper_i__byte_reverse$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 116 \oper_i__sign_extend$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 117 \oper_i__update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
+ wire width 1 output 118 \update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 119 \issue_i$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 120 \busy_o$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 121 \reg1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 122 \rd__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 123 \rd__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 124 \src1_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 125 \rd__rel$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 126 \rd__go$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 127 \src1_i$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 128 \rd__rel$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 129 \rd__go$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 130 \src1_i$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 131 \rd__rel$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 132 \rd__go$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 133 \src1_i$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 134 \rd__rel$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 135 \rd__go$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 136 \src1_i$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 137 \rd__rel$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 138 \rd__go$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 139 \src1_i$62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 140 \reg2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 141 \src2_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 142 \src2_i$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 143 \src2_i$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 144 \src2_i$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 145 \src2_i$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 146 \src2_i$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 147 \reg3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 148 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 149 \cr_in1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 150 \rd__rel$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 151 \rd__go$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 152 \cr_in2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 153 \cr_in2$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 154 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 155 \src1_i$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 156 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 157 \src2_i$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 158 \rego
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 159 \wr__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 160 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 5 \wr__go$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 147 \wr__rel$63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 148 \wr__go$64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$64$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 149 \wr__rel$65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 150 \wr__go$66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$66$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 151 \wr__rel$67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 152 \wr__go$68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$68$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 153 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 154 \wr__rel$69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 155 \wr__go$70
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 \wr__go$70$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 156 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 157 \ea
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 158 \ea_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 159 \ea$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 160 \fasto1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 161 \wr__rel$72
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 162 \wr__go$73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$73$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 163 \fasto2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 164 \opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 161 \wr__rel$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 162 \wr__go$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 \wr__go$74$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 163 \wr__rel$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 164 \wr__go$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 \wr__go$76$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 165 \wr__rel$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 166 \wr__go$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 \wr__go$78$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 167 \wr__rel$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 168 \wr__go$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 \wr__go$80$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 169 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 170 \wr__rel$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 171 \wr__go$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 \wr__go$82$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 172 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 173 \ea
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 174 \ea_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 175 \ea$83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 176 \fasto1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 177 \wr__rel$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 178 \wr__go$85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 \wr__go$85$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 179 \fasto2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ wire width 32 output 180 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 165 \in1_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+ wire width 3 output 181 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 166 \in2_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+ wire width 4 output 182 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 167 \in3_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+ wire width 2 output 183 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 168 \out_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+ wire width 2 output 184 \out_sel
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 169 \rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 185 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 170 \cr_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+ wire width 3 output 186 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 171 \cr_out$74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:37"
- wire width 64 output 172 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+ wire width 3 output 187 \cr_out$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 64 output 188 \nia
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 10 output 173 \function_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 10 output 189 \function_unit
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 174 \internal_op
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 175 \rego_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 176 \ea_ok$75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 177 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 178 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 179 \spro
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 180 \spro_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 181 \fasto1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 182 \fasto2_ok
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+ wire width 7 output 190 \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 191 \rego_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 192 \ea_ok$87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 193 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 194 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 195 \spro
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 196 \spro_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 197 \fasto1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 198 \fasto2_ok
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 183 \ldst_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 184 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 185 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 186 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 187 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 188 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 189 \lk$76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 190 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 191 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 192 \upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+ wire width 4 output 199 \ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 200 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 201 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 202 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 203 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 204 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 205 \lk$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 206 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 207 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 208 \upd
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 output 193 \form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 194 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 195 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 output 196 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 197 \go_die_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 198 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 199 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 200 \go_die_i$77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 201 \shadown_i$78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 202 \dest1_o$79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 203 \go_die_i$80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 204 \shadown_i$81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 205 \dest1_o$82
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 206 \go_die_i$83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 207 \shadown_i$84
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 208 \dest1_o$85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 209 \go_die_i$86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 210 \shadown_i$87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 211 \dest1_o$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 212 \go_die_i$89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 213 \load_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 214 \stwd_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 215 \shadown_i$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+ wire width 5 output 209 \form
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 210 \rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 211 \sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+ wire width 8 output 212 \asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 213 \go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 214 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 215 \dest1_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 216 \go_die_i$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 217 \shadown_i$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 218 \dest1_o$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 219 \go_die_i$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 220 \shadown_i$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 221 \dest1_o$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 222 \go_die_i$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 223 \shadown_i$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 224 \dest1_o$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 225 \go_die_i$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 226 \shadown_i$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 227 \dest1_o$100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 228 \go_die_i$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 229 \shadown_i$102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 230 \dest1_o$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 231 \go_die_i$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
+ wire width 1 output 232 \load_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
+ wire width 1 output 233 \stwd_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 234 \shadown_i$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 235 \ldst_port0_is_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 236 \ldst_port0_is_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 237 \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 output 238 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 239 \ldst_port0_addr_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 output 240 \ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 241 \ldst_port0_addr_ok_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 242 \ldst_port0_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 243 \ldst_port0_ld_data_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 244 \ldst_port0_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 245 \ldst_port0_st_data_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 246 \ldst_port0_is_ld_i$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 247 \ldst_port0_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 248 \ldst_port0_is_st_i$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 249 \ldst_port0_data_len$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 48 output 250 \ldst_port0_addr_i$109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 251 \ldst_port0_addr_i_ok$110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+ wire width 8 output 252 \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+ wire width 48 output 253 \x_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 254 \ldst_port0_addr_ok_o$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 output 255 \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 256 \ldst_port0_ld_data_o$112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 257 \ldst_port0_ld_data_o_ok$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+ wire width 1 output 258 \x_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 259 \ldst_port0_st_data_i_ok$114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 260 \ldst_port0_st_data_i$115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+ wire width 64 output 261 \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 262 \ldst_port0_addr_exc_o$116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+ wire width 1 output 263 \x_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+ wire width 1 output 264 \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+ wire width 1 output 265 \m_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+ wire width 1 output 266 \x_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 output 267 \ldst_port0_go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 input 268 \ldst_port0_go_die_i$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 269 \ldst_port0_busy_o$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 270 \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 1 input 271 \x_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 272 \dbus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 273 \dbus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 274 \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 input 275 \dbus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 45 output 276 \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 8 output 277 \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 278 \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 output 279 \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+ wire width 1 input 280 \m_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+ wire width 1 output 281 \m_load_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+ wire width 1 output 282 \m_store_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+ wire width 45 output 283 \m_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+ wire width 1 output 284 \m_busy_o
cell \pdecode2 \pdecode2
connect \bigendian \bigendian
connect \raw_opcode_in \raw_opcode_in
connect \cr_in2_ok$1 \cr_in2_ok$5
connect \fast1_ok \fast1_ok
connect \fast2_ok \fast2_ok
+ connect \trapaddr \trapaddr
connect \reg3_ok \reg3_ok
connect \update \update
connect \reg1 \reg1
connect \reg3 \reg3
connect \cr_in1 \cr_in1
connect \cr_in2 \cr_in2
- connect \cr_in2$2 \cr_in2$60
+ connect \cr_in2$2 \cr_in2$70
connect \fast1 \fast1
connect \fast2 \fast2
connect \rego \rego
connect \out_sel \out_sel
connect \rc_sel \rc_sel
connect \cr_in \cr_in
- connect \cr_out$3 \cr_out$74
+ connect \cr_out$3 \cr_out$86
connect \nia \nia
connect \function_unit \function_unit
connect \internal_op \internal_op
connect \rego_ok \rego_ok
- connect \ea_ok \ea_ok$75
+ connect \ea_ok \ea_ok$87
connect \spr1 \spr1
connect \spr1_ok \spr1_ok
connect \spro \spro
connect \cry_out \cry_out
connect \is_32b \is_32b
connect \sgn \sgn
- connect \lk$4 \lk$76
+ connect \lk$4 \lk$88
connect \br \br
connect \sgn_ext \sgn_ext
connect \upd \upd
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 10 \fus_oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 64 \fus_oper_i__imm_data__imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__imm_data__imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__rc__rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__rc__rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__oe__oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__oe__oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 \fus_oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
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- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \fus_xer_ca$141
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \fus_xer_ca$175
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \fus_xer_ca$176
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_xer_ov_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \fus_xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_xer_so_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \fus_spr1_ok$177
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \fus_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \fus_spr1$178
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \fus_spr2_ok$179
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \fus_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \fus_spr2$180
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fus_nia_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \fus_nia_ok$181
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \fus_nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:105"
- wire width 1 \fus_ldst_port0_is_ld_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 \fus_ldst_port0_is_st_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:109"
- wire width 4 \fus_ldst_port0_data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 12 \fus_ldst_port0_addr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fus_ldst_port0_addr_i_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:117"
- wire width 1 \fus_ldst_port0_addr_exc_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/pimem.py:116"
- wire width 1 \fus_ldst_port0_addr_ok_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fus_ldst_port0_ld_data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fus_ldst_port0_ld_data_o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fus_ldst_port0_st_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fus_ldst_port0_st_data_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \fus_nia$182
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \fus_msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \fus_msr
cell \fus \fus
connect \ad__go \ad__go
connect \ad__rel \ad__rel
connect \oper_i__write_cr_whole \oper_i__write_cr_whole
connect \issue_i$4 \issue_i$3
connect \busy_o$5 \busy_o$4
- connect \rdmaskn$6 \fus_rdmaskn$91
+ connect \rdmaskn$6 \fus_rdmaskn$119
connect \oper_i__insn_type$7 \oper_i__insn_type$6
connect \oper_i__fn_unit$8 \oper_i__fn_unit$7
- connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$92
- connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$93
+ connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$120
+ connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$121
connect \oper_i__lk$11 \oper_i__lk$8
connect \oper_i__is_32bit$12 \oper_i__is_32bit$9
connect \oper_i__insn$13 \oper_i__insn$10
connect \issue_i$14 \issue_i$11
connect \busy_o$15 \busy_o$12
- connect \rdmaskn$16 \fus_rdmaskn$94
+ connect \rdmaskn$16 \fus_rdmaskn$122
connect \oper_i__insn_type$17 \oper_i__insn_type$13
connect \oper_i__fn_unit$18 \oper_i__fn_unit$14
- connect \oper_i__imm_data__imm$19 \fus_oper_i__imm_data__imm$95
- connect \oper_i__imm_data__imm_ok$20 \fus_oper_i__imm_data__imm_ok$96
- connect \oper_i__lk$21 \oper_i__lk$15
- connect \oper_i__rc__rc$22 \fus_oper_i__rc__rc$97
- connect \oper_i__rc__rc_ok$23 \fus_oper_i__rc__rc_ok$98
- connect \oper_i__oe__oe$24 \fus_oper_i__oe__oe$99
- connect \oper_i__oe__oe_ok$25 \fus_oper_i__oe__oe_ok$100
- connect \oper_i__invert_a$26 \oper_i__invert_a$16
- connect \oper_i__zero_a$27 \fus_oper_i__zero_a$101
- connect \oper_i__input_carry$28 \oper_i__input_carry$17
- connect \oper_i__invert_out$29 \oper_i__invert_out$18
- connect \oper_i__write_cr__data$30 \fus_oper_i__write_cr__data$102
- connect \oper_i__write_cr__ok$31 \fus_oper_i__write_cr__ok$103
- connect \oper_i__output_carry$32 \oper_i__output_carry$19
- connect \oper_i__is_32bit$33 \oper_i__is_32bit$20
- connect \oper_i__is_signed$34 \oper_i__is_signed$21
- connect \oper_i__data_len$35 \oper_i__data_len$22
- connect \oper_i__insn$36 \fus_oper_i__insn$104
- connect \issue_i$37 \issue_i$23
- connect \busy_o$38 \busy_o$24
- connect \rdmaskn$39 \fus_rdmaskn$105
- connect \oper_i__insn_type$40 \oper_i__insn_type$25
- connect \oper_i__fn_unit$41 \fus_oper_i__fn_unit$106
- connect \oper_i__imm_data__imm$42 \fus_oper_i__imm_data__imm$107
- connect \oper_i__imm_data__imm_ok$43 \fus_oper_i__imm_data__imm_ok$108
- connect \oper_i__rc__rc$44 \fus_oper_i__rc__rc$109
- connect \oper_i__rc__rc_ok$45 \fus_oper_i__rc__rc_ok$110
- connect \oper_i__oe__oe$46 \fus_oper_i__oe__oe$111
- connect \oper_i__oe__oe_ok$47 \fus_oper_i__oe__oe_ok$112
- connect \oper_i__write_cr__data$48 \fus_oper_i__write_cr__data$113
- connect \oper_i__write_cr__ok$49 \fus_oper_i__write_cr__ok$114
- connect \oper_i__input_carry$50 \oper_i__input_carry$26
- connect \oper_i__output_carry$51 \oper_i__output_carry$27
- connect \oper_i__input_cr$52 \oper_i__input_cr$28
- connect \oper_i__output_cr$53 \oper_i__output_cr$29
- connect \oper_i__is_32bit$54 \oper_i__is_32bit$30
- connect \oper_i__is_signed$55 \oper_i__is_signed$31
- connect \oper_i__insn$56 \fus_oper_i__insn$115
- connect \issue_i$57 \issue_i$32
- connect \busy_o$58 \busy_o$33
- connect \rdmaskn$59 \fus_rdmaskn$116
- connect \oper_i__insn_type$60 \oper_i__insn_type$34
- connect \oper_i__imm_data__imm$61 \fus_oper_i__imm_data__imm$117
- connect \oper_i__imm_data__imm_ok$62 \fus_oper_i__imm_data__imm_ok$118
- connect \oper_i__zero_a$63 \oper_i__zero_a
- connect \oper_i__is_32bit$64 \oper_i__is_32bit$35
- connect \oper_i__is_signed$65 \oper_i__is_signed$36
- connect \oper_i__data_len$66 \oper_i__data_len$37
- connect \oper_i__byte_reverse$67 \oper_i__byte_reverse$38
- connect \oper_i__sign_extend$68 \oper_i__sign_extend$39
+ connect \oper_i__insn$19 \oper_i__insn$15
+ connect \oper_i__is_32bit$20 \oper_i__is_32bit$16
+ connect \oper_i__traptype \oper_i__traptype
+ connect \oper_i__trapaddr \oper_i__trapaddr
+ connect \issue_i$21 \issue_i$17
+ connect \busy_o$22 \busy_o$18
+ connect \rdmaskn$23 \fus_rdmaskn$123
+ connect \oper_i__insn_type$24 \oper_i__insn_type$19
+ connect \oper_i__fn_unit$25 \oper_i__fn_unit$20
+ connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$124
+ connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$125
+ connect \oper_i__lk$28 \oper_i__lk$21
+ connect \oper_i__rc__rc$29 \fus_oper_i__rc__rc$126
+ connect \oper_i__rc__rc_ok$30 \fus_oper_i__rc__rc_ok$127
+ connect \oper_i__oe__oe$31 \fus_oper_i__oe__oe$128
+ connect \oper_i__oe__oe_ok$32 \fus_oper_i__oe__oe_ok$129
+ connect \oper_i__invert_a$33 \oper_i__invert_a$22
+ connect \oper_i__zero_a$34 \fus_oper_i__zero_a$130
+ connect \oper_i__input_carry$35 \oper_i__input_carry$23
+ connect \oper_i__invert_out$36 \oper_i__invert_out$24
+ connect \oper_i__write_cr__data$37 \fus_oper_i__write_cr__data$131
+ connect \oper_i__write_cr__ok$38 \fus_oper_i__write_cr__ok$132
+ connect \oper_i__output_carry$39 \oper_i__output_carry$25
+ connect \oper_i__is_32bit$40 \oper_i__is_32bit$26
+ connect \oper_i__is_signed$41 \oper_i__is_signed$27
+ connect \oper_i__data_len$42 \oper_i__data_len$28
+ connect \oper_i__insn$43 \fus_oper_i__insn$133
+ connect \issue_i$44 \issue_i$29
+ connect \busy_o$45 \busy_o$30
+ connect \rdmaskn$46 \fus_rdmaskn$134
+ connect \oper_i__insn_type$47 \oper_i__insn_type$31
+ connect \oper_i__fn_unit$48 \fus_oper_i__fn_unit$135
+ connect \oper_i__imm_data__imm$49 \fus_oper_i__imm_data__imm$136
+ connect \oper_i__imm_data__imm_ok$50 \fus_oper_i__imm_data__imm_ok$137
+ connect \oper_i__rc__rc$51 \fus_oper_i__rc__rc$138
+ connect \oper_i__rc__rc_ok$52 \fus_oper_i__rc__rc_ok$139
+ connect \oper_i__oe__oe$53 \fus_oper_i__oe__oe$140
+ connect \oper_i__oe__oe_ok$54 \fus_oper_i__oe__oe_ok$141
+ connect \oper_i__write_cr__data$55 \fus_oper_i__write_cr__data$142
+ connect \oper_i__write_cr__ok$56 \fus_oper_i__write_cr__ok$143
+ connect \oper_i__input_carry$57 \oper_i__input_carry$32
+ connect \oper_i__output_carry$58 \oper_i__output_carry$33
+ connect \oper_i__input_cr$59 \oper_i__input_cr$34
+ connect \oper_i__output_cr$60 \oper_i__output_cr$35
+ connect \oper_i__is_32bit$61 \oper_i__is_32bit$36
+ connect \oper_i__is_signed$62 \oper_i__is_signed$37
+ connect \oper_i__insn$63 \fus_oper_i__insn$144
+ connect \issue_i$64 \issue_i$38
+ connect \busy_o$65 \busy_o$39
+ connect \rdmaskn$66 \fus_rdmaskn$145
+ connect \oper_i__insn_type$67 \oper_i__insn_type$40
+ connect \oper_i__imm_data__imm$68 \fus_oper_i__imm_data__imm$146
+ connect \oper_i__imm_data__imm_ok$69 \fus_oper_i__imm_data__imm_ok$147
+ connect \oper_i__zero_a$70 \oper_i__zero_a
+ connect \oper_i__is_32bit$71 \oper_i__is_32bit$41
+ connect \oper_i__is_signed$72 \oper_i__is_signed$42
+ connect \oper_i__data_len$73 \oper_i__data_len$43
+ connect \oper_i__byte_reverse$74 \oper_i__byte_reverse$44
+ connect \oper_i__sign_extend$75 \oper_i__sign_extend$45
connect \oper_i__update \oper_i__update
- connect \issue_i$69 \issue_i$40
- connect \busy_o$70 \busy_o$41
- connect \rdmaskn$71 \fus_rdmaskn$119
+ connect \issue_i$76 \issue_i$46
+ connect \busy_o$77 \busy_o$47
+ connect \rdmaskn$78 \fus_rdmaskn$148
connect \rd__rel \rd__rel
connect \rd__go \rd__go
connect \src1_i \src1_i
- connect \rd__rel$72 \rd__rel$42
- connect \rd__go$73 \rd__go$43
- connect \src1_i$74 \src1_i$44
- connect \rd__rel$75 \rd__rel$45
- connect \rd__go$76 \rd__go$46
- connect \src1_i$77 \src1_i$47
- connect \rd__rel$78 \rd__rel$48
- connect \rd__go$79 \rd__go$49
- connect \src1_i$80 \src1_i$50
- connect \rd__rel$81 \rd__rel$51
- connect \rd__go$82 \rd__go$52
- connect \src1_i$83 \src1_i$53
+ connect \rd__rel$79 \rd__rel$48
+ connect \rd__go$80 \rd__go$49
+ connect \src1_i$81 \src1_i$50
+ connect \rd__rel$82 \rd__rel$51
+ connect \rd__go$83 \rd__go$52
+ connect \src1_i$84 \src1_i$53
+ connect \rd__rel$85 \rd__rel$54
+ connect \rd__go$86 \rd__go$55
+ connect \src1_i$87 \src1_i$56
+ connect \rd__rel$88 \rd__rel$57
+ connect \rd__go$89 \rd__go$58
+ connect \src1_i$90 \src1_i$59
+ connect \rd__rel$91 \rd__rel$60
+ connect \rd__go$92 \rd__go$61
+ connect \src1_i$93 \src1_i$62
connect \src2_i \src2_i
- connect \src2_i$84 \src2_i$54
- connect \src2_i$85 \src2_i$55
- connect \src2_i$86 \src2_i$56
- connect \src2_i$87 \src2_i$57
+ connect \src2_i$94 \src2_i$63
+ connect \src2_i$95 \src2_i$64
+ connect \src2_i$96 \src2_i$65
+ connect \src2_i$97 \src2_i$66
+ connect \src2_i$98 \src2_i$67
connect \src3_i \fus_src3_i
- connect \src3_i$88 \src3_i
- connect \src3_i$89 \fus_src3_i$120
+ connect \src3_i$99 \src3_i
+ connect \src3_i$100 \fus_src3_i$149
connect \src4_i \fus_src4_i
- connect \src4_i$90 \fus_src4_i$121
- connect \src3_i$91 \fus_src3_i$122
- connect \src4_i$92 \fus_src4_i$123
- connect \rd__rel$93 \rd__rel$58
- connect \rd__go$94 \rd__go$59
- connect \src3_i$95 \fus_src3_i$124
+ connect \src4_i$101 \fus_src4_i$150
+ connect \src3_i$102 \fus_src3_i$151
+ connect \src4_i$103 \fus_src4_i$152
+ connect \rd__rel$104 \rd__rel$68
+ connect \rd__go$105 \rd__go$69
+ connect \src3_i$106 \fus_src3_i$153
connect \src5_i \fus_src5_i
connect \src6_i \fus_src6_i
- connect \src1_i$96 \src1_i$61
- connect \src2_i$97 \src2_i$62
- connect \src4_i$98 \fus_src4_i$125
+ connect \src1_i$107 \src1_i$71
+ connect \src3_i$108 \fus_src3_i$154
+ connect \src2_i$109 \src2_i$72
+ connect \src4_i$110 \fus_src4_i$155
+ connect \src4_i$111 \fus_src4_i$156
+ connect \src5_i$112 \fus_src5_i$157
+ connect \src6_i$113 \fus_src6_i$158
connect \o_ok \fus_o_ok
connect \wr__rel \wr__rel
connect \wr__go \wr__go
- connect \o_ok$99 \fus_o_ok$126
- connect \wr__rel$100 \wr__rel$63
- connect \wr__go$101 \wr__go$64
- connect \o_ok$102 \fus_o_ok$127
- connect \wr__rel$103 \wr__rel$65
- connect \wr__go$104 \wr__go$66
- connect \o_ok$105 \fus_o_ok$128
- connect \wr__rel$106 \wr__rel$67
- connect \wr__go$107 \wr__go$68
- connect \wr__rel$108 \wr__rel$69
- connect \wr__go$109 \wr__go$70
+ connect \o_ok$114 \fus_o_ok$159
+ connect \wr__rel$115 \wr__rel$73
+ connect \wr__go$116 \wr__go$74
+ connect \o_ok$117 \fus_o_ok$160
+ connect \wr__rel$118 \wr__rel$75
+ connect \wr__go$119 \wr__go$76
+ connect \o_ok$120 \fus_o_ok$161
+ connect \wr__rel$121 \wr__rel$77
+ connect \wr__go$122 \wr__go$78
+ connect \o_ok$123 \fus_o_ok$162
+ connect \wr__rel$124 \wr__rel$79
+ connect \wr__go$125 \wr__go$80
+ connect \wr__rel$126 \wr__rel$81
+ connect \wr__go$127 \wr__go$82
connect \o \fus_o
- connect \o$110 \fus_o$129
- connect \o$111 \fus_o$130
- connect \o$112 \fus_o$131
- connect \o$113 \o
- connect \ea \ea$71
+ connect \o$128 \fus_o$163
+ connect \o$129 \fus_o$164
+ connect \o$130 \fus_o$165
+ connect \o$131 \fus_o$166
+ connect \o$132 \o
+ connect \ea \ea$83
connect \full_cr_ok \fus_full_cr_ok
connect \full_cr \fus_full_cr
connect \cr_a_ok \fus_cr_a_ok
- connect \cr_a_ok$114 \fus_cr_a_ok$132
- connect \cr_a_ok$115 \fus_cr_a_ok$133
- connect \cr_a_ok$116 \fus_cr_a_ok$134
+ connect \cr_a_ok$133 \fus_cr_a_ok$167
+ connect \cr_a_ok$134 \fus_cr_a_ok$168
+ connect \cr_a_ok$135 \fus_cr_a_ok$169
connect \cr_a \fus_cr_a
- connect \cr_a$117 \fus_cr_a$135
- connect \cr_a$118 \fus_cr_a$136
- connect \cr_a$119 \fus_cr_a$137
+ connect \cr_a$136 \fus_cr_a$170
+ connect \cr_a$137 \fus_cr_a$171
+ connect \cr_a$138 \fus_cr_a$172
connect \xer_ca_ok \fus_xer_ca_ok
- connect \xer_ca_ok$120 \fus_xer_ca_ok$138
- connect \xer_ca_ok$121 \fus_xer_ca_ok$139
+ connect \xer_ca_ok$139 \fus_xer_ca_ok$173
+ connect \xer_ca_ok$140 \fus_xer_ca_ok$174
connect \xer_ca \fus_xer_ca
- connect \xer_ca$122 \fus_xer_ca$140
- connect \xer_ca$123 \fus_xer_ca$141
+ connect \xer_ca$141 \fus_xer_ca$175
+ connect \xer_ca$142 \fus_xer_ca$176
connect \xer_ov_ok \fus_xer_ov_ok
connect \xer_ov \fus_xer_ov
connect \xer_so_ok \fus_xer_so_ok
connect \xer_so \fus_xer_so
connect \spr1_ok \fus_spr1_ok
- connect \wr__rel$124 \wr__rel$72
- connect \wr__go$125 \wr__go$73
+ connect \wr__rel$143 \wr__rel$84
+ connect \wr__go$144 \wr__go$85
+ connect \spr1_ok$145 \fus_spr1_ok$177
connect \spr1 \fus_spr1
+ connect \spr1$146 \fus_spr1$178
connect \spr2_ok \fus_spr2_ok
+ connect \spr2_ok$147 \fus_spr2_ok$179
connect \spr2 \fus_spr2
+ connect \spr2$148 \fus_spr2$180
connect \nia_ok \fus_nia_ok
+ connect \nia_ok$149 \fus_nia_ok$181
connect \nia \fus_nia
+ connect \nia$150 \fus_nia$182
+ connect \msr_ok \fus_msr_ok
+ connect \msr \fus_msr
connect \go_die_i \go_die_i
connect \shadown_i \shadown_i
connect \dest1_o \dest1_o
- connect \go_die_i$126 \go_die_i$77
- connect \shadown_i$127 \shadown_i$78
- connect \dest1_o$128 \dest1_o$79
- connect \go_die_i$129 \go_die_i$80
- connect \shadown_i$130 \shadown_i$81
- connect \dest1_o$131 \dest1_o$82
- connect \go_die_i$132 \go_die_i$83
- connect \shadown_i$133 \shadown_i$84
- connect \dest1_o$134 \dest1_o$85
- connect \go_die_i$135 \go_die_i$86
- connect \shadown_i$136 \shadown_i$87
- connect \dest1_o$137 \dest1_o$88
- connect \go_die_i$138 \go_die_i$89
+ connect \go_die_i$151 \go_die_i$89
+ connect \shadown_i$152 \shadown_i$90
+ connect \dest1_o$153 \dest1_o$91
+ connect \go_die_i$154 \go_die_i$92
+ connect \shadown_i$155 \shadown_i$93
+ connect \dest1_o$156 \dest1_o$94
+ connect \go_die_i$157 \go_die_i$95
+ connect \shadown_i$158 \shadown_i$96
+ connect \dest1_o$159 \dest1_o$97
+ connect \go_die_i$160 \go_die_i$98
+ connect \shadown_i$161 \shadown_i$99
+ connect \dest1_o$162 \dest1_o$100
+ connect \go_die_i$163 \go_die_i$101
+ connect \shadown_i$164 \shadown_i$102
+ connect \dest1_o$165 \dest1_o$103
+ connect \go_die_i$166 \go_die_i$104
connect \load_mem_o \load_mem_o
connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i$139 \shadown_i$90
- connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
- connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
- connect \ldst_port0_data_len \fus_ldst_port0_data_len
- connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
- connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
- connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
- connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
- connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
+ connect \shadown_i$167 \shadown_i$105
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i
+ connect \ldst_port0_data_len \ldst_port0_data_len
+ connect \ldst_port0_addr_i \ldst_port0_addr_i
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
end
cell \l0 \l0
connect \rst \rst
connect \clk \clk
- connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
- connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
- connect \ldst_port0_data_len \fus_ldst_port0_data_len
- connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
- connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
- connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
- connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
- connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
- connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i
+ connect \ldst_port0_data_len \ldst_port0_data_len
+ connect \ldst_port0_addr_i \ldst_port0_addr_i
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+ connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$106
+ connect \ldst_port0_busy_o \ldst_port0_busy_o
+ connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$107
+ connect \ldst_port0_data_len$3 \ldst_port0_data_len$108
+ connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$109
+ connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$110
+ connect \x_mask_i \x_mask_i
+ connect \x_addr_i \x_addr_i
+ connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$111
+ connect \m_ld_data_o \m_ld_data_o
+ connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$112
+ connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$113
+ connect \x_busy_o \x_busy_o
+ connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$114
+ connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$115
+ connect \x_st_data_i \x_st_data_i
+ connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$116
+ connect \x_ld_i \x_ld_i
+ connect \x_st_i \x_st_i
+ connect \m_valid_i \m_valid_i
+ connect \x_valid_i \x_valid_i
+ connect \ldst_port0_go_die_i \ldst_port0_go_die_i
+ connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$117
+ connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$118
+ connect \dbus__cyc \dbus__cyc
+ connect \x_stall_i \x_stall_i
+ connect \dbus__ack \dbus__ack
+ connect \dbus__err \dbus__err
+ connect \dbus__stb \dbus__stb
+ connect \dbus__dat_r \dbus__dat_r
+ connect \dbus__adr \dbus__adr
+ connect \dbus__sel \dbus__sel
+ connect \dbus__we \dbus__we
+ connect \dbus__dat_w \dbus__dat_w
+ connect \m_stall_i \m_stall_i
+ connect \m_load_err_o \m_load_err_o
+ connect \m_store_err_o \m_store_err_o
+ connect \m_badaddr_o \m_badaddr_o
+ connect \m_busy_o \m_busy_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_data_i$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen$142
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen$142$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i$143
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i$143$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 32 \int_wen$183
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 32 \int_wen$183$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \int_data_i$184
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \int_data_i$184$next
cell \int \int
connect \rst \rst
connect \clk \clk
connect \src3__data_o \int_src3__data_o
connect \wen \int_wen
connect \data_i \int_data_i
- connect \wen$1 \int_wen$142
- connect \data_i$2 \int_data_i$143
+ connect \wen$1 \int_wen$183
+ connect \data_i$2 \int_data_i$184
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_full_rd__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \cr_full_rd__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_full_wr__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_full_wr__wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \cr_full_wr__data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \cr_full_wr__data_i$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_data_i$next
cell \cr \cr
connect \rst \rst
connect \wen \cr_wen
connect \data_i \cr_data_i
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \xer_src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \xer_src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \xer_src2__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \xer_src2__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \xer_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \xer_wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \xer_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \xer_data_i$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$144
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$144$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$145
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$145$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$146
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$146$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$147
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$147$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 3 \xer_wen$185
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 3 \xer_wen$185$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 2 \xer_data_i$186
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 2 \xer_data_i$186$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 3 \xer_wen$187
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 3 \xer_wen$187$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 2 \xer_data_i$188
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 2 \xer_data_i$188$next
cell \xer \xer
connect \rst \rst
connect \clk \clk
connect \src2__data_o \xer_src2__data_o
connect \wen \xer_wen
connect \data_i \xer_data_i
- connect \wen$1 \xer_wen$144
- connect \data_i$2 \xer_data_i$145
- connect \wen$3 \xer_wen$146
- connect \data_i$4 \xer_data_i$147
+ connect \wen$1 \xer_wen$185
+ connect \data_i$2 \xer_data_i$186
+ connect \wen$3 \xer_wen$187
+ connect \data_i$4 \xer_data_i$188
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_src3__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_src3__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_src4__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_src4__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_src1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_src1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \fast_src2__ren
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_src2__data_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_wen$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_data_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_data_i$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$148
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$148$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$149
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$149$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$150
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$150$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \fast_wen$189
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \fast_wen$189$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$190
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$190$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$191
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$191$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \fast_wen$192
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \fast_wen$192$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$193
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 \fast_data_i$193$next
cell \fast \fast
connect \d_rd1__ren \d_rd1__ren
connect \d_rd1__data_o \d_rd1__data_o
connect \src4__data_o \fast_src4__data_o
connect \src1__ren \fast_src1__ren
connect \src1__data_o \fast_src1__data_o
+ connect \src2__ren \fast_src2__ren
+ connect \src2__data_o \fast_src2__data_o
connect \wen$1 \fast_wen
connect \data_i$2 \fast_data_i
- connect \wen$3 \fast_wen$148
- connect \data_i$4 \fast_data_i$149
- connect \data_i$5 \fast_data_i$150
+ connect \wen$3 \fast_wen$189
+ connect \data_i$4 \fast_data_i$190
+ connect \data_i$5 \fast_data_i$191
+ connect \wen$6 \fast_wen$192
+ connect \data_i$7 \fast_data_i$193
end
cell \spr \spr
connect \rst \rst
connect \clk \clk
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_INT_ra_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 \rdpick_INT_ra_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 \rdpick_INT_ra_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 \rdpick_INT_ra_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 \rdpick_INT_ra_o
cell \rdpick_INT_ra \rdpick_INT_ra
connect \en_o \rdpick_INT_ra_en_o
connect \i \rdpick_INT_ra_i
connect \o \rdpick_INT_ra_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_INT_rb_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 \rdpick_INT_rb_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 \rdpick_INT_rb_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 \rdpick_INT_rb_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 \rdpick_INT_rb_o
cell \rdpick_INT_rb \rdpick_INT_rb
connect \en_o \rdpick_INT_rb_en_o
connect \i \rdpick_INT_rb_i
connect \o \rdpick_INT_rb_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_INT_rc_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 \rdpick_INT_rc_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 \rdpick_INT_rc_o
cell \rdpick_INT_rc \rdpick_INT_rc
connect \en_o \rdpick_INT_rc_en_o
connect \i \rdpick_INT_rc_i
connect \o \rdpick_INT_rc_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_XER_xer_so_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \rdpick_XER_xer_so_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \rdpick_XER_xer_so_o
cell \rdpick_XER_xer_so \rdpick_XER_xer_so
connect \en_o \rdpick_XER_xer_so_en_o
connect \i \rdpick_XER_xer_so_i
connect \o \rdpick_XER_xer_so_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_XER_xer_ca_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 \rdpick_XER_xer_ca_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 \rdpick_XER_xer_ca_o
cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
connect \en_o \rdpick_XER_xer_ca_en_o
connect \i \rdpick_XER_xer_ca_i
connect \o \rdpick_XER_xer_ca_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_CR_full_cr_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \rdpick_CR_full_cr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \rdpick_CR_full_cr_o
cell \rdpick_CR_full_cr \rdpick_CR_full_cr
connect \en_o \rdpick_CR_full_cr_en_o
connect \i \rdpick_CR_full_cr_i
connect \o \rdpick_CR_full_cr_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_CR_cr_a_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 2 \rdpick_CR_cr_a_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 2 \rdpick_CR_cr_a_o
cell \rdpick_CR_cr_a \rdpick_CR_cr_a
connect \en_o \rdpick_CR_cr_a_en_o
connect \i \rdpick_CR_cr_a_i
connect \o \rdpick_CR_cr_a_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_CR_cr_b_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \rdpick_CR_cr_b_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \rdpick_CR_cr_b_o
cell \rdpick_CR_cr_b \rdpick_CR_cr_b
connect \en_o \rdpick_CR_cr_b_en_o
connect \i \rdpick_CR_cr_b_i
connect \o \rdpick_CR_cr_b_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_CR_cr_c_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \rdpick_CR_cr_c_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \rdpick_CR_cr_c_o
cell \rdpick_CR_cr_c \rdpick_CR_cr_c
connect \en_o \rdpick_CR_cr_c_en_o
connect \i \rdpick_CR_cr_c_i
connect \o \rdpick_CR_cr_c_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_FAST_spr1_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \rdpick_FAST_spr1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \rdpick_FAST_spr1_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \rdpick_FAST_spr1_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \rdpick_FAST_spr1_o
cell \rdpick_FAST_spr1 \rdpick_FAST_spr1
connect \en_o \rdpick_FAST_spr1_en_o
connect \i \rdpick_FAST_spr1_i
connect \o \rdpick_FAST_spr1_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_FAST_spr2_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \rdpick_FAST_spr2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \rdpick_FAST_spr2_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \rdpick_FAST_spr2_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \rdpick_FAST_spr2_o
cell \rdpick_FAST_spr2 \rdpick_FAST_spr2
connect \en_o \rdpick_FAST_spr2_en_o
connect \i \rdpick_FAST_spr2_i
connect \o \rdpick_FAST_spr2_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_FAST_cia_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \rdpick_FAST_cia_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \rdpick_FAST_cia_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \rdpick_FAST_cia_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \rdpick_FAST_cia_o
cell \rdpick_FAST_cia \rdpick_FAST_cia
connect \en_o \rdpick_FAST_cia_en_o
connect \i \rdpick_FAST_cia_i
connect \o \rdpick_FAST_cia_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \rdpick_FAST_msr_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 1 \rdpick_FAST_msr_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 1 \rdpick_FAST_msr_o
+ cell \rdpick_FAST_msr \rdpick_FAST_msr
+ connect \en_o \rdpick_FAST_msr_en_o
+ connect \i \rdpick_FAST_msr_i
+ connect \o \rdpick_FAST_msr_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_INT_o_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 5 \wrpick_INT_o_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 5 \wrpick_INT_o_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 6 \wrpick_INT_o_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 6 \wrpick_INT_o_o
cell \wrpick_INT_o \wrpick_INT_o
connect \en_o \wrpick_INT_o_en_o
connect \i \wrpick_INT_o_i
connect \o \wrpick_INT_o_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_INT_o1_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \wrpick_INT_o1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \wrpick_INT_o1_o
cell \wrpick_INT_o1 \wrpick_INT_o1
connect \en_o \wrpick_INT_o1_en_o
connect \i \wrpick_INT_o1_i
connect \o \wrpick_INT_o1_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_CR_full_cr_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \wrpick_CR_full_cr_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \wrpick_CR_full_cr_o
cell \wrpick_CR_full_cr \wrpick_CR_full_cr
connect \en_o \wrpick_CR_full_cr_en_o
connect \i \wrpick_CR_full_cr_i
connect \o \wrpick_CR_full_cr_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_CR_cr_a_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 4 \wrpick_CR_cr_a_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 4 \wrpick_CR_cr_a_o
cell \wrpick_CR_cr_a \wrpick_CR_cr_a
connect \en_o \wrpick_CR_cr_a_en_o
connect \i \wrpick_CR_cr_a_i
connect \o \wrpick_CR_cr_a_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_XER_xer_ca_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 3 \wrpick_XER_xer_ca_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 3 \wrpick_XER_xer_ca_o
cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
connect \en_o \wrpick_XER_xer_ca_en_o
connect \i \wrpick_XER_xer_ca_i
connect \o \wrpick_XER_xer_ca_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_XER_xer_ov_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \wrpick_XER_xer_ov_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \wrpick_XER_xer_ov_o
cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
connect \en_o \wrpick_XER_xer_ov_en_o
connect \i \wrpick_XER_xer_ov_i
connect \o \wrpick_XER_xer_ov_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_XER_xer_so_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \wrpick_XER_xer_so_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
wire width 1 \wrpick_XER_xer_so_o
cell \wrpick_XER_xer_so \wrpick_XER_xer_so
connect \en_o \wrpick_XER_xer_so_en_o
connect \i \wrpick_XER_xer_so_i
connect \o \wrpick_XER_xer_so_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_FAST_spr1_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \wrpick_FAST_spr1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \wrpick_FAST_spr1_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \wrpick_FAST_spr1_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \wrpick_FAST_spr1_o
cell \wrpick_FAST_spr1 \wrpick_FAST_spr1
connect \en_o \wrpick_FAST_spr1_en_o
connect \i \wrpick_FAST_spr1_i
connect \o \wrpick_FAST_spr1_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_FAST_spr2_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \wrpick_FAST_spr2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \wrpick_FAST_spr2_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \wrpick_FAST_spr2_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \wrpick_FAST_spr2_o
cell \wrpick_FAST_spr2 \wrpick_FAST_spr2
connect \en_o \wrpick_FAST_spr2_en_o
connect \i \wrpick_FAST_spr2_i
connect \o \wrpick_FAST_spr2_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:35"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_FAST_nia_en_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \wrpick_FAST_nia_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \wrpick_FAST_nia_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \wrpick_FAST_nia_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \wrpick_FAST_nia_o
cell \wrpick_FAST_nia \wrpick_FAST_nia
connect \en_o \wrpick_FAST_nia_en_o
connect \i \wrpick_FAST_nia_i
connect \o \wrpick_FAST_nia_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \wrpick_FAST_msr_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 1 \wrpick_FAST_msr_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 1 \wrpick_FAST_msr_o
+ cell \wrpick_FAST_msr \wrpick_FAST_msr
+ connect \en_o \wrpick_FAST_msr_en_o
+ connect \i \wrpick_FAST_msr_i
+ connect \o \wrpick_FAST_msr_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_alu0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $151
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $152
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $153
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $194
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $195
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $196
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 2'10
- connect \Y $152
+ connect \Y $195
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $154
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $197
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $152
- connect \Y $151
+ connect \A $195
+ connect \Y $194
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $155
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $156
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $198
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $199
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $151
- connect \Y $155
+ connect \B $194
+ connect \Y $198
end
process $group_0
assign \en_alu0 1'0
- assign \en_alu0 $155
+ assign \en_alu0 $198
sync init
end
process $group_1
assign \oper_i__insn_type 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__insn_type \insn_type
end
end
process $group_2
assign \fus_oper_i__fn_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \fus_oper_i__fn_unit \fn_unit
end
process $group_3
assign \fus_oper_i__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fus_oper_i__imm_data__imm_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign { \fus_oper_i__imm_data__imm_ok \fus_oper_i__imm_data__imm } { \imm_ok \imm }
end
end
process $group_5
assign \oper_i__lk 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__lk \lk
end
process $group_6
assign \fus_oper_i__rc__rc 1'0
assign \fus_oper_i__rc__rc_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign { \fus_oper_i__rc__rc_ok \fus_oper_i__rc__rc } { \rc_ok \rc }
end
process $group_8
assign \fus_oper_i__oe__oe 1'0
assign \fus_oper_i__oe__oe_ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign { \fus_oper_i__oe__oe_ok \fus_oper_i__oe__oe } { \oe_ok \oe }
end
end
process $group_10
assign \oper_i__invert_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__invert_a \invert_a
end
end
process $group_11
assign \fus_oper_i__zero_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \fus_oper_i__zero_a \zero_a
end
end
process $group_12
assign \oper_i__invert_out 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__invert_out \invert_out
end
process $group_13
assign \fus_oper_i__write_cr__data 3'000
assign \fus_oper_i__write_cr__ok 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign { \fus_oper_i__write_cr__ok \fus_oper_i__write_cr__data } { \cr_out_ok \cr_out }
end
end
process $group_15
assign \oper_i__input_carry 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__input_carry \input_carry
end
end
process $group_16
assign \oper_i__output_carry 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__output_carry \output_carry
end
end
process $group_17
assign \oper_i__input_cr 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__input_cr \input_cr
end
end
process $group_18
assign \oper_i__output_cr 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__output_cr \output_cr
end
end
process $group_19
assign \oper_i__is_32bit 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__is_32bit \is_32bit
end
end
process $group_20
assign \oper_i__is_signed 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__is_signed \is_signed
end
end
process $group_21
assign \oper_i__data_len 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__data_len \data_len
end
end
process $group_22
assign \fus_oper_i__insn 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \fus_oper_i__insn \insn
end
end
process $group_23
assign \oper_i__byte_reverse 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__byte_reverse \byte_reverse
end
end
process $group_24
assign \oper_i__sign_extend 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__sign_extend \sign_extend
end
end
process $group_25
assign \issue_i$1 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \issue_i$1 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_cr0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_branch0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
+ wire width 1 \en_trap0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_logical0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_shiftrot0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:110"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
wire width 1 \en_ldst0
process $group_26
assign \corebusy_o 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \corebusy_o \busy_o
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \corebusy_o \busy_o$4
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \corebusy_o \busy_o$12
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \corebusy_o \busy_o$18
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \corebusy_o \busy_o$24
+ assign \corebusy_o \busy_o$30
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \corebusy_o \busy_o$33
+ assign \corebusy_o \busy_o$39
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \corebusy_o \busy_o$41
+ assign \corebusy_o \busy_o$47
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 4 $157
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:71"
- wire width 1 $158
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:71"
- cell $and $159
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 4 $200
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
+ wire width 1 $201
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
+ cell $and $202
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $158
+ connect \Y $201
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $160
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $161
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ wire width 1 $203
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ cell $eq $204
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $160
+ connect \Y $203
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $162
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $205
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A { $160 $158 \reg2_ok \reg1_ok }
- connect \Y $157
+ connect \A { $203 $201 \reg2_ok \reg1_ok }
+ connect \Y $200
end
process $group_27
assign \fus_rdmaskn 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_alu0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn $157
+ assign \fus_rdmaskn $200
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:102"
- wire width 6 \fu_enable
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104"
+ wire width 7 \fu_enable
process $group_28
- assign \fu_enable 6'000000
+ assign \fu_enable 7'0000000
assign \fu_enable [0] \en_alu0
assign \fu_enable [1] \en_cr0
assign \fu_enable [2] \en_branch0
- assign \fu_enable [3] \en_logical0
- assign \fu_enable [4] \en_shiftrot0
- assign \fu_enable [5] \en_ldst0
+ assign \fu_enable [3] \en_trap0
+ assign \fu_enable [4] \en_logical0
+ assign \fu_enable [5] \en_shiftrot0
+ assign \fu_enable [6] \en_ldst0
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $163
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $164
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $165
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $206
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $207
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $208
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 7'1000000
- connect \Y $164
+ connect \Y $207
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $166
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $209
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $164
- connect \Y $163
+ connect \A $207
+ connect \Y $206
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $167
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $168
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $210
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $163
- connect \Y $167
+ connect \B $206
+ connect \Y $210
end
process $group_29
assign \en_cr0 1'0
- assign \en_cr0 $167
+ assign \en_cr0 $210
sync init
end
process $group_30
assign \oper_i__insn_type$2 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__insn_type$2 \insn_type
end
end
process $group_31
assign \oper_i__fn_unit 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__fn_unit \fn_unit
end
end
process $group_32
assign \oper_i__insn 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__insn \insn
end
end
process $group_33
assign \oper_i__read_cr_whole 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__read_cr_whole \read_cr_whole
end
end
process $group_34
assign \oper_i__write_cr_whole 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__write_cr_whole \write_cr_whole
end
end
process $group_35
assign \issue_i$3 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \issue_i$3 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 6 $169
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $170
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 6 $212
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $213
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A { \cr_in2_ok$5 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
- connect \Y $169
+ connect \Y $212
end
process $group_36
- assign \fus_rdmaskn$91 6'000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ assign \fus_rdmaskn$119 6'000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_cr0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn$91 $169
+ assign \fus_rdmaskn$119 $212
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $171
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $172
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $173
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $214
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $215
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $216
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 6'100000
- connect \Y $172
+ connect \Y $215
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $174
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $217
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $172
- connect \Y $171
+ connect \A $215
+ connect \Y $214
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $175
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $176
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $218
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $171
- connect \Y $175
+ connect \B $214
+ connect \Y $218
end
process $group_37
assign \en_branch0 1'0
- assign \en_branch0 $175
+ assign \en_branch0 $218
sync init
end
process $group_38
assign \oper_i__insn_type$6 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__insn_type$6 \insn_type
end
end
process $group_39
assign \oper_i__fn_unit$7 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__fn_unit$7 \fn_unit
end
sync init
end
process $group_40
- assign \fus_oper_i__imm_data__imm$92 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$93 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ assign \fus_oper_i__imm_data__imm$120 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$121 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$93 \fus_oper_i__imm_data__imm$92 } { \imm_ok \imm }
+ assign { \fus_oper_i__imm_data__imm_ok$121 \fus_oper_i__imm_data__imm$120 } { \imm_ok \imm }
end
sync init
end
process $group_42
assign \oper_i__lk$8 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__lk$8 \lk
end
end
process $group_43
assign \oper_i__is_32bit$9 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__is_32bit$9 \is_32bit
end
end
process $group_44
assign \oper_i__insn$10 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__insn$10 \insn
end
end
process $group_45
assign \issue_i$11 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \issue_i$11 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 4 $177
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $178
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 4 $220
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $221
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A { 1'1 \cr_in1_ok \fast2_ok \fast1_ok }
- connect \Y $177
+ connect \Y $220
end
process $group_46
- assign \fus_rdmaskn$94 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ assign \fus_rdmaskn$122 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_branch0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn$94 $177
+ assign \fus_rdmaskn$122 $220
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $179
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $180
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $181
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $222
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $223
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $224
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 10
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 10
+ connect \A \fn_unit
+ connect \B 8'10000000
+ connect \Y $223
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $225
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 10
+ parameter \Y_WIDTH 1
+ connect \A $223
+ connect \Y $222
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $226
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $227
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \valid
+ connect \B $222
+ connect \Y $226
+ end
+ process $group_47
+ assign \en_trap0 1'0
+ assign \en_trap0 $226
+ sync init
+ end
+ process $group_48
+ assign \oper_i__insn_type$13 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__insn_type$13 \insn_type
+ end
+ sync init
+ end
+ process $group_49
+ assign \oper_i__fn_unit$14 10'0000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__fn_unit$14 \fn_unit
+ end
+ sync init
+ end
+ process $group_50
+ assign \oper_i__insn$15 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__insn$15 \insn
+ end
+ sync init
+ end
+ process $group_51
+ assign \oper_i__is_32bit$16 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__is_32bit$16 \is_32bit
+ end
+ sync init
+ end
+ process $group_52
+ assign \oper_i__traptype 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__traptype \traptype
+ end
+ sync init
+ end
+ process $group_53
+ assign \oper_i__trapaddr 13'0000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \oper_i__trapaddr \trapaddr
+ end
+ sync init
+ end
+ process $group_54
+ assign \issue_i$17 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \issue_i$17 \issue_i
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 6 $228
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $229
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A { 1'1 1'1 \fast2_ok \fast1_ok \reg2_ok \reg1_ok }
+ connect \Y $228
+ end
+ process $group_55
+ assign \fus_rdmaskn$123 6'000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ switch { \en_trap0 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
+ case 1'1
+ assign \fus_rdmaskn$123 $228
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $230
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $231
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $232
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 5'10000
- connect \Y $180
+ connect \Y $231
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $182
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $233
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $180
- connect \Y $179
+ connect \A $231
+ connect \Y $230
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $183
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $184
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $234
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $235
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $179
- connect \Y $183
+ connect \B $230
+ connect \Y $234
end
- process $group_47
+ process $group_56
assign \en_logical0 1'0
- assign \en_logical0 $183
+ assign \en_logical0 $234
sync init
end
- process $group_48
- assign \oper_i__insn_type$13 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_57
+ assign \oper_i__insn_type$19 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__insn_type$13 \insn_type
+ assign \oper_i__insn_type$19 \insn_type
end
sync init
end
- process $group_49
- assign \oper_i__fn_unit$14 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_58
+ assign \oper_i__fn_unit$20 10'0000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__fn_unit$14 \fn_unit
+ assign \oper_i__fn_unit$20 \fn_unit
end
sync init
end
- process $group_50
- assign \fus_oper_i__imm_data__imm$95 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$96 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_59
+ assign \fus_oper_i__imm_data__imm$124 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$125 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$96 \fus_oper_i__imm_data__imm$95 } { \imm_ok \imm }
+ assign { \fus_oper_i__imm_data__imm_ok$125 \fus_oper_i__imm_data__imm$124 } { \imm_ok \imm }
end
sync init
end
- process $group_52
- assign \oper_i__lk$15 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_61
+ assign \oper_i__lk$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__lk$15 \lk
+ assign \oper_i__lk$21 \lk
end
sync init
end
- process $group_53
- assign \fus_oper_i__rc__rc$97 1'0
- assign \fus_oper_i__rc__rc_ok$98 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_62
+ assign \fus_oper_i__rc__rc$126 1'0
+ assign \fus_oper_i__rc__rc_ok$127 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__rc__rc_ok$98 \fus_oper_i__rc__rc$97 } { \rc_ok \rc }
+ assign { \fus_oper_i__rc__rc_ok$127 \fus_oper_i__rc__rc$126 } { \rc_ok \rc }
end
sync init
end
- process $group_55
- assign \fus_oper_i__oe__oe$99 1'0
- assign \fus_oper_i__oe__oe_ok$100 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_64
+ assign \fus_oper_i__oe__oe$128 1'0
+ assign \fus_oper_i__oe__oe_ok$129 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__oe__oe_ok$100 \fus_oper_i__oe__oe$99 } { \oe_ok \oe }
+ assign { \fus_oper_i__oe__oe_ok$129 \fus_oper_i__oe__oe$128 } { \oe_ok \oe }
end
sync init
end
- process $group_57
- assign \oper_i__invert_a$16 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_66
+ assign \oper_i__invert_a$22 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__invert_a$16 \invert_a
+ assign \oper_i__invert_a$22 \invert_a
end
sync init
end
- process $group_58
- assign \fus_oper_i__zero_a$101 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_67
+ assign \fus_oper_i__zero_a$130 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_oper_i__zero_a$101 \zero_a
+ assign \fus_oper_i__zero_a$130 \zero_a
end
sync init
end
- process $group_59
- assign \oper_i__input_carry$17 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_68
+ assign \oper_i__input_carry$23 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__input_carry$17 \input_carry
+ assign \oper_i__input_carry$23 \input_carry
end
sync init
end
- process $group_60
- assign \oper_i__invert_out$18 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_69
+ assign \oper_i__invert_out$24 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__invert_out$18 \invert_out
+ assign \oper_i__invert_out$24 \invert_out
end
sync init
end
- process $group_61
- assign \fus_oper_i__write_cr__data$102 3'000
- assign \fus_oper_i__write_cr__ok$103 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_70
+ assign \fus_oper_i__write_cr__data$131 3'000
+ assign \fus_oper_i__write_cr__ok$132 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__write_cr__ok$103 \fus_oper_i__write_cr__data$102 } { \cr_out_ok \cr_out }
+ assign { \fus_oper_i__write_cr__ok$132 \fus_oper_i__write_cr__data$131 } { \cr_out_ok \cr_out }
end
sync init
end
- process $group_63
- assign \oper_i__output_carry$19 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_72
+ assign \oper_i__output_carry$25 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__output_carry$19 \output_carry
+ assign \oper_i__output_carry$25 \output_carry
end
sync init
end
- process $group_64
- assign \oper_i__is_32bit$20 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_73
+ assign \oper_i__is_32bit$26 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_32bit$20 \is_32bit
+ assign \oper_i__is_32bit$26 \is_32bit
end
sync init
end
- process $group_65
- assign \oper_i__is_signed$21 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_74
+ assign \oper_i__is_signed$27 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_signed$21 \is_signed
+ assign \oper_i__is_signed$27 \is_signed
end
sync init
end
- process $group_66
- assign \oper_i__data_len$22 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_75
+ assign \oper_i__data_len$28 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__data_len$22 \data_len
+ assign \oper_i__data_len$28 \data_len
end
sync init
end
- process $group_67
- assign \fus_oper_i__insn$104 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_76
+ assign \fus_oper_i__insn$133 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_oper_i__insn$104 \insn
+ assign \fus_oper_i__insn$133 \insn
end
sync init
end
- process $group_68
- assign \issue_i$23 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_77
+ assign \issue_i$29 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \issue_i$23 \issue_i
+ assign \issue_i$29 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 2 $185
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $186
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 2 $236
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $237
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A { \reg2_ok \reg1_ok }
- connect \Y $185
+ connect \Y $236
end
- process $group_69
- assign \fus_rdmaskn$105 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_78
+ assign \fus_rdmaskn$134 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_logical0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn$105 $185
+ assign \fus_rdmaskn$134 $236
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $187
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $188
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $189
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $238
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $239
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $240
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 4'1000
- connect \Y $188
+ connect \Y $239
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $190
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $241
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $188
- connect \Y $187
+ connect \A $239
+ connect \Y $238
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $191
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $192
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $242
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $243
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $187
- connect \Y $191
+ connect \B $238
+ connect \Y $242
end
- process $group_70
+ process $group_79
assign \en_shiftrot0 1'0
- assign \en_shiftrot0 $191
+ assign \en_shiftrot0 $242
sync init
end
- process $group_71
- assign \oper_i__insn_type$25 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_80
+ assign \oper_i__insn_type$31 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__insn_type$25 \insn_type
+ assign \oper_i__insn_type$31 \insn_type
end
sync init
end
- process $group_72
- assign \fus_oper_i__fn_unit$106 10'0000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_81
+ assign \fus_oper_i__fn_unit$135 10'0000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_oper_i__fn_unit$106 \fn_unit
+ assign \fus_oper_i__fn_unit$135 \fn_unit
end
sync init
end
- process $group_73
- assign \fus_oper_i__imm_data__imm$107 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$108 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_82
+ assign \fus_oper_i__imm_data__imm$136 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$137 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$108 \fus_oper_i__imm_data__imm$107 } { \imm_ok \imm }
+ assign { \fus_oper_i__imm_data__imm_ok$137 \fus_oper_i__imm_data__imm$136 } { \imm_ok \imm }
end
sync init
end
- process $group_75
- assign \fus_oper_i__rc__rc$109 1'0
- assign \fus_oper_i__rc__rc_ok$110 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_84
+ assign \fus_oper_i__rc__rc$138 1'0
+ assign \fus_oper_i__rc__rc_ok$139 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__rc__rc_ok$110 \fus_oper_i__rc__rc$109 } { \rc_ok \rc }
+ assign { \fus_oper_i__rc__rc_ok$139 \fus_oper_i__rc__rc$138 } { \rc_ok \rc }
end
sync init
end
- process $group_77
- assign \fus_oper_i__oe__oe$111 1'0
- assign \fus_oper_i__oe__oe_ok$112 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_86
+ assign \fus_oper_i__oe__oe$140 1'0
+ assign \fus_oper_i__oe__oe_ok$141 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__oe__oe_ok$112 \fus_oper_i__oe__oe$111 } { \oe_ok \oe }
+ assign { \fus_oper_i__oe__oe_ok$141 \fus_oper_i__oe__oe$140 } { \oe_ok \oe }
end
sync init
end
- process $group_79
- assign \fus_oper_i__write_cr__data$113 3'000
- assign \fus_oper_i__write_cr__ok$114 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_88
+ assign \fus_oper_i__write_cr__data$142 3'000
+ assign \fus_oper_i__write_cr__ok$143 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__write_cr__ok$114 \fus_oper_i__write_cr__data$113 } { \cr_out_ok \cr_out }
+ assign { \fus_oper_i__write_cr__ok$143 \fus_oper_i__write_cr__data$142 } { \cr_out_ok \cr_out }
end
sync init
end
- process $group_81
- assign \oper_i__input_carry$26 2'00
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_90
+ assign \oper_i__input_carry$32 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__input_carry$26 \input_carry
+ assign \oper_i__input_carry$32 \input_carry
end
sync init
end
- process $group_82
- assign \oper_i__output_carry$27 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_91
+ assign \oper_i__output_carry$33 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__output_carry$27 \output_carry
+ assign \oper_i__output_carry$33 \output_carry
end
sync init
end
- process $group_83
- assign \oper_i__input_cr$28 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_92
+ assign \oper_i__input_cr$34 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__input_cr$28 \input_cr
+ assign \oper_i__input_cr$34 \input_cr
end
sync init
end
- process $group_84
- assign \oper_i__output_cr$29 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_93
+ assign \oper_i__output_cr$35 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__output_cr$29 \output_cr
+ assign \oper_i__output_cr$35 \output_cr
end
sync init
end
- process $group_85
- assign \oper_i__is_32bit$30 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_94
+ assign \oper_i__is_32bit$36 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_32bit$30 \is_32bit
+ assign \oper_i__is_32bit$36 \is_32bit
end
sync init
end
- process $group_86
- assign \oper_i__is_signed$31 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_95
+ assign \oper_i__is_signed$37 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_signed$31 \is_signed
+ assign \oper_i__is_signed$37 \is_signed
end
sync init
end
- process $group_87
- assign \fus_oper_i__insn$115 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_96
+ assign \fus_oper_i__insn$144 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_oper_i__insn$115 \insn
+ assign \fus_oper_i__insn$144 \insn
end
sync init
end
- process $group_88
- assign \issue_i$32 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_97
+ assign \issue_i$38 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \issue_i$32 \issue_i
+ assign \issue_i$38 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 4 $193
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $194
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $195
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 4 $244
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ wire width 1 $245
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ cell $eq $246
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $194
+ connect \Y $245
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $196
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $247
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A { $194 \reg3_ok \reg2_ok \reg1_ok }
- connect \Y $193
+ connect \A { $245 \reg3_ok \reg2_ok \reg1_ok }
+ connect \Y $244
end
- process $group_89
- assign \fus_rdmaskn$116 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_98
+ assign \fus_rdmaskn$145 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_shiftrot0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn$116 $193
+ assign \fus_rdmaskn$145 $244
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $197
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 10 $198
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $199
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $248
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 10 $249
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $250
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 10
connect \A \fn_unit
connect \B 3'100
- connect \Y $198
+ connect \Y $249
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $reduce_bool $200
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $reduce_bool $251
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \Y_WIDTH 1
- connect \A $198
- connect \Y $197
+ connect \A $249
+ connect \Y $248
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- wire width 1 $201
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:111"
- cell $and $202
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ wire width 1 $252
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ cell $and $253
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \valid
- connect \B $197
- connect \Y $201
+ connect \B $248
+ connect \Y $252
end
- process $group_90
+ process $group_99
assign \en_ldst0 1'0
- assign \en_ldst0 $201
+ assign \en_ldst0 $252
sync init
end
- process $group_91
- assign \oper_i__insn_type$34 7'0000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_100
+ assign \oper_i__insn_type$40 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__insn_type$34 \insn_type
+ assign \oper_i__insn_type$40 \insn_type
end
sync init
end
- process $group_92
- assign \fus_oper_i__imm_data__imm$117 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$118 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_101
+ assign \fus_oper_i__imm_data__imm$146 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$147 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$118 \fus_oper_i__imm_data__imm$117 } { \imm_ok \imm }
+ assign { \fus_oper_i__imm_data__imm_ok$147 \fus_oper_i__imm_data__imm$146 } { \imm_ok \imm }
end
sync init
end
- process $group_94
+ process $group_103
assign \oper_i__zero_a 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__zero_a \zero_a
end
sync init
end
- process $group_95
- assign \oper_i__is_32bit$35 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_104
+ assign \oper_i__is_32bit$41 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_32bit$35 \is_32bit
+ assign \oper_i__is_32bit$41 \is_32bit
end
sync init
end
- process $group_96
- assign \oper_i__is_signed$36 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_105
+ assign \oper_i__is_signed$42 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__is_signed$36 \is_signed
+ assign \oper_i__is_signed$42 \is_signed
end
sync init
end
- process $group_97
- assign \oper_i__data_len$37 4'0000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_106
+ assign \oper_i__data_len$43 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__data_len$37 \data_len
+ assign \oper_i__data_len$43 \data_len
end
sync init
end
- process $group_98
- assign \oper_i__byte_reverse$38 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_107
+ assign \oper_i__byte_reverse$44 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__byte_reverse$38 \byte_reverse
+ assign \oper_i__byte_reverse$44 \byte_reverse
end
sync init
end
- process $group_99
- assign \oper_i__sign_extend$39 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_108
+ assign \oper_i__sign_extend$45 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \oper_i__sign_extend$39 \sign_extend
+ assign \oper_i__sign_extend$45 \sign_extend
end
sync init
end
- process $group_100
+ process $group_109
assign \oper_i__update 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
assign \oper_i__update \update
end
sync init
end
- process $group_101
- assign \issue_i$40 1'0
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_110
+ assign \issue_i$46 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \issue_i$40 \issue_i
+ assign \issue_i$46 \issue_i
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- wire width 3 $203
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:117"
- cell $not $204
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ wire width 3 $254
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119"
+ cell $not $255
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A { \reg3_ok \reg2_ok \reg1_ok }
- connect \Y $203
+ connect \Y $254
end
- process $group_102
- assign \fus_rdmaskn$119 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ process $group_111
+ assign \fus_rdmaskn$148 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
switch { \en_ldst0 }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114"
case 1'1
- assign \fus_rdmaskn$119 $203
+ assign \fus_rdmaskn$148 $254
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_INT_ra
- process $group_103
+ process $group_112
assign \rdflag_INT_ra 1'0
assign \rdflag_INT_ra \reg1_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:47"
- wire width 32 $205
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:47"
- cell $sshl $206
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47"
+ wire width 32 $256
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47"
+ cell $sshl $257
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg1
- connect \Y $205
+ connect \Y $256
end
- process $group_104
+ process $group_113
assign \int_src1__ren 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_INT_ra_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \int_src1__ren $205
+ assign \int_src1__ren $256
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $207
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $208
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $258
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $259
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [0]
connect \B \fu_enable [0]
- connect \Y $207
+ connect \Y $258
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $209
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $210
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $261
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $207
+ connect \A $258
connect \B \rdflag_INT_ra
- connect \Y $209
+ connect \Y $260
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $211
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $212
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $262
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $263
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [0]
+ connect \A \rd__rel$48 [0]
connect \B \fu_enable [1]
- connect \Y $211
+ connect \Y $262
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $213
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $214
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $264
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $265
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $211
+ connect \A $262
connect \B \rdflag_INT_ra
- connect \Y $213
+ connect \Y $264
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $215
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $216
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $266
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$45 [0]
+ connect \A \rd__rel$51 [0]
connect \B \fu_enable [3]
- connect \Y $215
+ connect \Y $266
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $217
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $218
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $268
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $215
+ connect \A $266
connect \B \rdflag_INT_ra
- connect \Y $217
+ connect \Y $268
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $219
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $220
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $270
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$48 [0]
+ connect \A \rd__rel$54 [0]
connect \B \fu_enable [4]
- connect \Y $219
+ connect \Y $270
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $221
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $222
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $272
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $273
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $219
+ connect \A $270
connect \B \rdflag_INT_ra
- connect \Y $221
+ connect \Y $272
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $223
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $224
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $274
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $275
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$51 [0]
+ connect \A \rd__rel$57 [0]
connect \B \fu_enable [5]
- connect \Y $223
+ connect \Y $274
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $225
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $226
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $276
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $277
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $223
+ connect \A $274
connect \B \rdflag_INT_ra
- connect \Y $225
+ connect \Y $276
end
- process $group_105
- assign \rdpick_INT_ra_i 5'00000
- assign \rdpick_INT_ra_i [0] $209
- assign \rdpick_INT_ra_i [1] $213
- assign \rdpick_INT_ra_i [2] $217
- assign \rdpick_INT_ra_i [3] $221
- assign \rdpick_INT_ra_i [4] $225
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $279
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$60 [0]
+ connect \B \fu_enable [6]
+ connect \Y $278
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $280
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $281
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $278
+ connect \B \rdflag_INT_ra
+ connect \Y $280
+ end
+ process $group_114
+ assign \rdpick_INT_ra_i 6'000000
+ assign \rdpick_INT_ra_i [0] $260
+ assign \rdpick_INT_ra_i [1] $264
+ assign \rdpick_INT_ra_i [2] $268
+ assign \rdpick_INT_ra_i [3] $272
+ assign \rdpick_INT_ra_i [4] $276
+ assign \rdpick_INT_ra_i [5] $280
sync init
end
- process $group_106
+ process $group_115
assign \rd__go 4'0000
assign \rd__go [0] \rdpick_INT_ra_o [0]
assign \rd__go [1] \rdpick_INT_rb_o [0]
assign \rd__go [3] \rdpick_XER_xer_ca_o [0]
sync init
end
- process $group_107
+ process $group_116
assign \src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src1_i \int_src1__data_o
sync init
end
- process $group_108
- assign \rd__go$43 6'000000
- assign \rd__go$43 [0] \rdpick_INT_ra_o [1]
- assign \rd__go$43 [1] \rdpick_INT_rb_o [1]
- assign \rd__go$43 [2] \rdpick_CR_full_cr_o
- assign \rd__go$43 [3] \rdpick_CR_cr_a_o [0]
- assign \rd__go$43 [4] \rdpick_CR_cr_b_o
- assign \rd__go$43 [5] \rdpick_CR_cr_c_o
+ process $group_117
+ assign \rd__go$49 6'000000
+ assign \rd__go$49 [0] \rdpick_INT_ra_o [1]
+ assign \rd__go$49 [1] \rdpick_INT_rb_o [1]
+ assign \rd__go$49 [2] \rdpick_CR_full_cr_o
+ assign \rd__go$49 [3] \rdpick_CR_cr_a_o [0]
+ assign \rd__go$49 [4] \rdpick_CR_cr_b_o
+ assign \rd__go$49 [5] \rdpick_CR_cr_c_o
sync init
end
- process $group_109
- assign \src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$44 \int_src1__data_o
+ process $group_118
+ assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$50 \int_src1__data_o
sync init
end
- process $group_110
- assign \rd__go$46 2'00
- assign \rd__go$46 [0] \rdpick_INT_ra_o [2]
- assign \rd__go$46 [1] \rdpick_INT_rb_o [2]
+ process $group_119
+ assign \rd__go$52 6'000000
+ assign \rd__go$52 [0] \rdpick_INT_ra_o [2]
+ assign \rd__go$52 [1] \rdpick_INT_rb_o [2]
+ assign \rd__go$52 [2] \rdpick_FAST_spr1_o [1]
+ assign \rd__go$52 [3] \rdpick_FAST_spr2_o [1]
+ assign \rd__go$52 [4] \rdpick_FAST_cia_o [1]
+ assign \rd__go$52 [5] \rdpick_FAST_msr_o
sync init
end
- process $group_111
- assign \src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$47 \int_src1__data_o
+ process $group_120
+ assign \src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$53 \int_src1__data_o
sync init
end
- process $group_112
- assign \rd__go$49 4'0000
- assign \rd__go$49 [0] \rdpick_INT_ra_o [3]
- assign \rd__go$49 [1] \rdpick_INT_rb_o [3]
- assign \rd__go$49 [2] \rdpick_INT_rc_o [0]
- assign \rd__go$49 [3] \rdpick_XER_xer_ca_o [1]
+ process $group_121
+ assign \rd__go$55 2'00
+ assign \rd__go$55 [0] \rdpick_INT_ra_o [3]
+ assign \rd__go$55 [1] \rdpick_INT_rb_o [3]
sync init
end
- process $group_113
- assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$50 \int_src1__data_o
+ process $group_122
+ assign \src1_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$56 \int_src1__data_o
sync init
end
- process $group_114
- assign \rd__go$52 3'000
- assign \rd__go$52 [0] \rdpick_INT_ra_o [4]
- assign \rd__go$52 [1] \rdpick_INT_rb_o [4]
- assign \rd__go$52 [2] \rdpick_INT_rc_o [1]
+ process $group_123
+ assign \rd__go$58 4'0000
+ assign \rd__go$58 [0] \rdpick_INT_ra_o [4]
+ assign \rd__go$58 [1] \rdpick_INT_rb_o [4]
+ assign \rd__go$58 [2] \rdpick_INT_rc_o [0]
+ assign \rd__go$58 [3] \rdpick_XER_xer_ca_o [1]
sync init
end
- process $group_115
- assign \src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$53 \int_src1__data_o
+ process $group_124
+ assign \src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$59 \int_src1__data_o
+ sync init
+ end
+ process $group_125
+ assign \rd__go$61 3'000
+ assign \rd__go$61 [0] \rdpick_INT_ra_o [5]
+ assign \rd__go$61 [1] \rdpick_INT_rb_o [5]
+ assign \rd__go$61 [2] \rdpick_INT_rc_o [1]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ process $group_126
+ assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$62 \int_src1__data_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_INT_rb
- process $group_116
+ process $group_127
assign \rdflag_INT_rb 1'0
assign \rdflag_INT_rb \reg2_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:49"
- wire width 32 $227
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:49"
- cell $sshl $228
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49"
+ wire width 32 $282
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49"
+ cell $sshl $283
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg2
- connect \Y $227
+ connect \Y $282
end
- process $group_117
+ process $group_128
assign \int_src2__ren 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_INT_rb_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \int_src2__ren $227
+ assign \int_src2__ren $282
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $229
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $230
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $284
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $285
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [1]
connect \B \fu_enable [0]
- connect \Y $229
+ connect \Y $284
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $231
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $232
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $286
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $287
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $229
+ connect \A $284
connect \B \rdflag_INT_rb
- connect \Y $231
+ connect \Y $286
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $233
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $234
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $288
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $289
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [1]
+ connect \A \rd__rel$48 [1]
connect \B \fu_enable [1]
- connect \Y $233
+ connect \Y $288
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $235
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $236
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $290
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $233
+ connect \A $288
connect \B \rdflag_INT_rb
- connect \Y $235
+ connect \Y $290
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $237
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $238
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $292
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $293
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$45 [1]
+ connect \A \rd__rel$51 [1]
connect \B \fu_enable [3]
- connect \Y $237
+ connect \Y $292
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $239
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $240
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $295
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $237
+ connect \A $292
connect \B \rdflag_INT_rb
- connect \Y $239
+ connect \Y $294
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $241
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $242
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $296
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $297
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$48 [1]
+ connect \A \rd__rel$54 [1]
connect \B \fu_enable [4]
- connect \Y $241
+ connect \Y $296
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $243
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $244
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $298
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $299
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $241
+ connect \A $296
connect \B \rdflag_INT_rb
- connect \Y $243
+ connect \Y $298
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $245
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $246
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$51 [1]
+ connect \A \rd__rel$57 [1]
connect \B \fu_enable [5]
- connect \Y $245
+ connect \Y $300
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $247
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $248
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $302
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $303
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $245
+ connect \A $300
connect \B \rdflag_INT_rb
- connect \Y $247
+ connect \Y $302
end
- process $group_118
- assign \rdpick_INT_rb_i 5'00000
- assign \rdpick_INT_rb_i [0] $231
- assign \rdpick_INT_rb_i [1] $235
- assign \rdpick_INT_rb_i [2] $239
- assign \rdpick_INT_rb_i [3] $243
- assign \rdpick_INT_rb_i [4] $247
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $305
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$60 [1]
+ connect \B \fu_enable [6]
+ connect \Y $304
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $307
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $304
+ connect \B \rdflag_INT_rb
+ connect \Y $306
+ end
+ process $group_129
+ assign \rdpick_INT_rb_i 6'000000
+ assign \rdpick_INT_rb_i [0] $286
+ assign \rdpick_INT_rb_i [1] $290
+ assign \rdpick_INT_rb_i [2] $294
+ assign \rdpick_INT_rb_i [3] $298
+ assign \rdpick_INT_rb_i [4] $302
+ assign \rdpick_INT_rb_i [5] $306
sync init
end
- process $group_119
+ process $group_130
assign \src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src2_i \int_src2__data_o
sync init
end
- process $group_120
- assign \src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$54 \int_src2__data_o
+ process $group_131
+ assign \src2_i$63 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$63 \int_src2__data_o
sync init
end
- process $group_121
- assign \src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$55 \int_src2__data_o
+ process $group_132
+ assign \src2_i$64 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$64 \int_src2__data_o
sync init
end
- process $group_122
- assign \src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$56 \int_src2__data_o
+ process $group_133
+ assign \src2_i$65 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$65 \int_src2__data_o
sync init
end
- process $group_123
- assign \src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$57 \int_src2__data_o
+ process $group_134
+ assign \src2_i$66 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$66 \int_src2__data_o
+ sync init
+ end
+ process $group_135
+ assign \src2_i$67 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$67 \int_src2__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_INT_rc
- process $group_124
+ process $group_136
assign \rdflag_INT_rc 1'0
assign \rdflag_INT_rc \reg3_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $249
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $250
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+ wire width 32 $308
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+ cell $sshl $309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg3
- connect \Y $249
+ connect \Y $308
end
- process $group_125
+ process $group_137
assign \int_src3__ren 32'00000000000000000000000000000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_INT_rc_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \int_src3__ren $249
+ assign \int_src3__ren $308
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $251
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $252
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $310
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $311
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$48 [2]
- connect \B \fu_enable [4]
- connect \Y $251
+ connect \A \rd__rel$57 [2]
+ connect \B \fu_enable [5]
+ connect \Y $310
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $253
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $254
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $313
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $251
+ connect \A $310
connect \B \rdflag_INT_rc
- connect \Y $253
+ connect \Y $312
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $255
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $256
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$51 [2]
- connect \B \fu_enable [5]
- connect \Y $255
+ connect \A \rd__rel$60 [2]
+ connect \B \fu_enable [6]
+ connect \Y $314
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $257
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $258
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $317
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $255
+ connect \A $314
connect \B \rdflag_INT_rc
- connect \Y $257
+ connect \Y $316
end
- process $group_126
+ process $group_138
assign \rdpick_INT_rc_i 2'00
- assign \rdpick_INT_rc_i [0] $253
- assign \rdpick_INT_rc_i [1] $257
+ assign \rdpick_INT_rc_i [0] $312
+ assign \rdpick_INT_rc_i [1] $316
sync init
end
- process $group_127
+ process $group_139
assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fus_src3_i \int_src3__data_o
sync init
end
- process $group_128
+ process $group_140
assign \src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src3_i \int_src3__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_XER_xer_so
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:71"
- wire width 1 $259
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:71"
- cell $and $260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
+ wire width 1 $318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
+ cell $and $319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $259
+ connect \Y $318
end
- process $group_129
+ process $group_141
assign \rdflag_XER_xer_so 1'0
- assign \rdflag_XER_xer_so $259
+ assign \rdflag_XER_xer_so $318
sync init
end
- process $group_130
+ process $group_142
assign \xer_src1__ren 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_XER_xer_so_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
assign \xer_src1__ren 3'001
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $261
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $262
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $321
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [2]
connect \B \fu_enable [0]
- connect \Y $261
+ connect \Y $320
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $263
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $264
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $261
+ connect \A $320
connect \B \rdflag_XER_xer_so
- connect \Y $263
+ connect \Y $322
end
- process $group_131
+ process $group_143
assign \rdpick_XER_xer_so_i 1'0
- assign \rdpick_XER_xer_so_i $263
+ assign \rdpick_XER_xer_so_i $322
sync init
end
- process $group_132
- assign \fus_src3_i$120 1'0
- assign \fus_src3_i$120 \xer_src1__data_o [0]
+ process $group_144
+ assign \fus_src3_i$149 1'0
+ assign \fus_src3_i$149 \xer_src1__data_o [0]
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_XER_xer_ca
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $265
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $266
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ wire width 1 $324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
+ cell $eq $325
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $265
+ connect \Y $324
end
- process $group_133
+ process $group_145
assign \rdflag_XER_xer_ca 1'0
- assign \rdflag_XER_xer_ca $265
+ assign \rdflag_XER_xer_ca $324
sync init
end
- process $group_134
+ process $group_146
assign \xer_src2__ren 3'000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_XER_xer_ca_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
assign \xer_src2__ren 3'010
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $267
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $268
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $326
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $327
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [3]
connect \B \fu_enable [0]
- connect \Y $267
+ connect \Y $326
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $269
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $270
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $267
+ connect \A $326
connect \B \rdflag_XER_xer_ca
- connect \Y $269
+ connect \Y $328
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $271
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $272
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $331
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$48 [3]
- connect \B \fu_enable [4]
- connect \Y $271
+ connect \A \rd__rel$57 [3]
+ connect \B \fu_enable [5]
+ connect \Y $330
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $273
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $274
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $271
+ connect \A $330
connect \B \rdflag_XER_xer_ca
- connect \Y $273
+ connect \Y $332
end
- process $group_135
+ process $group_147
assign \rdpick_XER_xer_ca_i 2'00
- assign \rdpick_XER_xer_ca_i [0] $269
- assign \rdpick_XER_xer_ca_i [1] $273
+ assign \rdpick_XER_xer_ca_i [0] $328
+ assign \rdpick_XER_xer_ca_i [1] $332
sync init
end
- process $group_136
+ process $group_148
assign \fus_src4_i 2'00
assign \fus_src4_i \xer_src2__data_o
sync init
end
- process $group_137
- assign \fus_src4_i$121 2'00
- assign \fus_src4_i$121 \xer_src2__data_o
+ process $group_149
+ assign \fus_src4_i$150 2'00
+ assign \fus_src4_i$150 \xer_src2__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_CR_full_cr
- process $group_138
+ process $group_150
assign \rdflag_CR_full_cr 1'0
assign \rdflag_CR_full_cr \read_cr_whole
sync init
end
- process $group_139
+ process $group_151
assign \cr_full_rd__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_CR_full_cr_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
assign \cr_full_rd__ren 8'11111111
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $275
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $276
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $334
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $335
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [2]
+ connect \A \rd__rel$48 [2]
connect \B \fu_enable [1]
- connect \Y $275
+ connect \Y $334
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $277
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $337
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $275
+ connect \A $334
connect \B \rdflag_CR_full_cr
- connect \Y $277
+ connect \Y $336
end
- process $group_140
+ process $group_152
assign \rdpick_CR_full_cr_i 1'0
- assign \rdpick_CR_full_cr_i $277
+ assign \rdpick_CR_full_cr_i $336
sync init
end
- process $group_141
- assign \fus_src3_i$122 32'00000000000000000000000000000000
- assign \fus_src3_i$122 \cr_full_rd__data_o
+ process $group_153
+ assign \fus_src3_i$151 32'00000000000000000000000000000000
+ assign \fus_src3_i$151 \cr_full_rd__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_CR_cr_a
- process $group_142
+ process $group_154
assign \rdflag_CR_cr_a 1'0
assign \rdflag_CR_cr_a \cr_in1_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 16 $279
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 4 $280
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:59"
- cell $sub $281
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
+ wire width 16 $338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
+ wire width 4 $339
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
+ cell $sub $340
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_in1
- connect \Y $280
+ connect \Y $339
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 16 $282
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:59"
- cell $sshl $283
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
+ wire width 16 $341
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
+ cell $sshl $342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $280
- connect \Y $282
+ connect \B $339
+ connect \Y $341
end
- connect $279 $282
- process $group_143
+ connect $338 $341
+ process $group_155
assign \cr_src1__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_CR_cr_a_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \cr_src1__ren $279 [7:0]
+ assign \cr_src1__ren $338 [7:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $284
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $285
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $344
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [3]
+ connect \A \rd__rel$48 [3]
connect \B \fu_enable [1]
- connect \Y $284
+ connect \Y $343
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $286
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $287
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $284
+ connect \A $343
connect \B \rdflag_CR_cr_a
- connect \Y $286
+ connect \Y $345
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $288
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $289
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $347
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $348
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$58 [2]
+ connect \A \rd__rel$68 [2]
connect \B \fu_enable [2]
- connect \Y $288
+ connect \Y $347
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $290
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $291
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $349
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $288
+ connect \A $347
connect \B \rdflag_CR_cr_a
- connect \Y $290
+ connect \Y $349
end
- process $group_144
+ process $group_156
assign \rdpick_CR_cr_a_i 2'00
- assign \rdpick_CR_cr_a_i [0] $286
- assign \rdpick_CR_cr_a_i [1] $290
+ assign \rdpick_CR_cr_a_i [0] $345
+ assign \rdpick_CR_cr_a_i [1] $349
sync init
end
- process $group_145
- assign \fus_src4_i$123 4'0000
- assign \fus_src4_i$123 \cr_src1__data_o
+ process $group_157
+ assign \fus_src4_i$152 4'0000
+ assign \fus_src4_i$152 \cr_src1__data_o
sync init
end
- process $group_146
- assign \rd__go$59 4'0000
- assign \rd__go$59 [2] \rdpick_CR_cr_a_o [1]
- assign \rd__go$59 [0] \rdpick_FAST_spr1_o
- assign \rd__go$59 [1] \rdpick_FAST_spr2_o
- assign \rd__go$59 [3] \rdpick_FAST_cia_o
+ process $group_158
+ assign \rd__go$69 4'0000
+ assign \rd__go$69 [2] \rdpick_CR_cr_a_o [1]
+ assign \rd__go$69 [0] \rdpick_FAST_spr1_o [0]
+ assign \rd__go$69 [1] \rdpick_FAST_spr2_o [0]
+ assign \rd__go$69 [3] \rdpick_FAST_cia_o [0]
sync init
end
- process $group_147
- assign \fus_src3_i$124 4'0000
- assign \fus_src3_i$124 \cr_src1__data_o
+ process $group_159
+ assign \fus_src3_i$153 4'0000
+ assign \fus_src3_i$153 \cr_src1__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_CR_cr_b
- process $group_148
+ process $group_160
assign \rdflag_CR_cr_b 1'0
assign \rdflag_CR_cr_b \cr_in2_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 16 $292
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 4 $293
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:61"
- cell $sub $294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
+ wire width 16 $351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
+ wire width 4 $352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
+ cell $sub $353
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_in2
- connect \Y $293
+ connect \Y $352
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 16 $295
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:61"
- cell $sshl $296
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
+ wire width 16 $354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
+ cell $sshl $355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $293
- connect \Y $295
+ connect \B $352
+ connect \Y $354
end
- connect $292 $295
- process $group_149
+ connect $351 $354
+ process $group_161
assign \cr_src2__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_CR_cr_b_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \cr_src2__ren $292 [7:0]
+ assign \cr_src2__ren $351 [7:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $297
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $298
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [4]
+ connect \A \rd__rel$48 [4]
connect \B \fu_enable [1]
- connect \Y $297
+ connect \Y $356
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $299
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $297
+ connect \A $356
connect \B \rdflag_CR_cr_b
- connect \Y $299
+ connect \Y $358
end
- process $group_150
+ process $group_162
assign \rdpick_CR_cr_b_i 1'0
- assign \rdpick_CR_cr_b_i $299
+ assign \rdpick_CR_cr_b_i $358
sync init
end
- process $group_151
+ process $group_163
assign \fus_src5_i 4'0000
assign \fus_src5_i \cr_src2__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_CR_cr_c
- process $group_152
+ process $group_164
assign \rdflag_CR_cr_c 1'0
assign \rdflag_CR_cr_c \cr_in2_ok$5
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 16 $301
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 4 $302
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:63"
- cell $sub $303
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
+ wire width 16 $360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
+ wire width 4 $361
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
+ cell $sub $362
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 4
connect \A 3'111
- connect \B \cr_in2$60
- connect \Y $302
+ connect \B \cr_in2$70
+ connect \Y $361
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 16 $304
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:63"
- cell $sshl $305
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
+ wire width 16 $363
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
+ cell $sshl $364
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $302
- connect \Y $304
+ connect \B $361
+ connect \Y $363
end
- connect $301 $304
- process $group_153
+ connect $360 $363
+ process $group_165
assign \cr_src3__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_CR_cr_c_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \cr_src3__ren $301 [7:0]
+ assign \cr_src3__ren $360 [7:0]
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $306
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $307
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $365
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$42 [5]
+ connect \A \rd__rel$48 [5]
connect \B \fu_enable [1]
- connect \Y $306
+ connect \Y $365
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $308
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $368
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $306
+ connect \A $365
connect \B \rdflag_CR_cr_c
- connect \Y $308
+ connect \Y $367
end
- process $group_154
+ process $group_166
assign \rdpick_CR_cr_c_i 1'0
- assign \rdpick_CR_cr_c_i $308
+ assign \rdpick_CR_cr_c_i $367
sync init
end
- process $group_155
+ process $group_167
assign \fus_src6_i 4'0000
assign \fus_src6_i \cr_src3__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_FAST_spr1
- process $group_156
+ process $group_168
assign \rdflag_FAST_spr1 1'0
assign \rdflag_FAST_spr1 \fast1_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:92"
- wire width 8 $310
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:92"
- cell $sshl $311
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92"
+ wire width 8 $369
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92"
+ cell $sshl $370
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fast1
- connect \Y $310
+ connect \Y $369
end
- process $group_157
+ process $group_169
assign \fast_src3__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_FAST_spr1_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \fast_src3__ren $310
+ assign \fast_src3__ren $369
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $312
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $313
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $371
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$58 [0]
+ connect \A \rd__rel$68 [0]
connect \B \fu_enable [2]
- connect \Y $312
+ connect \Y $371
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $314
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $315
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $373
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $312
+ connect \A $371
connect \B \rdflag_FAST_spr1
- connect \Y $314
+ connect \Y $373
end
- process $group_158
- assign \rdpick_FAST_spr1_i 1'0
- assign \rdpick_FAST_spr1_i $314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $375
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $376
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$51 [2]
+ connect \B \fu_enable [3]
+ connect \Y $375
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $377
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $378
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $375
+ connect \B \rdflag_FAST_spr1
+ connect \Y $377
+ end
+ process $group_170
+ assign \rdpick_FAST_spr1_i 2'00
+ assign \rdpick_FAST_spr1_i [0] $373
+ assign \rdpick_FAST_spr1_i [1] $377
sync init
end
- process $group_159
- assign \src1_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$61 \fast_src3__data_o
+ process $group_171
+ assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$71 \fast_src3__data_o
+ sync init
+ end
+ process $group_172
+ assign \fus_src3_i$154 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src3_i$154 \fast_src3__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
wire width 1 \rdflag_FAST_spr2
- process $group_160
+ process $group_173
assign \rdflag_FAST_spr2 1'0
assign \rdflag_FAST_spr2 \fast2_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:94"
- wire width 8 $316
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:94"
- cell $sshl $317
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94"
+ wire width 8 $379
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94"
+ cell $sshl $380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fast2
- connect \Y $316
+ connect \Y $379
end
- process $group_161
+ process $group_174
assign \fast_src4__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
switch { \rdpick_FAST_spr2_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \fast_src4__ren $316
+ assign \fast_src4__ren $379
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $318
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $319
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $381
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$58 [1]
+ connect \A \rd__rel$68 [1]
connect \B \fu_enable [2]
- connect \Y $318
+ connect \Y $381
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $320
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $321
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $383
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $384
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $318
+ connect \A $381
connect \B \rdflag_FAST_spr2
- connect \Y $320
+ connect \Y $383
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $385
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $386
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$51 [3]
+ connect \B \fu_enable [3]
+ connect \Y $385
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $387
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $388
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $385
+ connect \B \rdflag_FAST_spr2
+ connect \Y $387
+ end
+ process $group_175
+ assign \rdpick_FAST_spr2_i 2'00
+ assign \rdpick_FAST_spr2_i [0] $383
+ assign \rdpick_FAST_spr2_i [1] $387
+ sync init
+ end
+ process $group_176
+ assign \src2_i$72 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$72 \fast_src4__data_o
+ sync init
+ end
+ process $group_177
+ assign \fus_src4_i$155 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src4_i$155 \fast_src4__data_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
+ wire width 1 \rdflag_FAST_cia
+ wire width 1 $verilog_initial_trigger
+ process $group_178
+ assign \rdflag_FAST_cia 1'0
+ assign \rdflag_FAST_cia 1'1
+ assign $verilog_initial_trigger $verilog_initial_trigger
+ sync init
+ update $verilog_initial_trigger 1'0
+ end
+ process $group_179
+ assign \fast_src1__ren 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+ switch { \rdpick_FAST_cia_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+ case 1'1
+ assign \fast_src1__ren 8'00000001
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $389
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $390
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$68 [3]
+ connect \B \fu_enable [2]
+ connect \Y $389
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $391
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $392
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $389
+ connect \B \rdflag_FAST_cia
+ connect \Y $391
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $393
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $394
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$51 [4]
+ connect \B \fu_enable [3]
+ connect \Y $393
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $395
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $396
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $393
+ connect \B \rdflag_FAST_cia
+ connect \Y $395
+ end
+ process $group_180
+ assign \rdpick_FAST_cia_i 2'00
+ assign \rdpick_FAST_cia_i [0] $391
+ assign \rdpick_FAST_cia_i [1] $395
+ sync init
end
- process $group_162
- assign \rdpick_FAST_spr2_i 1'0
- assign \rdpick_FAST_spr2_i $320
+ process $group_181
+ assign \fus_src4_i$156 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src4_i$156 \fast_src1__data_o
sync init
end
- process $group_163
- assign \src2_i$62 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$62 \fast_src4__data_o
+ process $group_182
+ assign \fus_src5_i$157 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src5_i$157 \fast_src1__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:150"
- wire width 1 \rdflag_FAST_cia
- wire width 1 $verilog_initial_trigger
- process $group_164
- assign \rdflag_FAST_cia 1'0
- assign \rdflag_FAST_cia 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
+ wire width 1 \rdflag_FAST_msr
+ process $group_183
+ assign \rdflag_FAST_msr 1'0
+ assign \rdflag_FAST_msr 1'1
assign $verilog_initial_trigger $verilog_initial_trigger
sync init
- update $verilog_initial_trigger 1'0
end
- process $group_165
- assign \fast_src1__ren 8'00000000
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
- switch { \rdpick_FAST_cia_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:162"
+ process $group_184
+ assign \fast_src2__ren 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+ switch { \rdpick_FAST_msr_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
case 1'1
- assign \fast_src1__ren 8'00000001
+ assign \fast_src2__ren 8'00000010
end
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $322
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $323
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $397
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $398
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$58 [3]
- connect \B \fu_enable [2]
- connect \Y $322
+ connect \A \rd__rel$51 [5]
+ connect \B \fu_enable [3]
+ connect \Y $397
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- wire width 1 $324
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:172"
- cell $and $325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ wire width 1 $399
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+ cell $and $400
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $322
- connect \B \rdflag_FAST_cia
- connect \Y $324
+ connect \A $397
+ connect \B \rdflag_FAST_msr
+ connect \Y $399
end
- process $group_166
- assign \rdpick_FAST_cia_i 1'0
- assign \rdpick_FAST_cia_i $324
+ process $group_185
+ assign \rdpick_FAST_msr_i 1'0
+ assign \rdpick_FAST_msr_i $399
sync init
end
- process $group_167
- assign \fus_src4_i$125 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src4_i$125 \fast_src1__data_o
+ process $group_186
+ assign \fus_src6_i$158 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src6_i$158 \fast_src2__data_o
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:108"
- wire width 32 $326
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:108"
- cell $sshl $327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ wire width 32 $401
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108"
+ cell $sshl $402
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \rego
- connect \Y $326
+ connect \Y $401
end
- process $group_168
+ process $group_187
assign \int_wen$next \int_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_INT_o_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
- assign \int_wen$next $326
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ assign \int_wen$next $401
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
assign \int_wen$next 32'00000000000000000000000000000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \int_wen$next 32'00000000000000000000000000000000
sync posedge \clk
update \int_wen \int_wen$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_alu0_o_0
- process $group_169
+ process $group_188
assign \wrflag_alu0_o_0 1'0
assign \wrflag_alu0_o_0 \fus_o_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $328
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $329
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $403
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $404
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [0]
connect \B \fu_enable [0]
- connect \Y $328
+ connect \Y $403
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $330
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $331
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $405
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $406
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$63 [0]
+ connect \A \wr__rel$73 [0]
connect \B \fu_enable [1]
- connect \Y $330
+ connect \Y $405
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $332
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $407
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $408
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$65 [0]
+ connect \A \wr__rel$75 [0]
connect \B \fu_enable [3]
- connect \Y $332
+ connect \Y $407
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $334
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $335
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $409
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $410
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$67 [0]
+ connect \A \wr__rel$77 [0]
connect \B \fu_enable [4]
- connect \Y $334
+ connect \Y $409
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $336
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $337
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $411
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $412
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$69 [0]
+ connect \A \wr__rel$79 [0]
connect \B \fu_enable [5]
- connect \Y $336
+ connect \Y $411
end
- process $group_170
- assign \wrpick_INT_o_i 5'00000
- assign \wrpick_INT_o_i [0] $328
- assign \wrpick_INT_o_i [1] $330
- assign \wrpick_INT_o_i [2] $332
- assign \wrpick_INT_o_i [3] $334
- assign \wrpick_INT_o_i [4] $336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $413
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $414
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$81 [0]
+ connect \B \fu_enable [6]
+ connect \Y $413
+ end
+ process $group_189
+ assign \wrpick_INT_o_i 6'000000
+ assign \wrpick_INT_o_i [0] $403
+ assign \wrpick_INT_o_i [1] $405
+ assign \wrpick_INT_o_i [2] $407
+ assign \wrpick_INT_o_i [3] $409
+ assign \wrpick_INT_o_i [4] $411
+ assign \wrpick_INT_o_i [5] $413
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $338
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $339
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $415
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $416
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [0]
connect \B \wrpick_INT_o_en_o
- connect \Y $338
+ connect \Y $415
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $340
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $341
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $417
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $418
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [0]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $340
+ connect \Y $417
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $342
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $419
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $420
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [0]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $342
+ connect \Y $419
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $344
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $421
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $422
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $344
+ connect \Y $421
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $346
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $347
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $423
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $346
+ connect \Y $423
end
- process $group_171
+ process $group_190
assign \wr__go$next \wr__go
- assign \wr__go$next [0] $338
- assign \wr__go$next [1] $340
- assign \wr__go$next [2] $342
- assign \wr__go$next [3] $344
- assign \wr__go$next [4] $346
+ assign \wr__go$next [0] $415
+ assign \wr__go$next [1] $417
+ assign \wr__go$next [2] $419
+ assign \wr__go$next [3] $421
+ assign \wr__go$next [4] $423
sync init
update \wr__go 5'00000
sync posedge \clk
update \wr__go \wr__go$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_cr0_o_0
- process $group_172
+ process $group_191
assign \wrflag_cr0_o_0 1'0
- assign \wrflag_cr0_o_0 \fus_o_ok$126
+ assign \wrflag_cr0_o_0 \fus_o_ok$159
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $348
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $349
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $425
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [1]
connect \B \wrpick_INT_o_en_o
- connect \Y $348
+ connect \Y $425
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $350
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $351
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $427
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_full_cr_o
connect \B \wrpick_CR_full_cr_en_o
- connect \Y $350
+ connect \Y $427
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $352
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $353
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $429
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $430
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [1]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $352
+ connect \Y $429
end
- process $group_173
- assign \wr__go$64$next \wr__go$64
- assign \wr__go$64$next [0] $348
- assign \wr__go$64$next [1] $350
- assign \wr__go$64$next [2] $352
+ process $group_192
+ assign \wr__go$74$next \wr__go$74
+ assign \wr__go$74$next [0] $425
+ assign \wr__go$74$next [1] $427
+ assign \wr__go$74$next [2] $429
+ sync init
+ update \wr__go$74 3'000
+ sync posedge \clk
+ update \wr__go$74 \wr__go$74$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_trap0_o_0
+ process $group_193
+ assign \wrflag_trap0_o_0 1'0
+ assign \wrflag_trap0_o_0 \fus_o_ok$160
sync init
- update \wr__go$64 3'000
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $431
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $432
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_INT_o_o [2]
+ connect \B \wrpick_INT_o_en_o
+ connect \Y $431
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $433
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $434
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_spr1_o [1]
+ connect \B \wrpick_FAST_spr1_en_o
+ connect \Y $433
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $435
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $436
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_spr2_o [1]
+ connect \B \wrpick_FAST_spr2_en_o
+ connect \Y $435
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $437
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $438
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_nia_o [1]
+ connect \B \wrpick_FAST_nia_en_o
+ connect \Y $437
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $439
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $440
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_msr_o
+ connect \B \wrpick_FAST_msr_en_o
+ connect \Y $439
+ end
+ process $group_194
+ assign \wr__go$76$next \wr__go$76
+ assign \wr__go$76$next [0] $431
+ assign \wr__go$76$next [1] $433
+ assign \wr__go$76$next [2] $435
+ assign \wr__go$76$next [3] $437
+ assign \wr__go$76$next [4] $439
+ sync init
+ update \wr__go$76 5'00000
sync posedge \clk
- update \wr__go$64 \wr__go$64$next
+ update \wr__go$76 \wr__go$76$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_logical0_o_0
- process $group_174
+ process $group_195
assign \wrflag_logical0_o_0 1'0
- assign \wrflag_logical0_o_0 \fus_o_ok$127
+ assign \wrflag_logical0_o_0 \fus_o_ok$161
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $354
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $355
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $441
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $442
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_INT_o_o [2]
+ connect \A \wrpick_INT_o_o [3]
connect \B \wrpick_INT_o_en_o
- connect \Y $354
+ connect \Y $441
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $356
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $357
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $443
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $444
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [2]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $356
+ connect \Y $443
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $358
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $359
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $445
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $446
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [1]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $358
+ connect \Y $445
end
- process $group_175
- assign \wr__go$66$next \wr__go$66
- assign \wr__go$66$next [0] $354
- assign \wr__go$66$next [1] $356
- assign \wr__go$66$next [2] $358
+ process $group_196
+ assign \wr__go$78$next \wr__go$78
+ assign \wr__go$78$next [0] $441
+ assign \wr__go$78$next [1] $443
+ assign \wr__go$78$next [2] $445
sync init
- update \wr__go$66 3'000
+ update \wr__go$78 3'000
sync posedge \clk
- update \wr__go$66 \wr__go$66$next
+ update \wr__go$78 \wr__go$78$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_shiftrot0_o_0
- process $group_176
+ process $group_197
assign \wrflag_shiftrot0_o_0 1'0
- assign \wrflag_shiftrot0_o_0 \fus_o_ok$128
+ assign \wrflag_shiftrot0_o_0 \fus_o_ok$162
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $360
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $361
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $447
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $448
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_INT_o_o [3]
+ connect \A \wrpick_INT_o_o [4]
connect \B \wrpick_INT_o_en_o
- connect \Y $360
+ connect \Y $447
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $362
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $363
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $449
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $450
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [3]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $362
+ connect \Y $449
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $364
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $365
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $451
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $452
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [2]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $364
+ connect \Y $451
end
- process $group_177
- assign \wr__go$68$next \wr__go$68
- assign \wr__go$68$next [0] $360
- assign \wr__go$68$next [1] $362
- assign \wr__go$68$next [2] $364
+ process $group_198
+ assign \wr__go$80$next \wr__go$80
+ assign \wr__go$80$next [0] $447
+ assign \wr__go$80$next [1] $449
+ assign \wr__go$80$next [2] $451
sync init
- update \wr__go$68 3'000
+ update \wr__go$80 3'000
sync posedge \clk
- update \wr__go$68 \wr__go$68$next
+ update \wr__go$80 \wr__go$80$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_ldst0_o_0
- process $group_178
+ process $group_199
assign \wrflag_ldst0_o_0 1'0
assign \wrflag_ldst0_o_0 \o_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $366
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $367
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $453
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $454
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_INT_o_o [4]
+ connect \A \wrpick_INT_o_o [5]
connect \B \wrpick_INT_o_en_o
- connect \Y $366
+ connect \Y $453
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $368
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $369
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $455
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $456
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o1_o
connect \B \wrpick_INT_o1_en_o
- connect \Y $368
+ connect \Y $455
end
- process $group_179
- assign \wr__go$70$next \wr__go$70
- assign \wr__go$70$next [0] $366
- assign \wr__go$70$next [1] $368
+ process $group_200
+ assign \wr__go$82$next \wr__go$82
+ assign \wr__go$82$next [0] $453
+ assign \wr__go$82$next [1] $455
sync init
- update \wr__go$70 2'00
+ update \wr__go$82 2'00
sync posedge \clk
- update \wr__go$70 \wr__go$70$next
+ update \wr__go$82 \wr__go$82$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 64 $457
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $458
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \fus_o$163
+ connect \B \fus_o$164
+ connect \Y $457
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 64 $370
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $371
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 64 $459
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $460
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
connect \A \fus_o
- connect \B \fus_o$129
- connect \Y $370
+ connect \B $457
+ connect \Y $459
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 64 $372
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $373
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 64 $461
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $462
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o$131
+ connect \A \fus_o$166
connect \B \o
- connect \Y $372
+ connect \Y $461
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- wire width 64 $374
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- cell $or $375
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 64 $463
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $464
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o$130
- connect \B $372
- connect \Y $374
+ connect \A \fus_o$165
+ connect \B $461
+ connect \Y $463
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- wire width 64 $376
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- cell $or $377
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 64 $465
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $466
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $370
- connect \B $374
- connect \Y $376
+ connect \A $459
+ connect \B $463
+ connect \Y $465
end
- process $group_180
+ process $group_201
assign \int_data_i$next \int_data_i
- assign \int_data_i$next $376
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ assign \int_data_i$next $465
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \int_data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
update \int_data_i \int_data_i$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:110"
- wire width 32 $378
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:110"
- cell $sshl $379
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110"
+ wire width 32 $467
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110"
+ cell $sshl $468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \ea
- connect \Y $378
+ connect \Y $467
end
- process $group_181
- assign \int_wen$142$next \int_wen$142
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ process $group_202
+ assign \int_wen$183$next \int_wen$183
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_INT_o1_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
- assign \int_wen$142$next $378
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ assign \int_wen$183$next $467
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
- assign \int_wen$142$next 32'00000000000000000000000000000000
+ assign \int_wen$183$next 32'00000000000000000000000000000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \int_wen$142$next 32'00000000000000000000000000000000
+ assign \int_wen$183$next 32'00000000000000000000000000000000
end
sync init
- update \int_wen$142 32'00000000000000000000000000000000
+ update \int_wen$183 32'00000000000000000000000000000000
sync posedge \clk
- update \int_wen$142 \int_wen$142$next
+ update \int_wen$183 \int_wen$183$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_ldst0_o1_1
- process $group_182
+ process $group_203
assign \wrflag_ldst0_o1_1 1'0
assign \wrflag_ldst0_o1_1 \ea_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $380
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $381
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $469
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$69 [1]
- connect \B \fu_enable [5]
- connect \Y $380
+ connect \A \wr__rel$81 [1]
+ connect \B \fu_enable [6]
+ connect \Y $469
end
- process $group_183
+ process $group_204
assign \wrpick_INT_o1_i 1'0
- assign \wrpick_INT_o1_i $380
+ assign \wrpick_INT_o1_i $469
sync init
end
- process $group_184
- assign \int_data_i$143$next \int_data_i$143
- assign \int_data_i$143$next \ea$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_205
+ assign \int_data_i$184$next \int_data_i$184
+ assign \int_data_i$184$next \ea$83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \int_data_i$143$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \int_data_i$184$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \int_data_i$143 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \int_data_i$184 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \int_data_i$143 \int_data_i$143$next
+ update \int_data_i$184 \int_data_i$184$next
end
- process $group_185
+ process $group_206
assign \cr_full_wr__wen$next \cr_full_wr__wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_CR_full_cr_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
assign \cr_full_wr__wen$next 8'11111111
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
assign \cr_full_wr__wen$next 8'00000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_full_wr__wen$next 8'00000000
sync posedge \clk
update \cr_full_wr__wen \cr_full_wr__wen$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_cr0_full_cr_1
- process $group_186
+ process $group_207
assign \wrflag_cr0_full_cr_1 1'0
assign \wrflag_cr0_full_cr_1 \fus_full_cr_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $382
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $383
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$63 [1]
+ connect \A \wr__rel$73 [1]
connect \B \fu_enable [1]
- connect \Y $382
+ connect \Y $471
end
- process $group_187
+ process $group_208
assign \wrpick_CR_full_cr_i 1'0
- assign \wrpick_CR_full_cr_i $382
+ assign \wrpick_CR_full_cr_i $471
sync init
end
- process $group_188
+ process $group_209
assign \cr_full_wr__data_i$next \cr_full_wr__data_i
assign \cr_full_wr__data_i$next \fus_full_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_full_wr__data_i$next 32'00000000000000000000000000000000
sync posedge \clk
update \cr_full_wr__data_i \cr_full_wr__data_i$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:118"
- wire width 16 $384
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:118"
- wire width 4 $385
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:118"
- cell $sub $386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118"
+ wire width 16 $473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118"
+ wire width 4 $474
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118"
+ cell $sub $475
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_out
- connect \Y $385
+ connect \Y $474
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:118"
- wire width 16 $387
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:118"
- cell $sshl $388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118"
+ wire width 16 $476
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118"
+ cell $sshl $477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $385
- connect \Y $387
+ connect \B $474
+ connect \Y $476
end
- connect $384 $387
- process $group_189
+ connect $473 $476
+ process $group_210
assign \cr_wen$next \cr_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_CR_cr_a_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
- assign \cr_wen$next $384 [7:0]
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ assign \cr_wen$next $473 [7:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
assign \cr_wen$next 8'00000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_wen$next 8'00000000
sync posedge \clk
update \cr_wen \cr_wen$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_alu0_cr_a_1
- process $group_190
+ process $group_211
assign \wrflag_alu0_cr_a_1 1'0
assign \wrflag_alu0_cr_a_1 \fus_cr_a_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $389
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $390
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $478
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $479
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [1]
connect \B \fu_enable [0]
- connect \Y $389
+ connect \Y $478
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $391
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $480
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $481
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$63 [2]
+ connect \A \wr__rel$73 [2]
connect \B \fu_enable [1]
- connect \Y $391
+ connect \Y $480
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $393
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $483
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$65 [1]
- connect \B \fu_enable [3]
- connect \Y $393
+ connect \A \wr__rel$77 [1]
+ connect \B \fu_enable [4]
+ connect \Y $482
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $395
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$67 [1]
- connect \B \fu_enable [4]
- connect \Y $395
+ connect \A \wr__rel$79 [1]
+ connect \B \fu_enable [5]
+ connect \Y $484
end
- process $group_191
+ process $group_212
assign \wrpick_CR_cr_a_i 4'0000
- assign \wrpick_CR_cr_a_i [0] $389
- assign \wrpick_CR_cr_a_i [1] $391
- assign \wrpick_CR_cr_a_i [2] $393
- assign \wrpick_CR_cr_a_i [3] $395
+ assign \wrpick_CR_cr_a_i [0] $478
+ assign \wrpick_CR_cr_a_i [1] $480
+ assign \wrpick_CR_cr_a_i [2] $482
+ assign \wrpick_CR_cr_a_i [3] $484
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_cr0_cr_a_2
- process $group_192
+ process $group_213
assign \wrflag_cr0_cr_a_2 1'0
- assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$132
+ assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$167
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_logical0_cr_a_1
- process $group_193
+ process $group_214
assign \wrflag_logical0_cr_a_1 1'0
- assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$133
+ assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$168
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_shiftrot0_cr_a_1
- process $group_194
+ process $group_215
assign \wrflag_shiftrot0_cr_a_1 1'0
- assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$134
+ assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$169
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 4 $397
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $398
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 4 $486
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $487
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \fus_cr_a
- connect \B \fus_cr_a$135
- connect \Y $397
+ connect \B \fus_cr_a$170
+ connect \Y $486
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 4 $399
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $400
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 4 $488
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $489
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \fus_cr_a$136
- connect \B \fus_cr_a$137
- connect \Y $399
+ connect \A \fus_cr_a$171
+ connect \B \fus_cr_a$172
+ connect \Y $488
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- wire width 4 $401
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- cell $or $402
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 4 $490
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $491
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $397
- connect \B $399
- connect \Y $401
+ connect \A $486
+ connect \B $488
+ connect \Y $490
end
- process $group_195
+ process $group_216
assign \cr_data_i$next \cr_data_i
- assign \cr_data_i$next $401
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ assign \cr_data_i$next $490
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \cr_data_i$next 4'0000
sync posedge \clk
update \cr_data_i \cr_data_i$next
end
- process $group_196
+ process $group_217
assign \xer_wen$next \xer_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_XER_xer_ca_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
assign \xer_wen$next 3'010
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
assign \xer_wen$next 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_wen$next 3'000
sync posedge \clk
update \xer_wen \xer_wen$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_alu0_xer_ca_2
- process $group_197
+ process $group_218
assign \wrflag_alu0_xer_ca_2 1'0
assign \wrflag_alu0_xer_ca_2 \fus_xer_ca_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $403
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $404
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $492
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $493
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [2]
connect \B \fu_enable [0]
- connect \Y $403
+ connect \Y $492
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $405
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $494
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $495
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$65 [2]
- connect \B \fu_enable [3]
- connect \Y $405
+ connect \A \wr__rel$77 [2]
+ connect \B \fu_enable [4]
+ connect \Y $494
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $407
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $408
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $496
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $497
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$67 [2]
- connect \B \fu_enable [4]
- connect \Y $407
+ connect \A \wr__rel$79 [2]
+ connect \B \fu_enable [5]
+ connect \Y $496
end
- process $group_198
+ process $group_219
assign \wrpick_XER_xer_ca_i 3'000
- assign \wrpick_XER_xer_ca_i [0] $403
- assign \wrpick_XER_xer_ca_i [1] $405
- assign \wrpick_XER_xer_ca_i [2] $407
+ assign \wrpick_XER_xer_ca_i [0] $492
+ assign \wrpick_XER_xer_ca_i [1] $494
+ assign \wrpick_XER_xer_ca_i [2] $496
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_logical0_xer_ca_2
- process $group_199
+ process $group_220
assign \wrflag_logical0_xer_ca_2 1'0
- assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$138
+ assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$173
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_shiftrot0_xer_ca_2
- process $group_200
+ process $group_221
assign \wrflag_shiftrot0_xer_ca_2 1'0
- assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$139
+ assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$174
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- wire width 2 $409
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:25"
- cell $or $410
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 2 $498
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $499
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \fus_xer_ca$140
- connect \B \fus_xer_ca$141
- connect \Y $409
+ connect \A \fus_xer_ca$175
+ connect \B \fus_xer_ca$176
+ connect \Y $498
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- wire width 2 $411
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/util.py:28"
- cell $or $412
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ wire width 2 $500
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ cell $or $501
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \fus_xer_ca
- connect \B $409
- connect \Y $411
+ connect \B $498
+ connect \Y $500
end
- process $group_201
+ process $group_222
assign \xer_data_i$next \xer_data_i
- assign \xer_data_i$next $411
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ assign \xer_data_i$next $500
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \xer_data_i$next 2'00
sync posedge \clk
update \xer_data_i \xer_data_i$next
end
- process $group_202
- assign \xer_wen$144$next \xer_wen$144
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ process $group_223
+ assign \xer_wen$185$next \xer_wen$185
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
switch { \wrpick_XER_xer_ov_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
- assign \xer_wen$144$next 3'100
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ assign \xer_wen$185$next 3'100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
- assign \xer_wen$144$next 3'000
+ assign \xer_wen$185$next 3'000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \xer_wen$144$next 3'000
+ assign \xer_wen$185$next 3'000
end
sync init
- update \xer_wen$144 3'000
+ update \xer_wen$185 3'000
sync posedge \clk
- update \xer_wen$144 \xer_wen$144$next
+ update \xer_wen$185 \xer_wen$185$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
wire width 1 \wrflag_alu0_xer_ov_3
- process $group_203
+ process $group_224
assign \wrflag_alu0_xer_ov_3 1'0
assign \wrflag_alu0_xer_ov_3 \fus_xer_ov_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $413
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $502
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $503
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [3]
connect \B \fu_enable [0]
- connect \Y $413
+ connect \Y $502
end
- process $group_204
+ process $group_225
assign \wrpick_XER_xer_ov_i 1'0
- assign \wrpick_XER_xer_ov_i $413
+ assign \wrpick_XER_xer_ov_i $502
+ sync init
+ end
+ process $group_226
+ assign \xer_data_i$186$next \xer_data_i$186
+ assign \xer_data_i$186$next \fus_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_data_i$186$next 2'00
+ end
+ sync init
+ update \xer_data_i$186 2'00
+ sync posedge \clk
+ update \xer_data_i$186 \xer_data_i$186$next
+ end
+ process $group_227
+ assign \xer_wen$187$next \xer_wen$187
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ switch { \wrpick_XER_xer_so_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ case 1'1
+ assign \xer_wen$187$next 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+ case
+ assign \xer_wen$187$next 3'000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_wen$187$next 3'000
+ end
+ sync init
+ update \xer_wen$187 3'000
+ sync posedge \clk
+ update \xer_wen$187 \xer_wen$187$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_alu0_xer_so_4
+ process $group_228
+ assign \wrflag_alu0_xer_so_4 1'0
+ assign \wrflag_alu0_xer_so_4 \fus_xer_so_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $504
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $505
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel [4]
+ connect \B \fu_enable [0]
+ connect \Y $504
+ end
+ process $group_229
+ assign \wrpick_XER_xer_so_i 1'0
+ assign \wrpick_XER_xer_so_i $504
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 $506
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ cell $pos $507
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 2
+ connect \A \fus_xer_so
+ connect \Y $506
+ end
+ process $group_230
+ assign \xer_data_i$188$next \xer_data_i$188
+ assign \xer_data_i$188$next $506
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_data_i$188$next 2'00
+ end
+ sync init
+ update \xer_data_i$188 2'00
+ sync posedge \clk
+ update \xer_data_i$188 \xer_data_i$188$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147"
+ wire width 8 $508
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147"
+ cell $sshl $509
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \fasto1
+ connect \Y $508
+ end
+ process $group_231
+ assign \fast_wen$next \fast_wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ switch { \wrpick_FAST_spr1_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ case 1'1
+ assign \fast_wen$next $508
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+ case
+ assign \fast_wen$next 8'00000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \fast_wen$next 8'00000000
+ end
+ sync init
+ update \fast_wen 8'00000000
+ sync posedge \clk
+ update \fast_wen \fast_wen$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_branch0_spr1_0
+ process $group_232
+ assign \wrflag_branch0_spr1_0 1'0
+ assign \wrflag_branch0_spr1_0 \fus_spr1_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $510
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $511
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$84 [0]
+ connect \B \fu_enable [2]
+ connect \Y $510
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $512
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $513
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$75 [1]
+ connect \B \fu_enable [3]
+ connect \Y $512
+ end
+ process $group_233
+ assign \wrpick_FAST_spr1_i 2'00
+ assign \wrpick_FAST_spr1_i [0] $510
+ assign \wrpick_FAST_spr1_i [1] $512
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $514
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $515
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_spr1_o [0]
+ connect \B \wrpick_FAST_spr1_en_o
+ connect \Y $514
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $516
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $517
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_spr2_o [0]
+ connect \B \wrpick_FAST_spr2_en_o
+ connect \Y $516
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ wire width 1 $518
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243"
+ cell $and $519
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_FAST_nia_o [0]
+ connect \B \wrpick_FAST_nia_en_o
+ connect \Y $518
+ end
+ process $group_234
+ assign \wr__go$85$next \wr__go$85
+ assign \wr__go$85$next [0] $514
+ assign \wr__go$85$next [1] $516
+ assign \wr__go$85$next [2] $518
+ sync init
+ update \wr__go$85 3'000
+ sync posedge \clk
+ update \wr__go$85 \wr__go$85$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_trap0_spr1_1
+ process $group_235
+ assign \wrflag_trap0_spr1_1 1'0
+ assign \wrflag_trap0_spr1_1 \fus_spr1_ok$177
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 64 $520
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $521
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \fus_spr1
+ connect \B \fus_spr1$178
+ connect \Y $520
+ end
+ process $group_236
+ assign \fast_data_i$next \fast_data_i
+ assign \fast_data_i$next $520
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \fast_data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ sync init
+ update \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \fast_data_i \fast_data_i$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149"
+ wire width 8 $522
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149"
+ cell $sshl $523
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 8
+ connect \A 1'1
+ connect \B \fasto2
+ connect \Y $522
+ end
+ process $group_237
+ assign \fast_wen$189$next \fast_wen$189
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ switch { \wrpick_FAST_spr2_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ case 1'1
+ assign \fast_wen$189$next $522
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+ case
+ assign \fast_wen$189$next 8'00000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \fast_wen$189$next 8'00000000
+ end
+ sync init
+ update \fast_wen$189 8'00000000
+ sync posedge \clk
+ update \fast_wen$189 \fast_wen$189$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_branch0_spr2_1
+ process $group_238
+ assign \wrflag_branch0_spr2_1 1'0
+ assign \wrflag_branch0_spr2_1 \fus_spr2_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $524
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $525
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$84 [1]
+ connect \B \fu_enable [2]
+ connect \Y $524
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $526
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $527
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$75 [2]
+ connect \B \fu_enable [3]
+ connect \Y $526
+ end
+ process $group_239
+ assign \wrpick_FAST_spr2_i 2'00
+ assign \wrpick_FAST_spr2_i [0] $524
+ assign \wrpick_FAST_spr2_i [1] $526
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_trap0_spr2_2
+ process $group_240
+ assign \wrflag_trap0_spr2_2 1'0
+ assign \wrflag_trap0_spr2_2 \fus_spr2_ok$179
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 64 $528
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $529
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \fus_spr2
+ connect \B \fus_spr2$180
+ connect \Y $528
+ end
+ process $group_241
+ assign \fast_data_i$190$next \fast_data_i$190
+ assign \fast_data_i$190$next $528
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \fast_data_i$190$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ sync init
+ update \fast_data_i$190 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \fast_data_i$190 \fast_data_i$190$next
+ end
+ process $group_242
+ assign \fast_nia_wen$next \fast_nia_wen
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ switch { \wrpick_FAST_nia_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ case 1'1
+ assign \fast_nia_wen$next 8'00000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+ case
+ assign \fast_nia_wen$next 8'00000000
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \fast_nia_wen$next 8'00000000
+ end
sync init
+ update \fast_nia_wen 8'00000000
+ sync posedge \clk
+ update \fast_nia_wen \fast_nia_wen$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_branch0_nia_2
+ process $group_243
+ assign \wrflag_branch0_nia_2 1'0
+ assign \wrflag_branch0_nia_2 \fus_nia_ok
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $530
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $531
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$84 [2]
+ connect \B \fu_enable [2]
+ connect \Y $530
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $532
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $533
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$75 [3]
+ connect \B \fu_enable [3]
+ connect \Y $532
+ end
+ process $group_244
+ assign \wrpick_FAST_nia_i 2'00
+ assign \wrpick_FAST_nia_i [0] $530
+ assign \wrpick_FAST_nia_i [1] $532
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_trap0_nia_3
+ process $group_245
+ assign \wrflag_trap0_nia_3 1'0
+ assign \wrflag_trap0_nia_3 \fus_nia_ok$181
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ wire width 64 $534
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ cell $or $535
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \fus_nia
+ connect \B \fus_nia$182
+ connect \Y $534
end
- process $group_205
- assign \xer_data_i$145$next \xer_data_i$145
- assign \xer_data_i$145$next \fus_xer_ov
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_246
+ assign \fast_data_i$191$next \fast_data_i$191
+ assign \fast_data_i$191$next $534
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \xer_data_i$145$next 2'00
+ assign \fast_data_i$191$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \xer_data_i$145 2'00
+ update \fast_data_i$191 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \xer_data_i$145 \xer_data_i$145$next
+ update \fast_data_i$191 \fast_data_i$191$next
end
- process $group_206
- assign \xer_wen$146$next \xer_wen$146
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- switch { \wrpick_XER_xer_so_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
+ process $group_247
+ assign \fast_wen$192$next \fast_wen$192
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
+ switch { \wrpick_FAST_msr_en_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224"
case 1'1
- assign \xer_wen$146$next 3'001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
+ assign \fast_wen$192$next 8'00000010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
case
- assign \xer_wen$146$next 3'000
+ assign \fast_wen$192$next 8'00000000
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \xer_wen$146$next 3'000
+ assign \fast_wen$192$next 8'00000000
end
sync init
- update \xer_wen$146 3'000
+ update \fast_wen$192 8'00000000
sync posedge \clk
- update \xer_wen$146 \xer_wen$146$next
+ update \fast_wen$192 \fast_wen$192$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
- wire width 1 \wrflag_alu0_xer_so_4
- process $group_207
- assign \wrflag_alu0_xer_so_4 1'0
- assign \wrflag_alu0_xer_so_4 \fus_xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+ wire width 1 \wrflag_trap0_msr_4
+ process $group_248
+ assign \wrflag_trap0_msr_4 1'0
+ assign \wrflag_trap0_msr_4 \fus_msr_ok
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $415
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ wire width 1 $536
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241"
+ cell $and $537
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel [4]
- connect \B \fu_enable [0]
- connect \Y $415
+ connect \A \wr__rel$75 [4]
+ connect \B \fu_enable [3]
+ connect \Y $536
end
- process $group_208
- assign \wrpick_XER_xer_so_i 1'0
- assign \wrpick_XER_xer_so_i $415
+ process $group_249
+ assign \wrpick_FAST_msr_i 1'0
+ assign \wrpick_FAST_msr_i $536
sync init
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 $417
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- cell $pos $418
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 2
- connect \A \fus_xer_so
- connect \Y $417
- end
- process $group_209
- assign \xer_data_i$147$next \xer_data_i$147
- assign \xer_data_i$147$next $417
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_250
+ assign \fast_data_i$193$next \fast_data_i$193
+ assign \fast_data_i$193$next \fus_msr
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \xer_data_i$147$next 2'00
+ assign \fast_data_i$193$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \xer_data_i$147 2'00
+ update \fast_data_i$193 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \xer_data_i$147 \xer_data_i$147$next
+ update \fast_data_i$193 \fast_data_i$193$next
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.imem"
+module \imem
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21"
+ wire width 48 input 0 \a_pc_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23"
+ wire width 1 input 1 \a_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
+ wire width 1 input 2 \f_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29"
+ wire width 1 output 3 \f_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30"
+ wire width 64 output 4 \f_instr_o
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 5 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 6 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 output 7 \ibus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 \ibus__cyc$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22"
+ wire width 1 input 8 \a_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 input 9 \ibus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 input 10 \ibus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 output 11 \ibus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 \ibus__stb$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 64 input 12 \ibus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 45 output 13 \ibus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 45 \ibus__adr$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+ wire width 1 input 14 \f_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+ wire width 1 output 15 \f_fetch_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+ wire width 1 \f_fetch_err_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+ wire width 45 output 16 \f_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+ wire width 45 \f_badaddr_o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+ wire width 1 output 17 \a_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_stall_i
+ connect \Y $1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:147"
- wire width 8 $419
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:147"
- cell $sshl $420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \fasto1
- connect \Y $419
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_valid_i
+ connect \B $1
+ connect \Y $3
end
- process $group_210
- assign \fast_wen$next \fast_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- switch { \wrpick_FAST_spr1_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- case 1'1
- assign \fast_wen$next $419
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
- case
- assign \fast_wen$next 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \ibus__ack
+ connect \B \ibus__err
+ connect \Y $5
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \f_valid_i
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $5
+ connect \B $7
+ connect \Y $9
+ end
+ process $group_0
+ assign \ibus__cyc$next \ibus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ switch { $3 \ibus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ switch { $9 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ case 1'1
+ assign \ibus__cyc$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ case 2'1-
+ assign \ibus__cyc$next 1'1
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_wen$next 8'00000000
+ assign \ibus__cyc$next 1'0
end
sync init
- update \fast_wen 8'00000000
+ update \ibus__cyc 1'0
sync posedge \clk
- update \fast_wen \fast_wen$next
+ update \ibus__cyc \ibus__cyc$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
- wire width 1 \wrflag_branch0_spr1_0
- process $group_211
- assign \wrflag_branch0_spr1_0 1'0
- assign \wrflag_branch0_spr1_0 \fus_spr1_ok
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $not $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_stall_i
+ connect \Y $11
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $421
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $and $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$72 [0]
- connect \B \fu_enable [2]
- connect \Y $421
- end
- process $group_212
- assign \wrpick_FAST_spr1_i 1'0
- assign \wrpick_FAST_spr1_i $421
- sync init
+ connect \A \a_valid_i
+ connect \B $11
+ connect \Y $13
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $423
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $424
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_FAST_spr1_o
- connect \B \wrpick_FAST_spr1_en_o
- connect \Y $423
+ connect \A \ibus__ack
+ connect \B \ibus__err
+ connect \Y $15
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $425
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_FAST_spr2_o
- connect \B \wrpick_FAST_spr2_en_o
- connect \Y $425
+ connect \A \f_valid_i
+ connect \Y $17
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- wire width 1 $427
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:241"
- cell $and $428
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_FAST_nia_o
- connect \B \wrpick_FAST_nia_en_o
- connect \Y $427
- end
- process $group_213
- assign \wr__go$73$next \wr__go$73
- assign \wr__go$73$next [0] $423
- assign \wr__go$73$next [1] $425
- assign \wr__go$73$next [2] $427
- sync init
- update \wr__go$73 3'000
- sync posedge \clk
- update \wr__go$73 \wr__go$73$next
+ connect \A $15
+ connect \B $17
+ connect \Y $19
end
- process $group_214
- assign \fast_data_i$next \fast_data_i
- assign \fast_data_i$next \fus_spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_1
+ assign \ibus__stb$next \ibus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ switch { $13 \ibus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ switch { $19 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ case 1'1
+ assign \ibus__stb$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ case 2'1-
+ assign \ibus__stb$next 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ibus__stb$next 1'0
end
sync init
- update \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \ibus__stb 1'0
sync posedge \clk
- update \fast_data_i \fast_data_i$next
+ update \ibus__stb \ibus__stb$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:56"
+ wire width 64 \ibus_rdata
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:56"
+ wire width 64 \ibus_rdata$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $not $22
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_stall_i
+ connect \Y $21
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:149"
- wire width 8 $429
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_regspec_map.py:149"
- cell $sshl $430
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $and $24
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 8
- connect \A 1'1
- connect \B \fasto2
- connect \Y $429
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_valid_i
+ connect \B $21
+ connect \Y $23
end
- process $group_215
- assign \fast_wen$148$next \fast_wen$148
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- switch { \wrpick_FAST_spr2_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- case 1'1
- assign \fast_wen$148$next $429
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
- case
- assign \fast_wen$148$next 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $26
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \ibus__ack
+ connect \B \ibus__err
+ connect \Y $25
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $not $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \f_valid_i
+ connect \Y $27
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ cell $or $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $25
+ connect \B $27
+ connect \Y $29
+ end
+ process $group_2
+ assign \ibus_rdata$next \ibus_rdata
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ switch { $23 \ibus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ switch { $29 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+ case 1'1
+ assign \ibus_rdata$next \ibus__dat_r
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ case 2'1-
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_wen$148$next 8'00000000
+ assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \fast_wen$148 8'00000000
+ update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \fast_wen$148 \fast_wen$148$next
+ update \ibus_rdata \ibus_rdata$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
- wire width 1 \wrflag_branch0_spr2_1
- process $group_216
- assign \wrflag_branch0_spr2_1 1'0
- assign \wrflag_branch0_spr2_1 \fus_spr2_ok
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $not $32
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \a_stall_i
+ connect \Y $31
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $431
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $432
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ cell $and $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$72 [1]
- connect \B \fu_enable [2]
- connect \Y $431
- end
- process $group_217
- assign \wrpick_FAST_spr2_i 1'0
- assign \wrpick_FAST_spr2_i $431
- sync init
+ connect \A \a_valid_i
+ connect \B $31
+ connect \Y $33
end
- process $group_218
- assign \fast_data_i$149$next \fast_data_i$149
- assign \fast_data_i$149$next \fus_spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_3
+ assign \ibus__adr$next \ibus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ switch { $33 \ibus__cyc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+ case 2'-1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+ case 2'1-
+ assign \ibus__adr$next \a_pc_i [47:3]
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_data_i$149$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ibus__adr$next 45'000000000000000000000000000000000000000000000
end
sync init
- update \fast_data_i$149 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \ibus__adr 45'000000000000000000000000000000000000000000000
sync posedge \clk
- update \fast_data_i$149 \fast_data_i$149$next
+ update \ibus__adr \ibus__adr$next
end
- process $group_219
- assign \fast_nia_wen$next \fast_nia_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- switch { \wrpick_FAST_nia_en_o }
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:222"
- case 1'1
- assign \fast_nia_wen$next 8'00000001
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:224"
- case
- assign \fast_nia_wen$next 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ cell $and $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \ibus__cyc
+ connect \B \ibus__err
+ connect \Y $35
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ cell $not $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \f_stall_i
+ connect \Y $37
+ end
+ process $group_4
+ assign \f_fetch_err_o$next \f_fetch_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ switch { $37 $35 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ case 2'-1
+ assign \f_fetch_err_o$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ case 2'1-
+ assign \f_fetch_err_o$next 1'0
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_nia_wen$next 8'00000000
+ assign \f_fetch_err_o$next 1'0
end
sync init
- update \fast_nia_wen 8'00000000
+ update \f_fetch_err_o 1'0
sync posedge \clk
- update \fast_nia_wen \fast_nia_wen$next
+ update \f_fetch_err_o \f_fetch_err_o$next
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:234"
- wire width 1 \wrflag_branch0_nia_2
- process $group_220
- assign \wrflag_branch0_nia_2 1'0
- assign \wrflag_branch0_nia_2 \fus_nia_ok
- sync init
- end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- wire width 1 $433
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:239"
- cell $and $434
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$72 [2]
- connect \B \fu_enable [2]
- connect \Y $433
+ connect \A \ibus__cyc
+ connect \B \ibus__err
+ connect \Y $39
end
- process $group_221
- assign \wrpick_FAST_nia_i 1'0
- assign \wrpick_FAST_nia_i $433
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ cell $not $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \f_stall_i
+ connect \Y $41
end
- process $group_222
- assign \fast_data_i$150$next \fast_data_i$150
- assign \fast_data_i$150$next \fus_nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ process $group_5
+ assign \f_badaddr_o$next \f_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ switch { $41 $39 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+ case 2'-1
+ assign \f_badaddr_o$next \ibus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+ case 2'1-
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \fast_data_i$150$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000
end
sync init
- update \fast_data_i$150 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \f_badaddr_o 45'000000000000000000000000000000000000000000000
sync posedge \clk
- update \fast_data_i$150 \fast_data_i$150$next
+ update \f_badaddr_o \f_badaddr_o$next
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "top.imem"
-module \imem
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 6 input 0 \mem_r_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 32 output 1 \mem_r_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 2 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 1 input 3 \mem_w_en
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 6 input 4 \mem_w_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 32 input 5 \mem_w_data
- memory width 32 size 64 \mem
- cell $meminit $1
- parameter \MEMID "\\mem"
- parameter \ABITS 7
- parameter \WIDTH 32
- parameter \WORDS 64
- parameter \PRIORITY 0
- connect \ADDR 7'0000000
- connect \DATA 2048'00000000000000000000000001111110000000000000000000000000011111000000000000000000000000000111101000000000000000000000000001111000000000000000000000000000011101100000000000000000000000000111010000000000000000000000000001110010000000000000000000000000011100000000000000000000000000000110111000000000000000000000000001101100000000000000000000000000011010100000000000000000000000000110100000000000000000000000000001100110000000000000000000000000011001000000000000000000000000000110001000000000000000000000000001100000000000000000000000000000010111100000000000000000000000000101110000000000000000000000000001011010000000000000000000000000010110000000000000000000000000000101011000000000000000000000000001010100000000000000000000000000010100100000000000000000000000000101000000000000000000000000000001001110000000000000000000000000010011000000000000000000000000000100101000000000000000000000000001001000000000000000000000000000010001100000000000000000000000000100010000000000000000000000000001000010000000000000000000000000010000000000000000000000000000000011111000000000000000000000000000111100000000000000000000000000001110100000000000000000000000000011100000000000000000000000000000110110000000000000000000000000001101000000000000000000000000000011001000000000000000000000000000110000000000000000000000000000001011100000000000000000000000000010110000000000000000000000000000101010000000000000000000000000001010000000000000000000000000000010011000000000000000000000000000100100000000000000000000000000001000100000000000000000000000000010000000000000000000000000000000011110000000000000000000000000000111000000000000000000000000000001101000000000000000000000000000011000000000000000000000000000000101100000000000000000000000000001010000000000000000000000000000010010000000000000000000000000000100000000000000000000000000000000111000000000000000000000000000001100000000000000000000000000000010100000000000000000000000000000100000000000000000000000000000000110000000000000000000000000000001000000000000000000000000000000001000000000000000000000000000000000
- end
- cell $memrd \rdport
- parameter \MEMID "\\mem"
- parameter \ABITS 6
- parameter \WIDTH 32
- parameter \CLK_ENABLE 1
- parameter \CLK_POLARITY 1
- parameter \TRANSPARENT 1
- connect \CLK \clk
- connect \EN 1'1
- connect \ADDR \mem_r_addr
- connect \DATA \mem_r_data
- end
- cell $memwr \wrport
- parameter \MEMID "\\mem"
- parameter \ABITS 6
- parameter \WIDTH 32
- parameter \CLK_ENABLE 1
- parameter \CLK_POLARITY 1
- parameter \PRIORITY 0
- connect \CLK \clk
- connect \EN { { \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en \mem_w_en } }
- connect \ADDR \mem_w_addr
- connect \DATA \mem_w_data
+ process $group_6
+ assign \a_busy_o 1'0
+ assign \a_busy_o \ibus__cyc
+ sync init
+ end
+ process $group_7
+ assign \f_busy_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+ switch { \f_fetch_err_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+ case 1'1
+ assign \f_busy_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+ case
+ assign \f_busy_o \ibus__cyc
+ end
+ sync init
+ end
+ process $group_8
+ assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+ switch { \f_fetch_err_o }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+ case 1'1
+ assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+ case
+ assign \f_instr_o \ibus_rdata
+ end
+ sync init
end
end
attribute \generator "nMigen"
attribute \top 1
-attribute \nmigen.hierarchy "top"
-module \top
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+attribute \nmigen.hierarchy "test_issuer"
+module \test_issuer
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 input 0 \pc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 input 1 \pc_ok
- attribute \src "issuer.py:44"
+ attribute \src "simple/issuer.py:46"
wire width 64 output 2 \pc_o
- attribute \src "issuer.py:43"
+ attribute \src "simple/issuer.py:45"
wire width 1 input 3 \go_insn_i
- attribute \src "issuer.py:47"
+ attribute \src "simple/issuer.py:49"
wire width 1 input 4 \memerr_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 5 \rd__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 5 output 6 \wr__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 output 7 \issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 8 \shadown_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 9 \go_die_i
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 7 output 10 \oper_i__insn_type
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 11 \oper_i__lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 12 \oper_i__invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 13 \oper_i__invert_out
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 2 output 14 \oper_i__input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 15 \oper_i__output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 16 \oper_i__input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 17 \oper_i__output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 18 \oper_i__is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 19 \oper_i__is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 4 output 20 \oper_i__data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 21 \oper_i__byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
wire width 1 output 22 \oper_i__sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 23 \src1_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 24 \src2_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 25 \busy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 26 \rd__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 5 output 27 \wr__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 28 \dest1_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 output 29 \rd__go$1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 30 \wr__go$2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 output 31 \issue_i$3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 32 \shadown_i$4
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 33 \go_die_i$5
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 7 output 34 \oper_i__insn_type$6
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 32 output 35 \oper_i__insn
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 10 output 36 \oper_i__fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 37 \oper_i__read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
wire width 1 output 38 \oper_i__write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 39 \src1_i$7
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 40 \src2_i$8
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 41 \busy_o$9
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 output 42 \rd__rel$10
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 43 \wr__rel$11
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 44 \dest1_o$12
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 45 \rd__go$13
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 46 \wr__go$14
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 output 47 \issue_i$15
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 48 \shadown_i$16
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 49 \go_die_i$17
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 7 output 50 \oper_i__insn_type$18
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 10 output 51 \oper_i__fn_unit$19
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 52 \oper_i__lk$20
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 1 output 53 \oper_i__is_32bit$21
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
wire width 32 output 54 \oper_i__insn$22
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 55 \src1_i$23
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
wire width 64 output 56 \src2_i$24
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 57 \busy_o$25
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 58 \rd__rel$26
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 59 \wr__rel$27
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 output 60 \dest1_o$28
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 61 \rd__go$29
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 62 \wr__go$30
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 61 \rd__go$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 62 \wr__go$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 output 63 \issue_i$31
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 64 \shadown_i$32
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 65 \go_die_i$33
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
wire width 7 output 66 \oper_i__insn_type$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 32 output 67 \oper_i__insn$35
+ attribute \enum_base_type "Function"
+ attribute \enum_value_0000000000 "NONE"
+ attribute \enum_value_0000000010 "ALU"
+ attribute \enum_value_0000000100 "LDST"
+ attribute \enum_value_0000001000 "SHIFT_ROT"
+ attribute \enum_value_0000010000 "LOGICAL"
+ attribute \enum_value_0000100000 "BRANCH"
+ attribute \enum_value_0001000000 "CR"
+ attribute \enum_value_0010000000 "TRAP"
+ attribute \enum_value_0100000000 "MUL"
+ attribute \enum_value_1000000000 "DIV"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 10 output 68 \oper_i__fn_unit$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 1 output 69 \oper_i__is_32bit$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 4 output 70 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ wire width 13 output 71 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 72 \src1_i$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 73 \src2_i$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 74 \busy_o$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 6 output 75 \rd__rel$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 5 output 76 \wr__rel$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 77 \dest1_o$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 78 \rd__go$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 79 \wr__go$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 80 \issue_i$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 81 \shadown_i$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 82 \go_die_i$48
+ attribute \enum_base_type "InternalOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 7 output 83 \oper_i__insn_type$49
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 10 output 67 \oper_i__fn_unit$35
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 68 \oper_i__lk$36
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 69 \oper_i__invert_a$37
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 70 \oper_i__invert_out$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 10 output 84 \oper_i__fn_unit$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 85 \oper_i__lk$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 86 \oper_i__invert_a$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 87 \oper_i__invert_out$53
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 71 \oper_i__input_carry$39
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 72 \oper_i__output_carry$40
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 73 \oper_i__is_32bit$41
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 74 \oper_i__is_signed$42
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 75 \oper_i__data_len$43
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 76 \src1_i$44
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 77 \src2_i$45
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 78 \busy_o$46
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 79 \rd__rel$47
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 80 \wr__rel$48
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 81 \dest1_o$49
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 82 \rd__go$50
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 83 \wr__go$51
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 84 \issue_i$52
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 85 \shadown_i$53
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 86 \go_die_i$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 2 output 88 \oper_i__input_carry$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 89 \oper_i__output_carry$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 90 \oper_i__is_32bit$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 1 output 91 \oper_i__is_signed$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ wire width 4 output 92 \oper_i__data_len$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 93 \src1_i$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 94 \src2_i$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 95 \busy_o$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 96 \rd__rel$62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 97 \wr__rel$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 98 \dest1_o$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 99 \rd__go$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 100 \wr__go$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 101 \issue_i$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 102 \shadown_i$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 103 \go_die_i$69
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 87 \oper_i__insn_type$55
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 7 output 104 \oper_i__insn_type$70
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 88 \oper_i__input_carry$56
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 89 \oper_i__output_carry$57
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 90 \oper_i__input_cr$58
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 91 \oper_i__output_cr$59
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 92 \oper_i__is_32bit$60
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 93 \oper_i__is_signed$61
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 94 \src1_i$62
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 95 \src2_i$63
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 96 \busy_o$64
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 97 \rd__rel$65
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 98 \wr__rel$66
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 99 \dest1_o$67
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 100 \rd__go$68
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 101 \ad__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 102 \wr__go$69
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 103 \st__go
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 104 \issue_i$70
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 105 \shadown_i$71
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 106 \go_die_i$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 2 output 105 \oper_i__input_carry$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 106 \oper_i__output_carry$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 107 \oper_i__input_cr$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 108 \oper_i__output_cr$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 109 \oper_i__is_32bit$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ wire width 1 output 110 \oper_i__is_signed$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 111 \src1_i$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 112 \src2_i$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 113 \busy_o$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 114 \rd__rel$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 115 \wr__rel$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 116 \dest1_o$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 117 \rd__go$83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 1 output 118 \ad__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 119 \wr__go$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 1 output 120 \st__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 121 \issue_i$85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 122 \shadown_i$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 123 \go_die_i$87
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 output 107 \oper_i__insn_type$73
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 108 \oper_i__is_32bit$74
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 109 \oper_i__zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 110 \oper_i__is_signed$75
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 output 111 \oper_i__data_len$76
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 112 \oper_i__byte_reverse$77
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 113 \oper_i__sign_extend$78
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 114 \oper_i__update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 115 \src1_i$79
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 116 \src2_i$80
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 117 \src3_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 118 \busy_o$81
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 119 \rd__rel$82
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 120 \ad__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 121 \st__rel
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 122 \wr__rel$83
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 123 \o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 124 \o_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 125 \ea
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 126 \ea_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 127 \load_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 128 \stwd_mem_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:318"
- wire width 32 output 129 \raw_opcode_in
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:319"
- wire width 1 output 130 \bigendian
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 131 \opcode_in
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 7 output 124 \oper_i__insn_type$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 125 \oper_i__is_32bit$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 126 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 127 \oper_i__is_signed$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 4 output 128 \oper_i__data_len$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 129 \oper_i__byte_reverse$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 130 \oper_i__sign_extend$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ wire width 1 output 131 \oper_i__update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 132 \src1_i$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 133 \src2_i$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 134 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 135 \busy_o$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 136 \rd__rel$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 1 output 137 \ad__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 1 output 138 \st__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 2 output 139 \wr__rel$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 140 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 141 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 142 \ea
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 143 \ea_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
+ wire width 1 output 144 \load_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
+ wire width 1 output 145 \stwd_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
+ wire width 32 output 146 \raw_opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
+ wire width 1 output 147 \bigendian
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ wire width 32 output 148 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 10 output 132 \function_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 10 output 149 \function_unit
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 133 \in1_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+ wire width 3 output 150 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 134 \in2_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+ wire width 4 output 151 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 135 \in3_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+ wire width 2 output 152 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 136 \out_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+ wire width 2 output 153 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 137 \cr_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+ wire width 3 output 154 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 138 \cr_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+ wire width 3 output 155 \cr_out
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0010 "is2B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 139 \ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+ wire width 4 output 156 \ldst_len
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 140 \rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 157 \rc_sel
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 141 \internal_op
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+ wire width 7 output 158 \internal_op
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11010 "EVS"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 output 142 \form
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 output 143 \asmcode
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 144 \inv_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 145 \inv_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 146 \cry_out
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 147 \br
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 148 \sgn_ext
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 149 \upd
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 150 \rsrv
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 151 \is_32b
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 152 \sgn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 153 \lk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 154 \sgl_pipe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:32"
- wire width 1 output 155 \valid
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+ wire width 5 output 159 \form
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+ wire width 8 output 160 \asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 161 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 162 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 163 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 164 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 165 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 166 \upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 167 \rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 168 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 169 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 170 \lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ wire width 1 output 171 \sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32"
+ wire width 1 output 172 \valid
attribute \enum_base_type "InternalOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_1000110 "OP_RFID"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:33"
- wire width 7 output 156 \insn_type
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+ wire width 7 output 173 \insn_type
attribute \enum_base_type "Function"
attribute \enum_value_0000000000 "NONE"
attribute \enum_value_0000000010 "ALU"
attribute \enum_value_0010000000 "TRAP"
attribute \enum_value_0100000000 "MUL"
attribute \enum_value_1000000000 "DIV"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:34"
- wire width 10 output 157 \fn_unit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:36"
- wire width 8 input 158 \asmcode$84
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:37"
- wire width 64 output 159 \nia
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 160 \rego
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 161 \rego_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 162 \ea$85
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 163 \ea_ok$86
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 164 \reg1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 165 \reg1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 166 \reg2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 167 \reg2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 168 \reg3
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 169 \reg3_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 170 \imm
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 171 \imm_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 172 \spro
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 173 \spro_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 174 \spr1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 175 \spr1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 input 176 \spr2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 177 \spr2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 178 \fast1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 179 \fast1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 180 \fast2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 181 \fast2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 182 \fasto1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 183 \fasto1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 184 \fasto2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 185 \fasto2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 186 \cr_in1
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 187 \cr_in1_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 188 \cr_in2
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 189 \cr_in2_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 190 \cr_in2$87
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 191 \cr_in2_ok$88
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:56"
- wire width 1 output 192 \read_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 193 \cr_out$89
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 194 \cr_out_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:58"
- wire width 1 output 195 \write_cr_whole
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:59"
- wire width 1 output 196 \lk$90
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 197 \rc
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 198 \rc_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 199 \oe
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 200 \oe_ok
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:62"
- wire width 1 output 201 \invert_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:63"
- wire width 1 output 202 \zero_a
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:64"
- wire width 1 output 203 \invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+ wire width 10 output 174 \fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36"
+ wire width 8 input 175 \asmcode$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 64 output 176 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 177 \rego
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 178 \rego_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 179 \ea$100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 180 \ea_ok$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 181 \reg1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 182 \reg1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 183 \reg2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 184 \reg2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 185 \reg3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 186 \reg3_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 187 \imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 188 \imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 189 \spro
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 190 \spro_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 output 191 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 192 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 10 input 193 \spr2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 194 \spr2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 195 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 196 \fast1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 197 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 198 \fast2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 199 \fasto1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 200 \fasto1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 201 \fasto2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 202 \fasto2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 203 \cr_in1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 204 \cr_in1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 205 \cr_in2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 206 \cr_in2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 207 \cr_in2$102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 208 \cr_in2_ok$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+ wire width 1 output 209 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 210 \cr_out$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 211 \cr_out_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ wire width 1 output 212 \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+ wire width 1 output 213 \lk$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 214 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 215 \rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 216 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 217 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
+ wire width 1 output 218 \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
+ wire width 1 output 219 \zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
+ wire width 1 output 220 \invert_out
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:65"
- wire width 2 output 204 \input_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:66"
- wire width 1 output 205 \output_carry
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:67"
- wire width 1 output 206 \input_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:68"
- wire width 1 output 207 \output_cr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:69"
- wire width 1 output 208 \is_32bit
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:70"
- wire width 1 output 209 \is_signed
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:71"
- wire width 32 output 210 \insn
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:72"
- wire width 4 output 211 \data_len
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:73"
- wire width 1 output 212 \byte_reverse
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:74"
- wire width 1 output 213 \sign_extend
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:75"
- wire width 1 output 214 \update
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:76"
- wire width 4 input 215 \traptype
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/decoder/decode2execute1.py:77"
- wire width 13 input 216 \trapaddr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 6 output 217 \mem_r_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:16"
- wire width 32 output 218 \mem_r_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 6 input 219 \mem_w_addr
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 32 input 220 \mem_w_data
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/experiment/testmem.py:17"
- wire width 1 input 221 \mem_w_en
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 222 \clk
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 223 \rst
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
+ wire width 2 output 221 \input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
+ wire width 1 output 222 \output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
+ wire width 1 output 223 \input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
+ wire width 1 output 224 \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
+ wire width 1 output 225 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
+ wire width 1 output 226 \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+ wire width 32 output 227 \insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
+ wire width 4 output 228 \data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
+ wire width 1 output 229 \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
+ wire width 1 output 230 \sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
+ wire width 1 output 231 \update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76"
+ wire width 4 input 232 \traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77"
+ wire width 13 output 233 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 234 \ldst_port0_is_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 235 \ldst_port0_is_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 236 \ldst_port0_data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 237 \ldst_port0_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 output 238 \ldst_port0_go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 48 output 239 \ldst_port0_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 240 \ldst_port0_addr_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 241 \ldst_port0_addr_ok_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 input 242 \ldst_port0_addr_exc_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 243 \ldst_port0_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 244 \ldst_port0_ld_data_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 245 \ldst_port0_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 246 \ldst_port0_st_data_i_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+ wire width 48 output 247 \x_addr_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+ wire width 8 output 248 \x_mask_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+ wire width 1 output 249 \x_ld_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+ wire width 1 output 250 \x_st_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+ wire width 64 output 251 \x_st_data_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+ wire width 1 input 252 \x_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+ wire width 1 output 253 \x_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+ wire width 1 input 254 \m_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+ wire width 1 output 255 \m_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+ wire width 1 output 256 \x_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+ wire width 1 output 257 \m_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+ wire width 64 output 258 \m_ld_data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+ wire width 1 output 259 \m_load_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+ wire width 1 output 260 \m_store_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+ wire width 45 output 261 \m_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 45 output 262 \dbus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 output 263 \dbus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 64 input 264 \dbus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 8 output 265 \dbus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 266 \dbus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 267 \dbus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 268 \dbus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 output 269 \dbus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 3 input 270 \dbus__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 2 input 271 \dbus__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+ wire width 1 input 272 \dbus__err
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+ wire width 1 output 273 \ldst_port0_is_ld_i$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+ wire width 1 output 274 \ldst_port0_is_st_i$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+ wire width 4 output 275 \ldst_port0_data_len$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+ wire width 1 output 276 \ldst_port0_busy_o$109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+ wire width 1 input 277 \ldst_port0_go_die_i$110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 96 output 278 \ldst_port0_addr_i$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 279 \ldst_port0_addr_i_ok$112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+ wire width 1 output 280 \ldst_port0_addr_ok_o$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+ wire width 1 output 281 \ldst_port0_addr_exc_o$114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 282 \ldst_port0_ld_data_o$115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 283 \ldst_port0_ld_data_o_ok$116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 284 \ldst_port0_st_data_i$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 285 \ldst_port0_st_data_i_ok$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21"
+ wire width 48 output 286 \a_pc_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22"
+ wire width 1 input 287 \a_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23"
+ wire width 1 output 288 \a_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+ wire width 1 input 289 \f_stall_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
+ wire width 1 output 290 \f_valid_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+ wire width 1 output 291 \a_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29"
+ wire width 1 output 292 \f_busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30"
+ wire width 64 output 293 \f_instr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+ wire width 1 output 294 \f_fetch_err_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+ wire width 45 output 295 \f_badaddr_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 45 output 296 \ibus__adr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 64 input 297 \ibus__dat_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 64 input 298 \ibus__dat_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 8 input 299 \ibus__sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 output 300 \ibus__cyc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 output 301 \ibus__stb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 input 302 \ibus__ack
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 input 303 \ibus__we
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 3 input 304 \ibus__cti
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 2 input 305 \ibus__bte
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+ wire width 1 input 306 \ibus__err
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 307 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 308 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \core_d_rd1__ren
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \core_d_rd1__data_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75"
wire width 1 \core_issue_i
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \core_fast_nia_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/soc/src/soc/simple/core.py:74"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:76"
wire width 1 \core_corebusy_o
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \core_wen
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/libre-soc/nmutil/src/nmutil/iocontrol.py:91"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \core_data_i
cell \core \core
connect \ad__go \ad__go
connect \imm \imm
connect \imm_ok \imm_ok
connect \oper_i__lk \oper_i__lk
- connect \lk \lk$90
+ connect \lk \lk$105
connect \rc \rc
connect \rc_ok \rc_ok
connect \oe \oe
connect \zero_a \zero_a
connect \oper_i__invert_out \oper_i__invert_out
connect \invert_out \invert_out
- connect \cr_out \cr_out$89
+ connect \cr_out \cr_out$104
connect \cr_out_ok \cr_out_ok
connect \oper_i__input_carry \oper_i__input_carry
connect \input_carry \input_carry
connect \busy_o$4 \busy_o$9
connect \cr_in1_ok \cr_in1_ok
connect \cr_in2_ok \cr_in2_ok
- connect \cr_in2_ok$5 \cr_in2_ok$88
+ connect \cr_in2_ok$5 \cr_in2_ok$103
connect \oper_i__insn_type$6 \oper_i__insn_type$18
connect \oper_i__fn_unit$7 \oper_i__fn_unit$19
connect \oper_i__lk$8 \oper_i__lk$20
connect \fast1_ok \fast1_ok
connect \fast2_ok \fast2_ok
connect \oper_i__insn_type$13 \oper_i__insn_type$34
- connect \oper_i__fn_unit$14 \oper_i__fn_unit$35
- connect \oper_i__lk$15 \oper_i__lk$36
- connect \oper_i__invert_a$16 \oper_i__invert_a$37
- connect \oper_i__input_carry$17 \oper_i__input_carry$39
- connect \oper_i__invert_out$18 \oper_i__invert_out$38
- connect \oper_i__output_carry$19 \oper_i__output_carry$40
- connect \oper_i__is_32bit$20 \oper_i__is_32bit$41
- connect \oper_i__is_signed$21 \oper_i__is_signed$42
- connect \oper_i__data_len$22 \oper_i__data_len$43
- connect \issue_i$23 \issue_i$31
- connect \busy_o$24 \busy_o$46
- connect \oper_i__insn_type$25 \oper_i__insn_type$55
- connect \oper_i__input_carry$26 \oper_i__input_carry$56
- connect \oper_i__output_carry$27 \oper_i__output_carry$57
- connect \oper_i__input_cr$28 \oper_i__input_cr$58
- connect \oper_i__output_cr$29 \oper_i__output_cr$59
- connect \oper_i__is_32bit$30 \oper_i__is_32bit$60
- connect \oper_i__is_signed$31 \oper_i__is_signed$61
- connect \issue_i$32 \issue_i$52
- connect \busy_o$33 \busy_o$64
+ connect \oper_i__fn_unit$14 \oper_i__fn_unit$36
+ connect \oper_i__insn$15 \oper_i__insn$35
+ connect \oper_i__is_32bit$16 \oper_i__is_32bit$37
+ connect \oper_i__traptype \oper_i__traptype
+ connect \traptype \traptype
+ connect \oper_i__trapaddr \oper_i__trapaddr
+ connect \trapaddr \trapaddr
+ connect \issue_i$17 \issue_i$31
+ connect \busy_o$18 \busy_o$40
+ connect \oper_i__insn_type$19 \oper_i__insn_type$49
+ connect \oper_i__fn_unit$20 \oper_i__fn_unit$50
+ connect \oper_i__lk$21 \oper_i__lk$51
+ connect \oper_i__invert_a$22 \oper_i__invert_a$52
+ connect \oper_i__input_carry$23 \oper_i__input_carry$54
+ connect \oper_i__invert_out$24 \oper_i__invert_out$53
+ connect \oper_i__output_carry$25 \oper_i__output_carry$55
+ connect \oper_i__is_32bit$26 \oper_i__is_32bit$56
+ connect \oper_i__is_signed$27 \oper_i__is_signed$57
+ connect \oper_i__data_len$28 \oper_i__data_len$58
+ connect \issue_i$29 \issue_i$46
+ connect \busy_o$30 \busy_o$61
+ connect \oper_i__insn_type$31 \oper_i__insn_type$70
+ connect \oper_i__input_carry$32 \oper_i__input_carry$71
+ connect \oper_i__output_carry$33 \oper_i__output_carry$72
+ connect \oper_i__input_cr$34 \oper_i__input_cr$73
+ connect \oper_i__output_cr$35 \oper_i__output_cr$74
+ connect \oper_i__is_32bit$36 \oper_i__is_32bit$75
+ connect \oper_i__is_signed$37 \oper_i__is_signed$76
+ connect \issue_i$38 \issue_i$67
+ connect \busy_o$39 \busy_o$79
connect \reg3_ok \reg3_ok
- connect \oper_i__insn_type$34 \oper_i__insn_type$73
+ connect \oper_i__insn_type$40 \oper_i__insn_type$88
connect \oper_i__zero_a \oper_i__zero_a
- connect \oper_i__is_32bit$35 \oper_i__is_32bit$74
- connect \oper_i__is_signed$36 \oper_i__is_signed$75
- connect \oper_i__data_len$37 \oper_i__data_len$76
- connect \oper_i__byte_reverse$38 \oper_i__byte_reverse$77
- connect \oper_i__sign_extend$39 \oper_i__sign_extend$78
+ connect \oper_i__is_32bit$41 \oper_i__is_32bit$89
+ connect \oper_i__is_signed$42 \oper_i__is_signed$90
+ connect \oper_i__data_len$43 \oper_i__data_len$91
+ connect \oper_i__byte_reverse$44 \oper_i__byte_reverse$92
+ connect \oper_i__sign_extend$45 \oper_i__sign_extend$93
connect \oper_i__update \oper_i__update
connect \update \update
- connect \issue_i$40 \issue_i$70
- connect \busy_o$41 \busy_o$81
+ connect \issue_i$46 \issue_i$85
+ connect \busy_o$47 \busy_o$96
connect \reg1 \reg1
connect \rd__rel \rd__rel
connect \rd__go \rd__go
connect \src1_i \src1_i
- connect \rd__rel$42 \rd__rel$10
- connect \rd__go$43 \rd__go$1
- connect \src1_i$44 \src1_i$7
- connect \rd__rel$45 \rd__rel$47
- connect \rd__go$46 \rd__go$29
- connect \src1_i$47 \src1_i$44
- connect \rd__rel$48 \rd__rel$65
- connect \rd__go$49 \rd__go$50
- connect \src1_i$50 \src1_i$62
- connect \rd__rel$51 \rd__rel$82
- connect \rd__go$52 \rd__go$68
- connect \src1_i$53 \src1_i$79
+ connect \rd__rel$48 \rd__rel$10
+ connect \rd__go$49 \rd__go$1
+ connect \src1_i$50 \src1_i$7
+ connect \rd__rel$51 \rd__rel$41
+ connect \rd__go$52 \rd__go$29
+ connect \src1_i$53 \src1_i$38
+ connect \rd__rel$54 \rd__rel$62
+ connect \rd__go$55 \rd__go$44
+ connect \src1_i$56 \src1_i$59
+ connect \rd__rel$57 \rd__rel$80
+ connect \rd__go$58 \rd__go$65
+ connect \src1_i$59 \src1_i$77
+ connect \rd__rel$60 \rd__rel$97
+ connect \rd__go$61 \rd__go$83
+ connect \src1_i$62 \src1_i$94
connect \reg2 \reg2
connect \src2_i \src2_i
- connect \src2_i$54 \src2_i$8
- connect \src2_i$55 \src2_i$45
- connect \src2_i$56 \src2_i$63
- connect \src2_i$57 \src2_i$80
+ connect \src2_i$63 \src2_i$8
+ connect \src2_i$64 \src2_i$39
+ connect \src2_i$65 \src2_i$60
+ connect \src2_i$66 \src2_i$78
+ connect \src2_i$67 \src2_i$95
connect \reg3 \reg3
connect \src3_i \src3_i
connect \cr_in1 \cr_in1
- connect \rd__rel$58 \rd__rel$26
- connect \rd__go$59 \rd__go$13
+ connect \rd__rel$68 \rd__rel$26
+ connect \rd__go$69 \rd__go$13
connect \cr_in2 \cr_in2
- connect \cr_in2$60 \cr_in2$87
+ connect \cr_in2$70 \cr_in2$102
connect \fast1 \fast1
- connect \src1_i$61 \src1_i$23
+ connect \src1_i$71 \src1_i$23
connect \fast2 \fast2
- connect \src2_i$62 \src2_i$24
+ connect \src2_i$72 \src2_i$24
connect \rego \rego
connect \wr__rel \wr__rel
connect \wr__go \wr__go
- connect \wr__rel$63 \wr__rel$11
- connect \wr__go$64 \wr__go$2
- connect \wr__rel$65 \wr__rel$48
- connect \wr__go$66 \wr__go$30
- connect \wr__rel$67 \wr__rel$66
- connect \wr__go$68 \wr__go$51
+ connect \wr__rel$73 \wr__rel$11
+ connect \wr__go$74 \wr__go$2
+ connect \wr__rel$75 \wr__rel$42
+ connect \wr__go$76 \wr__go$30
+ connect \wr__rel$77 \wr__rel$63
+ connect \wr__go$78 \wr__go$45
+ connect \wr__rel$79 \wr__rel$81
+ connect \wr__go$80 \wr__go$66
connect \o_ok \o_ok
- connect \wr__rel$69 \wr__rel$83
- connect \wr__go$70 \wr__go$69
+ connect \wr__rel$81 \wr__rel$98
+ connect \wr__go$82 \wr__go$84
connect \o \o
- connect \ea \ea$85
+ connect \ea \ea$100
connect \ea_ok \ea_ok
- connect \ea$71 \ea
+ connect \ea$83 \ea
connect \fasto1 \fasto1
- connect \wr__rel$72 \wr__rel$27
- connect \wr__go$73 \wr__go$14
+ connect \wr__rel$84 \wr__rel$27
+ connect \wr__go$85 \wr__go$14
connect \fasto2 \fasto2
connect \opcode_in \opcode_in
connect \in1_sel \in1_sel
connect \out_sel \out_sel
connect \rc_sel \rc_sel
connect \cr_in \cr_in
- connect \cr_out$74 \cr_out
+ connect \cr_out$86 \cr_out
connect \nia \nia
connect \function_unit \function_unit
connect \internal_op \internal_op
connect \rego_ok \rego_ok
- connect \ea_ok$75 \ea_ok$86
+ connect \ea_ok$87 \ea_ok$101
connect \spr1 \spr1
connect \spr1_ok \spr1_ok
connect \spro \spro
connect \cry_out \cry_out
connect \is_32b \is_32b
connect \sgn \sgn
- connect \lk$76 \lk
+ connect \lk$88 \lk
connect \br \br
connect \sgn_ext \sgn_ext
connect \upd \upd
connect \go_die_i \go_die_i
connect \shadown_i \shadown_i
connect \dest1_o \dest1_o
- connect \go_die_i$77 \go_die_i$5
- connect \shadown_i$78 \shadown_i$4
- connect \dest1_o$79 \dest1_o$12
- connect \go_die_i$80 \go_die_i$17
- connect \shadown_i$81 \shadown_i$16
- connect \dest1_o$82 \dest1_o$28
- connect \go_die_i$83 \go_die_i$33
- connect \shadown_i$84 \shadown_i$32
- connect \dest1_o$85 \dest1_o$49
- connect \go_die_i$86 \go_die_i$54
- connect \shadown_i$87 \shadown_i$53
- connect \dest1_o$88 \dest1_o$67
- connect \go_die_i$89 \go_die_i$72
+ connect \go_die_i$89 \go_die_i$5
+ connect \shadown_i$90 \shadown_i$4
+ connect \dest1_o$91 \dest1_o$12
+ connect \go_die_i$92 \go_die_i$17
+ connect \shadown_i$93 \shadown_i$16
+ connect \dest1_o$94 \dest1_o$28
+ connect \go_die_i$95 \go_die_i$33
+ connect \shadown_i$96 \shadown_i$32
+ connect \dest1_o$97 \dest1_o$43
+ connect \go_die_i$98 \go_die_i$48
+ connect \shadown_i$99 \shadown_i$47
+ connect \dest1_o$100 \dest1_o$64
+ connect \go_die_i$101 \go_die_i$69
+ connect \shadown_i$102 \shadown_i$68
+ connect \dest1_o$103 \dest1_o$82
+ connect \go_die_i$104 \go_die_i$87
connect \load_mem_o \load_mem_o
connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i$90 \shadown_i$71
+ connect \shadown_i$105 \shadown_i$86
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$106
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i$107
+ connect \ldst_port0_data_len \ldst_port0_data_len$108
+ connect \ldst_port0_addr_i \ldst_port0_addr_i$111
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$112
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$114
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$113
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$115
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$116
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i$117
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$118
+ connect \ldst_port0_is_ld_i$106 \ldst_port0_is_ld_i
+ connect \ldst_port0_busy_o \ldst_port0_busy_o
+ connect \ldst_port0_is_st_i$107 \ldst_port0_is_st_i
+ connect \ldst_port0_data_len$108 \ldst_port0_data_len
+ connect \ldst_port0_addr_i$109 \ldst_port0_addr_i
+ connect \ldst_port0_addr_i_ok$110 \ldst_port0_addr_i_ok
+ connect \x_mask_i \x_mask_i
+ connect \x_addr_i \x_addr_i
+ connect \ldst_port0_addr_ok_o$111 \ldst_port0_addr_ok_o
+ connect \m_ld_data_o \m_ld_data_o
+ connect \ldst_port0_ld_data_o$112 \ldst_port0_ld_data_o
+ connect \ldst_port0_ld_data_o_ok$113 \ldst_port0_ld_data_o_ok
+ connect \x_busy_o \x_busy_o
+ connect \ldst_port0_st_data_i_ok$114 \ldst_port0_st_data_i_ok
+ connect \ldst_port0_st_data_i$115 \ldst_port0_st_data_i
+ connect \x_st_data_i \x_st_data_i
+ connect \ldst_port0_addr_exc_o$116 \ldst_port0_addr_exc_o
+ connect \x_ld_i \x_ld_i
+ connect \x_st_i \x_st_i
+ connect \m_valid_i \m_valid_i
+ connect \x_valid_i \x_valid_i
+ connect \ldst_port0_go_die_i \ldst_port0_go_die_i
+ connect \ldst_port0_go_die_i$117 \ldst_port0_go_die_i$110
+ connect \ldst_port0_busy_o$118 \ldst_port0_busy_o$109
+ connect \dbus__cyc \dbus__cyc
+ connect \x_stall_i \x_stall_i
+ connect \dbus__ack \dbus__ack
+ connect \dbus__err \dbus__err
+ connect \dbus__stb \dbus__stb
+ connect \dbus__dat_r \dbus__dat_r
+ connect \dbus__adr \dbus__adr
+ connect \dbus__sel \dbus__sel
+ connect \dbus__we \dbus__we
+ connect \dbus__dat_w \dbus__dat_w
+ connect \m_stall_i \m_stall_i
+ connect \m_load_err_o \m_load_err_o
+ connect \m_store_err_o \m_store_err_o
+ connect \m_badaddr_o \m_badaddr_o
+ connect \m_busy_o \m_busy_o
end
cell \imem \imem
- connect \mem_r_addr \mem_r_addr
- connect \mem_r_data \mem_r_data
+ connect \a_pc_i \a_pc_i
+ connect \a_valid_i \a_valid_i
+ connect \f_valid_i \f_valid_i
+ connect \f_busy_o \f_busy_o
+ connect \f_instr_o \f_instr_o
+ connect \rst \rst
connect \clk \clk
- connect \mem_w_en \mem_w_en
- connect \mem_w_addr \mem_w_addr
- connect \mem_w_data \mem_w_data
+ connect \ibus__cyc \ibus__cyc
+ connect \a_stall_i \a_stall_i
+ connect \ibus__ack \ibus__ack
+ connect \ibus__err \ibus__err
+ connect \ibus__stb \ibus__stb
+ connect \ibus__dat_r \ibus__dat_r
+ connect \ibus__adr \ibus__adr
+ connect \f_stall_i \f_stall_i
+ connect \f_fetch_err_o \f_fetch_err_o
+ connect \f_badaddr_o \f_badaddr_o
+ connect \a_busy_o \a_busy_o
end
process $group_0
assign \ad__go 1'0
assign \st__go \st__rel
sync init
end
- attribute \src "issuer.py:71"
+ attribute \src "simple/issuer.py:73"
wire width 64 \current_pc
- attribute \src "issuer.py:71"
+ attribute \src "simple/issuer.py:73"
wire width 64 \current_pc$next
process $group_2
assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pc_o \current_pc
sync init
end
- attribute \src "issuer.py:77"
- wire width 64 \nia$91
- attribute \src "issuer.py:78"
- wire width 65 $92
- attribute \src "issuer.py:78"
- wire width 65 $93
- attribute \src "issuer.py:78"
- cell $add $94
+ attribute \src "simple/issuer.py:79"
+ wire width 64 \nia$119
+ attribute \src "simple/issuer.py:80"
+ wire width 65 $120
+ attribute \src "simple/issuer.py:80"
+ wire width 65 $121
+ attribute \src "simple/issuer.py:80"
+ cell $add $122
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \current_pc
connect \B 3'100
- connect \Y $93
+ connect \Y $121
end
- connect $92 $93
+ connect $120 $121
process $group_3
- assign \nia$91 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \nia$91 $92 [63:0]
+ assign \nia$119 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia$119 $120 [63:0]
sync init
end
- attribute \src "issuer.py:72"
+ attribute \src "simple/issuer.py:74"
wire width 1 \pc_changed
- attribute \src "issuer.py:72"
+ attribute \src "simple/issuer.py:74"
wire width 1 \pc_changed$next
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
wire width 2 \fsm_state
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
wire width 2 \fsm_state$next
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $95
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $96
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ wire width 1 $123
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ cell $reduce_bool $124
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \core_fast_nia_wen
- connect \Y $95
+ connect \Y $123
end
process $group_4
assign \pc_changed$next \pc_changed
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
assign \pc_changed$next 1'0
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
- attribute \src "issuer.py:126"
- switch { $95 }
- attribute \src "issuer.py:126"
+ attribute \src "simple/issuer.py:136"
+ switch { $123 }
+ attribute \src "simple/issuer.py:136"
case 1'1
assign \pc_changed$next 1'1
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \pc_changed$next 1'0
sync posedge \clk
update \pc_changed \pc_changed$next
end
- attribute \src "issuer.py:95"
- wire width 64 \pc$97
+ attribute \src "simple/issuer.py:97"
+ wire width 64 \pc$125
process $group_5
- assign \pc$97 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "issuer.py:88"
+ assign \pc$125 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
- attribute \src "issuer.py:96"
+ attribute \src "simple/issuer.py:98"
switch { \pc_ok }
- attribute \src "issuer.py:96"
+ attribute \src "simple/issuer.py:98"
case 1'1
- assign \pc$97 \pc
- attribute \src "issuer.py:99"
+ assign \pc$125 \pc
+ attribute \src "simple/issuer.py:101"
case
- assign \pc$97 \core_d_rd1__data_o
+ assign \pc$125 \core_d_rd1__data_o
end
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
end
process $group_6
assign \core_d_rd1__ren 8'00000000
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
- attribute \src "issuer.py:96"
+ attribute \src "simple/issuer.py:98"
switch { \pc_ok }
- attribute \src "issuer.py:96"
+ attribute \src "simple/issuer.py:98"
case 1'1
- attribute \src "issuer.py:99"
+ attribute \src "simple/issuer.py:101"
case
assign \core_d_rd1__ren 8'00000001
end
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
sync init
end
process $group_7
- assign \mem_r_addr 6'000000
- attribute \src "issuer.py:88"
+ assign \a_pc_i 48'000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
- assign \mem_r_addr \pc$97 [63:2] [5:0]
+ assign \a_pc_i \pc$125 [47:0]
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
sync init
end
- attribute \src "issuer.py:70"
- wire width 32 \current_insn
process $group_8
- assign \current_insn 32'00000000000000000000000000000000
- attribute \src "issuer.py:88"
+ assign \a_valid_i 1'0
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
- assign \current_insn \mem_r_data
+ assign \a_valid_i 1'1
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \current_insn \mem_r_data
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ assign \a_valid_i 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
sync init
end
process $group_9
+ assign \f_valid_i 1'0
+ attribute \src "simple/issuer.py:90"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:93"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:95"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:95"
+ case 1'1
+ assign \f_valid_i 1'1
+ end
+ attribute \src "simple/issuer.py:115"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ assign \f_valid_i 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ end
+ attribute \src "simple/issuer.py:132"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ end
+ sync init
+ end
+ process $group_10
assign \current_pc$next \current_pc
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
- assign \current_pc$next \pc$97
+ assign \current_pc$next \pc$125
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \current_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
update \current_pc \current_pc$next
end
- attribute \src "issuer.py:128"
- wire width 1 $98
- attribute \src "issuer.py:128"
- cell $not $99
+ attribute \src "simple/issuer.py:138"
+ wire width 1 $126
+ attribute \src "simple/issuer.py:138"
+ cell $not $127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $98
+ connect \Y $126
end
- process $group_10
+ process $group_11
assign \fsm_state$next \fsm_state
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
switch { \go_insn_i }
- attribute \src "issuer.py:93"
+ attribute \src "simple/issuer.py:95"
case 1'1
assign \fsm_state$next 2'01
end
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \fsm_state$next 2'10
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \fsm_state$next 2'10
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
- attribute \src "issuer.py:128"
- switch { $98 }
- attribute \src "issuer.py:128"
+ attribute \src "simple/issuer.py:138"
+ switch { $126 }
+ attribute \src "simple/issuer.py:138"
case 1'1
assign \fsm_state$next 2'00
end
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \fsm_state$next 2'00
sync posedge \clk
update \fsm_state \fsm_state$next
end
- process $group_11
+ attribute \src "simple/issuer.py:72"
+ wire width 32 \current_insn
+ attribute \src "simple/issuer.py:122"
+ wire width 32 $128
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
+ wire width 7 $129
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
+ cell $mul $130
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 7
+ connect \A \current_pc [2]
+ connect \B 6'100000
+ connect \Y $129
+ end
+ attribute \src "simple/issuer.py:122"
+ cell $shift $131
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 32
+ connect \A \f_instr_o
+ connect \B $129
+ connect \Y $128
+ end
+ process $group_12
+ assign \current_insn 32'00000000000000000000000000000000
+ attribute \src "simple/issuer.py:90"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:93"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:115"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \current_insn $128
+ end
+ attribute \src "simple/issuer.py:132"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ end
+ sync init
+ end
+ process $group_13
assign \valid 1'0
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \valid 1'1
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \valid 1'1
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
assign \valid 1'1
end
sync init
end
- process $group_12
+ process $group_14
assign \core_issue_i 1'0
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \core_issue_i 1'1
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \core_issue_i 1'1
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
sync init
end
- process $group_13
+ process $group_15
assign \bigendian 1'0
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \bigendian 1'0
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \bigendian 1'0
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
sync init
end
- attribute \src "issuer.py:74"
+ attribute \src "simple/issuer.py:76"
wire width 32 \ilatch
- attribute \src "issuer.py:74"
+ attribute \src "simple/issuer.py:76"
wire width 32 \ilatch$next
- process $group_14
+ process $group_16
assign \raw_opcode_in 32'00000000000000000000000000000000
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \raw_opcode_in \current_insn
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \raw_opcode_in \current_insn
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
assign \raw_opcode_in \ilatch
end
sync init
end
- process $group_15
+ process $group_17
assign \ilatch$next \ilatch
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- assign \ilatch$next \current_insn
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:116"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:116"
+ case 1'1
+ attribute \src "simple/issuer.py:120"
+ case
+ assign \ilatch$next \current_insn
+ end
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
end
- attribute \src "/dsk/l1/jpc/coriolis-2.x/src/nmigen/nmigen/hdl/xfrm.py:519"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \ilatch$next 32'00000000000000000000000000000000
sync posedge \clk
update \ilatch \ilatch$next
end
- attribute \src "issuer.py:128"
- wire width 1 $100
- attribute \src "issuer.py:128"
- cell $not $101
+ attribute \src "simple/issuer.py:138"
+ wire width 1 $132
+ attribute \src "simple/issuer.py:138"
+ cell $not $133
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $100
+ connect \Y $132
end
- attribute \src "issuer.py:134"
- wire width 1 $102
- attribute \src "issuer.py:134"
- cell $not $103
+ attribute \src "simple/issuer.py:144"
+ wire width 1 $134
+ attribute \src "simple/issuer.py:144"
+ cell $not $135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $102
+ connect \Y $134
end
- process $group_16
+ process $group_18
assign \core_wen 8'00000000
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
- attribute \src "issuer.py:128"
- switch { $100 }
- attribute \src "issuer.py:128"
+ attribute \src "simple/issuer.py:138"
+ switch { $132 }
+ attribute \src "simple/issuer.py:138"
case 1'1
- attribute \src "issuer.py:134"
- switch { $102 }
- attribute \src "issuer.py:134"
+ attribute \src "simple/issuer.py:144"
+ switch { $134 }
+ attribute \src "simple/issuer.py:144"
case 1'1
assign \core_wen 8'00000001
end
end
sync init
end
- attribute \src "issuer.py:128"
- wire width 1 $104
- attribute \src "issuer.py:128"
- cell $not $105
+ attribute \src "simple/issuer.py:138"
+ wire width 1 $136
+ attribute \src "simple/issuer.py:138"
+ cell $not $137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $104
+ connect \Y $136
end
- attribute \src "issuer.py:134"
- wire width 1 $106
- attribute \src "issuer.py:134"
- cell $not $107
+ attribute \src "simple/issuer.py:144"
+ wire width 1 $138
+ attribute \src "simple/issuer.py:144"
+ cell $not $139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $106
+ connect \Y $138
end
- process $group_17
+ process $group_19
assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "issuer.py:88"
+ attribute \src "simple/issuer.py:90"
switch \fsm_state
- attribute \src "issuer.py:91"
+ attribute \src "simple/issuer.py:93"
attribute \nmigen.decoding "IDLE/0"
case 2'00
- attribute \src "issuer.py:112"
+ attribute \src "simple/issuer.py:115"
attribute \nmigen.decoding "INSN_READ/1"
case 2'01
- attribute \src "issuer.py:122"
+ attribute \src "simple/issuer.py:132"
attribute \nmigen.decoding "INSN_ACTIVE/2"
case 2'10
- attribute \src "issuer.py:128"
- switch { $104 }
- attribute \src "issuer.py:128"
+ attribute \src "simple/issuer.py:138"
+ switch { $136 }
+ attribute \src "simple/issuer.py:138"
case 1'1
- attribute \src "issuer.py:134"
- switch { $106 }
- attribute \src "issuer.py:134"
+ attribute \src "simple/issuer.py:144"
+ switch { $138 }
+ attribute \src "simple/issuer.py:144"
case 1'1
- assign \core_data_i \nia$91
+ assign \core_data_i \nia$119
end
end
end
projects / soclayout.git / commitdiff