pass and lock immediate in

diff --git a/libreriscv b/libreriscv
index 999e7155eb5811b4fae733aa63328ca07a4da3d3..29219bd53d45768c6f57a876a78c5758b29bd7d1 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 999e7155eb5811b4fae733aa63328ca07a4da3d3
+Subproject commit 29219bd53d45768c6f57a876a78c5758b29bd7d1

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index d0fe6aa392103faea31878418ed801cc744e3a22..0937b0160c1b23935451b0917307289cb50833e1 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -57,7 +57,6 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # operation / data input
         self.oper_i = CompALUOpSubset() # operand
-        self.imm_i =  self.oper_i.imm_data      # immediate in
         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
 
@@ -109,11 +108,12 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # select immediate if opcode says so.  however also change the latch
         # to trigger *from* the opcode latch instead.
-        op_is_imm = self.imm_i.imm_ok
+        op_is_imm = oper_r.imm_data.imm_ok
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)
         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q))
-        m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i.imm, self.src2_i))
+        m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm,
+                                                  self.src2_i))
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
@@ -168,16 +168,14 @@ class ComputationUnitNoDelay(Elaboratable):
 
 
 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
-    yield dut.issue_i.eq(1)
-    yield
     yield dut.issue_i.eq(0)
     yield
     yield dut.src1_i.eq(a)
     yield dut.src2_i.eq(b)
     yield dut.oper_i.insn_type.eq(op)
     yield dut.oper_i.invert_a.eq(inv_a)
-    yield dut.imm_i.imm.eq(imm)
-    yield dut.imm_i.imm_ok.eq(imm_ok)
+    yield dut.oper_i.imm_data.imm.eq(imm)
+    yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index a96f90a8f9753dde7d60fc07707afef40a740562..1c725b25798a56e12967a04bbbff78a5b56d968d 100644 (file)
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -36,6 +36,7 @@ class RegSim:
         self.regs = [0] * nregs
 
     def op(self, op, op_imm, imm, src1, src2, dest):
+        print ("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
         maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1] & maxbits
         if op_imm: