make interface_decl usage generic

diff --git a/src/interface_decl.py b/src/interface_decl.py
index c6da931d7a07a1f6d419f0a7da4d52e7cd9bffe1..7bad1580cb023ebbad50235df2fab746f67395c0 100644 (file)
--- a/src/interface_decl.py
+++ b/src/interface_decl.py
@@ -1,5 +1,6 @@
 from UserDict import UserDict
 
+from wire_def import generic_io # special case
 
 class Pin(object):
     """ pin interface declaration.
@@ -168,6 +169,9 @@ class IOInterface(Interface):
     def ifacefmtinfn(self, name):
         return "cell{0}_mux_in"
 
+    def wirefmt(self, *args):
+        return generic_io.format(*args)
+
 
 class Interfaces(UserDict):
     """ contains a list of interface definitions
@@ -186,8 +190,10 @@ class Interfaces(UserDict):
                 spec = self.read_spec(name)
                 self.ifaceadd(name, count, Interface(name, spec))
 
-    def ifaceadd(self, name, count, iface):
-        self.ifacecount.append((name, count))
+    def ifaceadd(self, name, count, iface, at=None):
+        if at is None:
+            at = len(self.ifacecount)
+        self.ifacecount.insert(at, (name, count))
         self[name] = iface
 
     def read_spec(self, name):

diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py
index fa7e3a7a617e2547004f4f753d39152c2a76f91d..3669e32375d971c40ab3ee297e791ad29b54a22f 100644 (file)
--- a/src/pinmux_generator.py
+++ b/src/pinmux_generator.py
@@ -31,7 +31,7 @@ from bus_transactors import axi4_lite
 p = Parse()
 init(p)
 ifaces = Interfaces()
-#ifaces.ifaceadd('io', p.N_IO, io_interface)
+ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
 
 if not os.path.exists("bsv_src"):
     os.makedirs("bsv_src")
@@ -92,10 +92,6 @@ with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
       // declare the interface to the IO cells.
       // Each IO cell will have 8 input field (output from pin mux
       // and on output field (input to pinmux)''')
-    for i in range(0, p.N_IO):
-        bsv_file.write('''\n      // interface declaration between IO-{0} and pinmux'''.format(i))
-
-        bsv_file.write(io_interface.ifacefmt(i))
     # ==============================================================
 
     # == create method definitions for all peripheral interfaces ==#
@@ -125,11 +121,6 @@ with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
         bsv_file.write(muxwire.format(
             cell[0], int(math.log(len(cell) - 1, 2))))
 
-    bsv_file.write(
-        '''\n      // following wires capture the values sent to the IO Cell''')
-    for i in range(0, p.N_IO):
-        bsv_file.write(generic_io.format(i))
-
     ifaces.wirefmt(bsv_file)
 
     bsv_file.write("\n")
@@ -154,8 +145,6 @@ with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
     endinterface;
     interface peripheral_side = interface PeripheralSide
 ''')
-    for i in range(0, p.N_IO):
-        bsv_file.write(io_interface.ifacedef(i))
     ifaces.ifacedef(bsv_file)
     bsv_file.write(footer)
     print("BSV file successfully generated: bsv_src/pinmux.bsv")

diff --git a/src/wire_def.py b/src/wire_def.py
index f02ce3ca455ad0edb3be1094986b96f5c14e8235..5b85f7f180371b9798547c7f314b69962c20b779 100644 (file)
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -1,4 +1,4 @@
-# == Intermediate wire definitions ==#
+# == Intermediate wire definitions, special cases ==#
 muxwire = '''
       Wire#(Bit#({1})) wrcell{0}_mux<-mkDWire(0);'''
 generic_io = '''