still experimenting with async FF sync

diff --git a/src/soc/experiment/test/async_sim.py b/src/soc/experiment/test/async_sim.py
index 8ca20dc34495c81338bfdc5dedded9714f9be3b3..62ee0dff9418fae71fc0bb519a8223bf071a7193 100644 (file)
--- a/src/soc/experiment/test/async_sim.py
+++ b/src/soc/experiment/test/async_sim.py
@@ -12,7 +12,7 @@ class Domain1(Elaboratable):
     def __init__(self):
         self.tick = Signal()
         self.tick_clear_wait = Signal()
-        self.counter = Signal(8)
+        self.counter = Signal(64)
         self.rst = Signal()
 
     def elaborate(self, platform):
@@ -33,7 +33,7 @@ class Domain1(Elaboratable):
 # simple "counter" thing
 class Domain2(Elaboratable):
     def __init__(self):
-        self.counter = Signal(8)
+        self.counter = Signal(64)
         self.rst = Signal()
 
     def elaborate(self, platform):
@@ -64,7 +64,8 @@ class AsyncThing(Elaboratable):
         comb += core_sync.clk.eq(self.core_clk) # driven externally
         comb += core.rst.eq(ResetSignal())
 
-        m.submodules += AsyncFFSynchronizer(self.core_tick, core.tick)
+        m.submodules += AsyncFFSynchronizer(self.core_tick, core.tick,
+                                            domain="coresync")
 
         return m
 
@@ -86,11 +87,15 @@ def async_sim_clk(dut):
         yield Tick("sync")
         yield Tick("sync")
         yield Tick("sync")
+        yield Tick("sync")
+        yield Tick("sync")
         yield dut.core_clk.eq(0)
         yield Tick("sync")
         yield Tick("sync")
         yield Tick("sync")
         yield Tick("sync")
+        yield Tick("sync")
+        yield Tick("sync")
 
     counter = yield dut.core2.counter
     print ("async counter", counter)