another major bug, CacheTagArray valid was only 1 bit not NUM_WAYS

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index b3b3fd57b954b7c24e8443bbaa39e0d9ab14a7bb..3460e9768a886269596d919cce05e904916adb60 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -162,7 +162,7 @@ print ("    TAG_WIDTH", TAG_WIDTH)
 print ("     NUM_WAYS", NUM_WAYS)
 
 def CacheTagArray():
-    tag_layout = [('valid', 1),
+    tag_layout = [('valid', NUM_WAYS),
                   ('tag', TAG_RAM_WIDTH),
                  ]
     return Array(Record(tag_layout, name="tag%d" % x) for x in range(NUM_LINES))