sort out pad/core link

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index 353633d77ba427b1adf0270a060f057a39805646..65c280ac61d97681a493a456da7b9b7ffaccf90f 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -259,8 +259,7 @@ class ASICPlatform(TemplatedPlatform):
             # work out which bleeding way round what the hell is
             # connected to what.
             m.d.comb += io.pad.i.eq(self._invert_if(invert, port))
-            m.d.comb += pin.i.eq(io.pad.i)
-            m.d.comb += io.core.i.eq(pin.i)
+            m.d.comb += pin.i.eq(io.core.i)
         else: # simple pass-through from port to pin
             print("No JTAG chain in-between")
             m.d.comb += pin.i.eq(self._invert_if(invert, port))