update comments

diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py
index 9640c58a963d156b1289016ce3a410fb3413c547..1a4a2d66727c94911fffd4936ee5483d987b9b99 100644 (file)
--- a/src/soc/litex/sim.py
+++ b/src/soc/litex/sim.py
@@ -63,7 +63,7 @@ class SoCSMP(SoCCore):
 
         # SoCCore --------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
-            cpu_type                 = "microwatt", # XXX use None for now libre_soc
+            cpu_type                 = "microwatt", # XXX use microwatt
             cpu_variant              = cpu_variant,
             cpu_cls                  = LibreSOC,
             uart_name                = "sim",