self.ready = Signal(reset=True)
self.width = self.z0.width
- self.iterations = self.width - 1
+ self.iterations = self.fracbits - 1
def elaborate(self, platform):
m = Module()
yield
yield start.eq(0)
yield
- for i in range(fracbits * 3):
+ for i in range(dut.fracbits+1):
rdy = yield ready
zo = yield dut.z_out
if rdy and not asserted:
diff = abs(real_sin - expected_sin)
print(f"{real_sin} {expected_sin} {diff}")
self.assertTrue(diff < 0.001)
+ real_cos = yield dut.cos
+ real_cos = self.get_frac(real_cos, dut.cos.width - 2)
+ diff = abs(real_cos - expected_cos)
+ print(f"{real_cos} {expected_cos} {diff}")
+ self.assertTrue(diff < 0.001)
yield