bring out XICS ICS interrupt levels so that they can be wired to peripherals

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ea76bbe14c0c0c9629fc9ed1b510d356414c140a..a60bf38a4a4744580d0e5eb6145bd01ecef2048d 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -49,6 +49,7 @@ class TestIssuer(Elaboratable):
         if self.xics:
             self.xics_icp = XICS_ICP()
             self.xics_ics = XICS_ICS()
+            self.int_level_i = self.xics_ics.int_level_i
 
         # main instruction core
         self.core = core = NonProductionCore(pspec)
@@ -325,6 +326,7 @@ class TestIssuer(Elaboratable):
         if self.xics:
             ports += list(self.xics_icp.bus.fields.values())
             ports += list(self.xics_ics.bus.fields.values())
+            ports.append(self.int_level_i)
 
         return ports