sorting out fast/spr naming

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 40dd718ca264fad595f13d99d3e12fe259143cb6..8de4191c8d968282ddd54cc1578526b313841526 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -293,12 +293,13 @@ class CROutSel(Enum):
 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 
 spr_csv = get_csv("sprs.csv")
-spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
+spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 spr_dict = {}
 spr_byname = {}
 for row in spr_csv:
     info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
-                    priv_mfspr=row['priv_mfspr'], length=int(row['len']))
+                    priv_mfspr=row['priv_mfspr'], length=int(row['len']),
+                    idx=int(row['Idx']))
     spr_dict[int(row['Idx'])] = info
     spr_byname[row['SPR']] = info
 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index a14e2277b17f8c160e05b38b3fbe1bcbcc0e5775..9cc8ec9217bf6e342e42926103d41509da8da6e7 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -46,7 +46,7 @@ class ALUHelpers:
             fast1_sel = yield dec2.e.read_fast1.data
             spr1_sel = fast_reg_to_spr(fast1_sel)
             spr1_data = sim.spr[spr1_sel].value
-            res['spr1'] = spr1_data
+            res['fast1'] = spr1_data
 
     def get_sim_fast_spr2(res, sim, dec2):
         fast2_en = yield dec2.e.read_fast2.ok
@@ -54,7 +54,7 @@ class ALUHelpers:
             fast2_sel = yield dec2.e.read_fast2.data
             spr2_sel = fast_reg_to_spr(fast2_sel)
             spr2_data = sim.spr[spr2_sel].value
-            res['spr2'] = spr2_data
+            res['fast2'] = spr2_data
 
     def get_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.read_cr1.ok
@@ -135,14 +135,22 @@ class ALUHelpers:
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
 
-    def set_fast_spr1(alu, dec2, inp):
+    def set_slow_spr1(alu, dec2, inp):
         if 'spr1' in inp:
             yield alu.p.data_i.spr1.eq(inp['spr1'])
 
-    def set_fast_spr2(alu, dec2, inp):
+    def set_slow_spr2(alu, dec2, inp):
         if 'spr2' in inp:
             yield alu.p.data_i.spr2.eq(inp['spr2'])
 
+    def set_fast_spr1(alu, dec2, inp):
+        if 'fast1' in inp:
+            yield alu.p.data_i.fast1.eq(inp['fast1'])
+
+    def set_fast_spr2(alu, dec2, inp):
+        if 'fast2' in inp:
+            yield alu.p.data_i.fast2.eq(inp['fast2'])
+
     def set_cr_a(alu, dec2, inp):
         if 'cr_a' in inp:
             yield alu.p.data_i.cr_a.eq(inp['cr_a'])
@@ -161,16 +169,26 @@ class ALUHelpers:
         else:
             yield alu.p.data_i.full_cr.eq(0)
 
-    def get_fast_spr1(res, alu, dec2):
+    def get_slow_spr1(res, alu, dec2):
         spr1_valid = yield alu.n.data_o.spr1.ok
         if spr1_valid:
             res['spr1'] = yield alu.n.data_o.spr1.data
 
-    def get_fast_spr2(res, alu, dec2):
+    def get_slow_spr2(res, alu, dec2):
         spr2_valid = yield alu.n.data_o.spr2.ok
         if spr2_valid:
             res['spr2'] = yield alu.n.data_o.spr2.data
 
+    def get_fast_spr1(res, alu, dec2):
+        spr1_valid = yield alu.n.data_o.fast1.ok
+        if spr1_valid:
+            res['fast1'] = yield alu.n.data_o.fast1.data
+
+    def get_fast_spr2(res, alu, dec2):
+        spr2_valid = yield alu.n.data_o.fast2.ok
+        if spr2_valid:
+            res['fast2'] = yield alu.n.data_o.fast2.data
+
     def get_cia(res, alu, dec2):
         res['cia'] = yield alu.p.data_i.cia
 
@@ -240,7 +258,7 @@ class ALUHelpers:
             spr_num = yield dec2.e.write_fast2.data
             spr_num = fast_reg_to_spr(spr_num)
             spr_name = spr_dict[spr_num]
-            res['spr2'] = sim.spr[spr_name]
+            res['fast2'] = sim.spr[spr_name]
 
     def get_wr_fast_spr1(res, sim, dec2):
         ok = yield dec2.e.write_fast1.ok
@@ -248,7 +266,7 @@ class ALUHelpers:
             spr_num = yield dec2.e.write_fast1.data
             spr_num = fast_reg_to_spr(spr_num)
             spr_name = spr_dict[spr_num]
-            res['spr1'] = sim.spr[spr_name]
+            res['fast1'] = sim.spr[spr_name]
 
     def get_wr_sim_xer_ca(res, sim, dec2):
         cry_out = yield dec2.e.output_carry