debug fpmul pipeline

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index 9c238cf40d182b58455c1b15f95546a33b8138c9..9e82626763a91c5e02ba7f290fbe9d6c359b0165 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -10,7 +10,6 @@ from .mul0 import FPMulStage0Data
 
 class FPMulStage1Mod(FPState, Elaboratable):
     """ Second stage of mul: preparation for normalisation.
-        detects when tot sum is too big (tot[27] is kinda a carry bit)
     """
 
     def __init__(self, width, id_wid):
@@ -39,15 +38,14 @@ class FPMulStage1Mod(FPState, Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.o.z.eq(self.i.z)
-        # tot[-1] (MSB) gets set when the sum overflows. shift result down
         with m.If(~self.i.out_do_z):
             mw = self.o.z.m_width
             m.d.comb += [
                 self.o.z.m.eq(self.i.product[mw+2:]),
-                self.o.of.m0.eq(self.i.tot[mw+2]),
-                self.o.of.guard.eq(self.i.tot[mw+1]),
-                self.o.of.round_bit.eq(self.i.tot[mw]),
-                self.o.of.sticky.eq(self.i.tot[0:mw].bool())
+                self.o.of.m0.eq(self.i.product[mw+2]),
+                self.o.of.guard.eq(self.i.product[mw+1]),
+                self.o.of.round_bit.eq(self.i.product[mw]),
+                self.o.of.sticky.eq(self.i.product[0:mw].bool())
             ]
 
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index 0f49a37dd139cbad9d1f4b5e3918f3e5201fbfe0..d0612ac7a98276c95d90202e7c3cf11a26e003d0 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -15,7 +15,7 @@ from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPMulSpecialCasesDeNorm
-from .addstages import FPMulStages
+from .mulstages import FPMulStages
 
 
 
@@ -41,7 +41,7 @@ class FPMULMuxInOut(ReservationStations):
     """ Reservation-Station version of FPMUL pipeline.
 
         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 3-stage adder pipeline
+        * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
         Fan-in and Fan-out are combinatorial.

diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index fec43fabeae7351a224528d6848f3ad32e0827f6..92dd75afc17a1869d551d8dd97753ce66397f02e 100644 (file)
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -73,6 +73,9 @@ class FPMulSpecialCasesMod:
         sabx = Signal(reset_less=True)   # sign a xor b (sabx, get it?)
         m.d.comb += sabx.eq(a1.s ^ b1.s)
 
+        abnan = Signal(reset_less=True)
+        m.d.comb += abnan.eq(a1.is_nan | b1.is_nan)
+
         # if a is NaN or b is NaN return NaN
         with m.If(abnan):
             m.d.comb += self.o.out_do_z.eq(1)