Start of a GTKWave document for the LDST CompUnit parallel unit test

diff --git a/src/soc/experiment/test/test_compldst_multi.py b/src/soc/experiment/test/test_compldst_multi.py
index 1f2125148e79be395cf5cb0c04cd438bd991e33a..5bb3c6ee78ff9a7adeaf5bb1ac76454ee5233309 100644 (file)
--- a/src/soc/experiment/test/test_compldst_multi.py
+++ b/src/soc/experiment/test/test_compldst_multi.py
@@ -4,6 +4,7 @@
 import unittest
 from nmigen import Module
 from nmigen.sim import Simulator
+from nmutil.gtkw import write_gtkw
 
 from openpower.consts import MSR
 from openpower.decoder.power_enums import MicrOp, LDSTMode
@@ -54,11 +55,12 @@ class TestLDSTCompUnit(unittest.TestCase):
         m = Module()
         pi = PortInterface(name="pi")
         regspec = LDSTPipeSpec.regspec
-        dut = LDSTCompUnit(pi, regspec)
+        dut = LDSTCompUnit(pi, regspec, name="ldst")
         m.submodules.dut = dut
         sim = Simulator(m)
         sim.add_clock(1e-6)
         op = OpSim(dut)
+        self.write_gtkw()
 
         def process():
             yield from op.issue(MicrOp.OP_STORE)
@@ -68,6 +70,25 @@ class TestLDSTCompUnit(unittest.TestCase):
         with sim_writer:
             sim.run()
 
+    @classmethod
+    def write_gtkw(cls):
+        traces = [
+            'clk',
+            ('operation', [
+                ('oper_i_ldst__insn_type', {'display': 'insn_type'}),
+                ('oper_i_ldst__ldst_mode', {'display': 'ldst_mode'}),
+                ('oper_i_ldst__zero_a', {'display': 'zero_a'}),
+                ('oper_i_ldst__imm_data__ok', {'display': 'imm_data_ok'}),
+                ('oper_i_ldst__imm_data__data[63:0]',
+                 {'display': 'imm_data_data', 'base': 'dec'})
+            ]),
+            ('cu_issue_i', {'display': 'issue_i'}),
+            ('cu_busy_o', {'display': 'busy_o'})
+        ]
+        write_gtkw("test_ldst_compunit.gtkw",
+                   "test_ldst_compunit.vcd",
+                   traces, module="top.dut")
+
 
 if __name__ == '__main__':
     unittest.main()