from soc.debug.jtagutils import (jtag_read_write_reg,
jtag_srv, jtag_set_reset,
jtag_set_ir, jtag_set_get_dr)
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
def test_pinset():
return {
from nmigen.asserts import Assert, AnyConst, Assume
from nmutil.formaltest import FHDLTestCase
-from soc.decoder.power_decoder import create_pdecode, PowerOp
-from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
+from openpower.decoder.power_decoder import create_pdecode, PowerOp
+from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form, Function,
LdstLen, CryIn,
MicrOp, SPR, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2,
+from openpower.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
import pdb
from nmigen.asserts import Assert, AnyConst
from nmutil.formaltest import FHDLTestCase
-from soc.decoder.power_decoder import create_pdecode, PowerOp
-from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
+from openpower.decoder.power_decoder import create_pdecode, PowerOp
+from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form,
MicrOp, SPR)
-from soc.decoder.power_decoder2 import (PowerDecode2,
+from openpower.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
import unittest
-from soc.decoder.selectable_int import SelectableInt, onebit
+from openpower.decoder.selectable_int import SelectableInt, onebit
from nmutil.divmod import trunc_divs, trunc_rems
from operator import floordiv, mod
-from soc.decoder.selectable_int import selectltu as ltu
-from soc.decoder.selectable_int import selectgtu as gtu
-from soc.decoder.selectable_int import check_extsign
+from openpower.decoder.selectable_int import selectltu as ltu
+from openpower.decoder.selectable_int import selectgtu as gtu
+from openpower.decoder.selectable_int import check_extsign
trunc_div = floordiv
trunc_rem = mod
from nmigen.back.pysim import Settle
from functools import wraps
from copy import copy
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
+from openpower.decoder.orderedset import OrderedSet
+from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
selectconcat)
-from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
+from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
insns, MicrOp, In1Sel, In2Sel, In3Sel,
OutSel, CROutSel,
SVP64RMMode, SVP64PredMode,
SVP64PredInt, SVP64PredCR)
-from soc.decoder.power_enums import SVPtype
+from openpower.decoder.power_enums import SVPtype
-from soc.decoder.helpers import exts, gtu, ltu, undefined
+from openpower.decoder.helpers import exts, gtu, ltu, undefined
from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
from soc.consts import SVP64CROffs
-from soc.decoder.power_svp64 import SVP64RM, decode_extra
+from openpower.decoder.power_svp64 import SVP64RM, decode_extra
-from soc.decoder.isa.radixmmu import RADIX
-from soc.decoder.isa.mem import Mem, swap_order
+from openpower.decoder.isa.radixmmu import RADIX
+from openpower.decoder.isa.mem import Mem, swap_order
from collections import namedtuple
import math
import astor
import ast
-from soc.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder import create_pdecode
from nmigen.back.pysim import Simulator, Delay
from nmigen import Module, Signal
-from soc.decoder.pseudo.parser import GardenSnakeCompiler
-from soc.decoder.selectable_int import SelectableInt, selectconcat
-from soc.decoder.isa.caller import GPR, Mem
+from openpower.decoder.pseudo.parser import GardenSnakeCompiler
+from openpower.decoder.selectable_int import SelectableInt, selectconcat
+from openpower.decoder.isa.caller import GPR, Mem
####### Test code #######
print("args", args)
print("-->", " ".join(map(str, args)))
- from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
+ from openpower.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,
trunc_div, trunc_rem)
d = {}
"""
from nmigen import Const
from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import CryIn
def regspec_decode_read(e, regfile, name):
# Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
# Funded by NLnet http://nlnet.nl
-from soc.decoder.power_enums import get_csv, find_wiki_dir
+from openpower.decoder.power_enums import get_csv, find_wiki_dir
import os
# identifies register by type
from nmutil.util import sel
-from soc.decoder.power_enums import (SVEXTRA, SVEtype)
+from openpower.decoder.power_enums import (SVEXTRA, SVEtype)
from soc.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field,
SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
"""
from nmigen import Elaboratable, Module, Signal, Const
-from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
+from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
SVP64PredMode, SVP64sat)
from soc.consts import EXTRA3, SVP64MODE
from soc.sv.svp64 import SVP64Rec
# Modifications for inclusion in PLY distribution
from copy import copy
from ply import lex
-from soc.decoder.selectable_int import SelectableInt
+from openpower.decoder.selectable_int import SelectableInt
# I implemented INDENT / DEDENT generation as a post-processing filter
import astor
from copy import deepcopy
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.pseudo.lexer import IndentLexer
-from soc.decoder.orderedset import OrderedSet
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.pseudo.lexer import IndentLexer
+from openpower.decoder.orderedset import OrderedSet
# I use the Python AST
#from compiler import ast
from nmutil.formaltest import FHDLTestCase
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
get_signal_name, get_csv)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.gas import get_assembled_instruction
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.gas import get_assembled_instruction
import random
from nmigen.cli import rtlil
import os
import unittest
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, MicrOp,
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
CRInSel, CROutSel,
OutSel, RC, LdstLen, CryIn,
from nmutil.sim_tmp_alternative import (Simulator, nmigen_sim_top_module,
is_engine_pysim)
-from soc.decoder.decode2execute1 import Data
-from soc.decoder.power_enums import MicrOp, Function, CryIn
+from openpower.decoder.decode2execute1 import Data
+from openpower.decoder.power_enums import MicrOp, Function, CryIn
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.cr.cr_input_record import CompCROpSubset
from nmigen import Module, Signal, Mux, Elaboratable
from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
from soc.experiment.alu_hier import CompALUOpSubset
def test_scoreboard():
from alu_hier import ALU
- from soc.decoder.power_decoder2 import Decode2ToExecute1Type
+ from openpower.decoder.power_decoder2 import Decode2ToExecute1Type
alu = ALU(16)
dut = ComputationUnitNoDelay(16, alu)
from soc.experiment.pimem import LDSTException
from soc.fu.regspec import RegSpecAPI
-from soc.decoder.power_enums import MicrOp, Function, LDSTMode
+from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
class LDSTCompUnitRecord(CompUnitRecord):
from nmigen.hdl.rec import Record, Layout
from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
from soc.regfile.regfile import ortreereduce
from nmutil.util import treereduce
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
#from nmutil.picker import PriorityPicker
from nmigen.lib.coding import PriorityEncoder
from soc.scoreboard.addr_split import LDSTSplitter
from nmutil.latch import SRLatch, latchregister
from nmutil.util import rising_edge
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
from soc.scoreboard.addr_match import LenExpand
from soc.experiment.mem_types import LDSTException
from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
-from soc.decoder.power_enums import MicrOp, Function
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
+from openpower.decoder.power_enums import MicrOp, Function
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.simulator.program import Program
from nmutil.latch import SRLatch
from soc.experiment.alu_hier import ALU, BranchALU
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp, Function
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_decoder2 import Decode2ToExecute1Type
+from openpower.decoder.power_enums import MicrOp, Function
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_decoder2 import Decode2ToExecute1Type
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from nmutil.latch import SRLatch
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from random import randint, seed
from copy import deepcopy
from soc.fu.cr.cr_input_record import CompCROpSubset
from soc.experiment.alu_hier import ALU, DummyALU
from soc.experiment.compalu_multi import MultiCompUnit
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from nmutil.gtkw import write_gtkw
from nmigen import Module, Signal
from nmigen.cli import rtlil
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import MicrOp, Function, CryIn
+from openpower.decoder.power_enums import MicrOp, Function, CryIn
from nmigen.hdl.rec import Layout
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.alu.main_stage import ALUMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.alu.output_stage import ALUOutputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from nmutil.extend import exts, extz
from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
# microwatt calc_ov function.
from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
from soc.fu.common_output_stage import CommonOutputStage
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
class ALUOutputStage(CommonOutputStage):
from soc.fu.test.common import (TestAccumulatorBase, skip_case)
from soc.config.endian import bigendian
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import SVP64State
+from openpower.simulator.program import Program
+from openpower.decoder.isa.caller import SVP64State
from soc.sv.trans.svp64 import SVP64Asm
from soc.fu.alu.pipeline import ALUBasePipe
from soc.fu.test.common import (TestCase, TestAccumulatorBase, ALUHelpers)
from soc.config.endian import bigendian
-from soc.decoder.isa.all import ISA
-from soc.simulator.program import Program
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.isa.caller import special_sprs
+from openpower.decoder.isa.all import ISA
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.isa.caller import special_sprs
import unittest
from nmigen.cli import rtlil
from nmutil.formaltest import FHDLTestCase
from soc.fu.base_input_record import CompOpSubsetBase
from nmigen.hdl.rec import Layout
-from soc.decoder.power_enums import MicrOp, Function
+from openpower.decoder.power_enums import MicrOp, Function
class CompBROpSubset(CompOpSubsetBase):
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.branch.main_stage import BranchMainStage
from soc.fu.branch.pipe_data import BranchPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from nmutil.pipemodbase import PipeModBase
from nmutil.extend import exts
from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
def br_ext(bd):
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.regfile.regfiles import FastRegs
from soc.config.endian import bigendian
# generation for subtraction, should happen here
from nmigen import (Module, Signal)
from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import MicrOp
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import CryIn
class CommonInputStage(PipeModBase):
from nmigen import (Module, Signal, Cat, Const)
from nmutil.pipemodbase import PipeModBase
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
class CommonOutputStage(PipeModBase):
from nmigen import Elaboratable, Module
from nmigen.cli import rtlil
from soc.experiment.compalu_multi import MultiCompUnit
-from soc.decoder.power_enums import Function
+from openpower.decoder.power_enums import Function
from soc.config.test.test_loadstore import TestMemPspec
# pipeline / spec imports
from soc.experiment.alu_hier import DummyALU
from soc.experiment.compalu_multi import MultiCompUnit
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
class MaskGenTestCase(FHDLTestCase):
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.alu.test.test_pipe_caller import get_cu_inputs
from soc.fu.alu.test.test_pipe_caller import ALUTestCase # creates the tests
import unittest
-from soc.decoder.power_enums import (XER_bits, Function, spr_dict, SPR)
+from openpower.decoder.power_enums import (XER_bits, Function, spr_dict, SPR)
from soc.fu.branch.test.test_pipe_caller import BranchTestCase, get_cu_inputs
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2, get_rdflags
-from soc.decoder.power_enums import Function
-from soc.decoder.isa.all import ISA
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2, get_rdflags
+from openpower.decoder.power_enums import Function
+from openpower.decoder.isa.all import ISA
from soc.experiment.compalu_multi import find_ok # hack
from soc.config.test.test_loadstore import TestMemPspec
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
# XXX bad practice: use of global variables
from soc.fu.cr.test.test_pipe_caller import get_cu_inputs
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.div.test.test_pipe_caller import get_cu_inputs
from soc.fu.div.test.test_pipe_caller import DivTestCases # creates the tests
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase, get_cu_inputs
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase,
get_cu_inputs)
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
# XXX bad practice: use of global variables
from soc.fu.shift_rot.test.test_pipe_caller import get_cu_inputs
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.spr.test.test_pipe_caller import get_cu_inputs
from soc.fu.spr.test.test_pipe_caller import SPRTestCase # creates the tests
import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
from soc.fu.trap.test.test_pipe_caller import get_cu_inputs
from soc.fu.trap.test.test_pipe_caller import TrapTestCase # creates the tests
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+from openpower.decoder.power_enums import (MicrOp, Function)
class CompCROpSubset(CompOpSubsetBase):
from soc.fu.cr.main_stage import CRMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
from nmutil.pipemodbase import PipeModBase
from soc.fu.cr.pipe_data import CRInputData, CROutputData
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
class CRMainStage(PipeModBase):
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
from nmutil.pipemodbase import PipeModBase
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
from soc.fu.div.pipe_data import (CoreInputData,
CoreInterstageData,
CoreOutputData)
from soc.fu.logical.main_stage import LogicalMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.logical.pipe_data import LogicalInputData
from soc.fu.div.pipe_data import DivMulOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
from soc.fu.div.pipe_data import CoreOutputData
from nmutil.pipemodbase import PipeModBase
from soc.fu.div.pipe_data import DivInputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
from soc.fu.div.pipe_data import CoreInputData
from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation
from nmutil.util import eq32
# Also, check out the cxxsim nmigen branch, and latest yosys from git
from nmutil.sim_tmp_alternative import Simulator, Delay
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import XER_bits, Function
-from soc.decoder.isa.all import ISA
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import XER_bits, Function
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.fu.test.common import ALUHelpers
import random
import unittest
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
from soc.fu.test.common import (TestCase, TestAccumulatorBase, skip_case)
import unittest
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
from soc.fu.test.common import TestAccumulatorBase
from soc.fu.base_input_record import CompOpSubsetBase
from nmigen.hdl.rec import Layout
-from soc.decoder.power_enums import MicrOp, Function, LDSTMode
+from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
class CompLDSTOpSubset(CompOpSubsetBase):
from nmigen.back.pysim import Simulator, Delay, Settle
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.logical.main_stage import LogicalMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from nmigen.hdl.rec import Layout
-from soc.decoder.power_enums import MicrOp, Function, CryIn
+from openpower.decoder.power_enums import MicrOp, Function, CryIn
from soc.fu.base_input_record import CompOpSubsetBase
from soc.fu.logical.popcount import Popcount
from soc.fu.logical.pipe_data import LogicalOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
class LogicalMainStage(PipeModBase):
from soc.fu.logical.pipe_data import (LogicalInputData, LogicalOutputData,
LogicalOutputDataFinal)
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
class LogicalOutputStage(CommonOutputStage):
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.experiment.mmu import MMU
from soc.experiment.dcache import DCache
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import decode_spr_num
-from soc.decoder.power_enums import MicrOp, XER_bits
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_decoder2 import decode_spr_num
+from openpower.decoder.power_enums import MicrOp, XER_bits
from soc.experiment.pimem import PortInterface
from soc.experiment.pimem import PortInterfaceBase
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+from openpower.decoder.power_enums import (MicrOp, Function)
class CompMMUOpSubset(CompOpSubsetBase):
from nmigen import Module, Signal
from soc.simple.test.test_issuer import TestRunner
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
import unittest
from nmigen import Module, Signal
from soc.simple.test.test_runner import TestRunner
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
import unittest
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.consts import MSR
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.consts import MSR
from nmutil.stageapi import StageChain
from nmigen.cli import rtlil
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
from soc.fu.mul.pipe_data import CompMULOpSubset, MulPipeSpec
from soc.fu.mul.pre_stage import MulMainStage1
from soc.fu.mul.main_stage import MulMainStage2
from soc.fu.mul.post_stage import MulMainStage3
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
import unittest
from soc.fu.base_input_record import CompOpSubsetBase
from nmigen.hdl.rec import Layout
-from soc.decoder.power_enums import MicrOp, Function, CryIn
+from openpower.decoder.power_enums import MicrOp, Function, CryIn
class CompMULOpSubset(CompOpSubsetBase):
from soc.fu.div.pipe_data import DivMulOutputData
from soc.fu.mul.pipe_data import MulOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
class MulMainStage3(PipeModBase):
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers)
import unittest
from soc.fu.mul.test.helper import MulTestHelper
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
from soc.fu.test.common import TestAccumulatorBase, skip_case
import unittest
from soc.fu.mul.test.helper import MulTestHelper
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.config.endian import bigendian
from soc.fu.test.common import (TestAccumulatorBase)
import random
from nmutil.concurrentunit import PipeContext
from nmutil.dynamicpipe import SimpleHandshakeRedir
from nmigen import Signal
-from soc.decoder.power_decoder2 import Data
+from openpower.decoder.power_decoder2 import Data
from soc.fu.regspec import get_regspec_bitwidth
from soc.fu.shift_rot.rotator import right_mask, left_mask
from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.consts import field
import unittest
from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
ShiftRotInputData)
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.fu.shift_rot.rotator import Rotator
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
class ShiftRotMainStage(PipeModBase):
from soc.fu.base_input_record import CompOpSubsetBase
from nmigen.hdl.rec import Layout
-from soc.decoder.power_enums import MicrOp, Function, CryIn
+from openpower.decoder.power_enums import MicrOp, Function, CryIn
class CompSROpSubset(CompOpSubsetBase):
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
from soc.fu.shift_rot.maskgen import MaskGen
-from soc.decoder.helpers import MASK
+from openpower.decoder.helpers import MASK
import random
import unittest
from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers
from soc.config.endian import bigendian
-from soc.decoder.isa.all import ISA
-from soc.simulator.program import Program
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.power_enums import (XER_bits, Function, CryIn)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.isa.all import ISA
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.power_enums import (XER_bits, Function, CryIn)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.isa.caller import ISACaller, special_sprs
import unittest
from nmigen.cli import rtlil
from nmigen import Module, Signal
from soc.fu.spr.pipe_data import SPRPipeSpec
from soc.fu.spr.spr_input_record import CompSPROpSubset
-from soc.decoder.power_decoder2 import decode_spr_num
-from soc.decoder.power_enums import MicrOp, SPR, XER_bits
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_decoder2 import decode_spr_num
+from openpower.decoder.power_enums import MicrOp, SPR, XER_bits
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
# use POWER numbering. sigh.
def xer_bit(name):
from nmigen import (Module, Signal, Cat)
from nmutil.pipemodbase import PipeModBase
from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
-from soc.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits
+from openpower.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import decode_spr_num
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_decoder2 import decode_spr_num
class SPRMainStage(PipeModBase):
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+from openpower.decoder.power_enums import (MicrOp, Function)
class CompSPROpSubset(CompOpSubsetBase):
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.consts import MSR
import inspect
import functools
import types
-from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
+from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict
from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr # HACK!
from soc.regfile.regfiles import XERRegs, FastRegs
from soc.consts import MSR, MSRb, PI, TT, field
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.fu.trap.main_stage import TrapMainStage
from soc.fu.trap.pipe_data import TrapPipeSpec
from nmutil.extend import exts
from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.experiment.mem_types import LDSTException
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
from soc.consts import MSR, PI, TT, field, field_slice
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ISACaller, special_sprs
+from openpower.decoder.power_decoder import (create_pdecode)
+from openpower.decoder.power_decoder2 import (PowerDecode2)
+from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.simulator.program import Program
+from openpower.decoder.isa.all import ISA
from soc.config.endian import bigendian
from soc.consts import MSR
from soc.fu.base_input_record import CompOpSubsetBase
-from soc.decoder.power_enums import (MicrOp, Function)
+from openpower.decoder.power_enums import (MicrOp, Function)
from soc.consts import TT
from soc.experiment.mem_types import LDSTException
from soc.regfile.regfile import RegFile, RegFileArray, RegFileMem
from soc.regfile.virtual_port import VirtualRegPort
-from soc.decoder.power_enums import SPRfull, SPRreduced
+from openpower.decoder.power_enums import SPRfull, SPRreduced
# "State" Regfile
from soc.regfile.regfiles import FastRegs
-from soc.decoder.power_enums import SPRfull as SPR, spr_dict
+from openpower.decoder.power_enums import SPRfull as SPR, spr_dict
# note that we can get away with using SPRfull here because the values
# (numerical values) are what is used for lookup.
from nmutil.iocontrol import RecordObject
from nmutil.nmoperator import eq, shape, cat
-from soc.decoder.power_decoder2 import Decode2ToExecute1Type
+from openpower.decoder.power_decoder2 import Decode2ToExecute1Type
class Instruction(Decode2ToExecute1Type):
from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
from nmigen.cli import rtlil
-from soc.decoder.power_decoder2 import PowerDecodeSubset
-from soc.decoder.power_regspec_map import regspec_decode_read
-from soc.decoder.power_regspec_map import regspec_decode_write
+from openpower.decoder.power_decoder2 import PowerDecodeSubset
+from openpower.decoder.power_regspec_map import regspec_decode_read
+from openpower.decoder.power_regspec_map import regspec_decode_write
from nmutil.picker import PriorityPicker
from nmutil.util import treereduce
from soc.fu.compunits.compunits import AllFunctionUnits
from soc.regfile.regfiles import RegFiles
-from soc.decoder.decode2execute1 import Decode2ToExecute1Type
-from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
-from soc.decoder.power_decoder2 import get_rdflags
-from soc.decoder.decode2execute1 import Data
+from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
+from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
+from openpower.decoder.power_decoder2 import get_rdflags
+from openpower.decoder.decode2execute1 import Data
from soc.experiment.l0_cache import TstL0CacheBuffer # test only
from soc.config.test.test_loadstore import TestMemPspec
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
from soc.config.state import CoreState
import operator
from nmigen.lib.coding import PriorityEncoder
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
-from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
-from soc.decoder.decode2execute1 import Data
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
+from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
+from openpower.decoder.decode2execute1 import Data
from soc.experiment.testmem import TestMemory # test only for instructions
from soc.regfile.regfiles import StateRegs, FastRegs
from soc.simple.core import NonProductionCore
from soc.config.test.test_loadstore import TestMemPspec
from soc.config.ifetch import ConfigFetchUnit
-from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
+from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
SVP64PredMode)
from soc.consts import (CR, SVP64CROffs)
from soc.debug.dmi import CoreDebug, DMIInterface
be done through multiple reads, extracting one relevant at a time.
later, a faster way would be to use the 32-bit-wide CR port but
this is more complex decoding, here. equivalent code used in
- ISACaller is "from soc.decoder.isa.caller import get_predcr"
+ ISACaller is "from openpower.decoder.isa.caller import get_predcr"
note: this ENTIRE FSM is not to be called when svp64 is disabled
"""
from nmutil.formaltest import FHDLTestCase
from nmigen.cli import rtlil
import unittest
-from soc.decoder.isa.caller import special_sprs
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import special_sprs
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.isa.all import ISA
# note that for testing using SPRfull should be ok here
-from soc.decoder.power_enums import SPRfull as SPR, spr_dict, Function, XER_bits
+from openpower.decoder.power_enums import SPRfull as SPR, spr_dict, Function, XER_bits
from soc.config.test.test_loadstore import TestMemPspec
-from soc.config.endian import bigendian
+from openpower.endian import bigendian
from soc.simple.core import NonProductionCore
from soc.experiment.compalu_multi import find_ok # hack
# from soc.fu.branch.test.test_pipe_caller import BranchTestCase
# from soc.fu.spr.test.test_pipe_caller import SPRTestCase
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
-from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
-# from soc.simulator.test_helloworld_sim import HelloTestCases
+from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
+# from openpower.simulator.test_helloworld_sim import HelloTestCases
if __name__ == "__main__":
-from soc.simulator.program import Program
+from openpower.simulator.program import Program
from soc.fu.test.common import TestCase
import unittest
from nmutil.formaltest import FHDLTestCase
from soc.simple.issuer import TestIssuer
-from soc.config.endian import bigendian
+from openpower.endian import bigendian
from soc.config.test.test_loadstore import TestMemPspec
from nmutil.formaltest import FHDLTestCase
from nmutil.gtkw import write_gtkw
from nmigen.cli import rtlil
-from soc.decoder.isa.caller import special_sprs, SVP64State
-from soc.decoder.isa.all import ISA
-from soc.config.endian import bigendian
+from openpower.decoder.isa.caller import special_sprs, SVP64State
+from openpower.decoder.isa.all import ISA
+from openpower.endian import bigendian
-from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_decoder2 import PowerDecode2
+from openpower.decoder.power_decoder import create_pdecode
+from openpower.decoder.power_decoder2 import PowerDecode2
from soc.regfile.regfiles import StateRegs
from soc.simple.issuer import TestIssuerInternal
import os, sys
from collections import OrderedDict
-from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
+from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
SV64P_PID_SIZE, SVP64RMFields,
SVP64RM_EXTRA2_SPEC_SIZE,
SVP64RM_EXTRA3_SPEC_SIZE,
SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
SVP64RM_ELWIDTH_SIZE)
-from soc.decoder.pseudo.pagereader import ISA
-from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
-from soc.decoder.selectable_int import SelectableInt
+from openpower.decoder.pseudo.pagereader import ISA
+from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
+from openpower.decoder.selectable_int import SelectableInt
from soc.consts import SVP64MODE
projects / soc.git / commitdiff