clarify
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 13 Sep 2020 11:39:33 +0000 (12:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 13 Sep 2020 11:39:33 +0000 (12:39 +0100)
src/unused/TLB/ariane/plru.py

index 70e212689cb783d24223c6e7f5ae7b640997ec9c..e99d56d90b8c86affac1fba9d4a5ec341406ab03 100644 (file)
@@ -23,8 +23,8 @@ class PLRU(Elaboratable):
     def __init__(self, BITS):
         self.BITS = BITS
         self.acc_en = Signal(BITS)
-        self.lru_o = Signal(BITS)
         self.acc_i = Signal()
+        self.lru_o = Signal(BITS)
 
     def elaborate(self, platform=None):
         m = Module()
@@ -49,7 +49,7 @@ class PLRU(Elaboratable):
         # endcase
 
         LOG_TLB = log2_int(self.BITS)
-        hit = Signal(self.BITS)
+        hit = Signal(self.BITS, reset_less=True)
         m.d.comb += hit.eq(Repl(self.acc_i, self.BITS) & self.acc_en)
 
         for i in range(self.BITS):