use alternative experimental class TestAddMod2

diff --git a/Makefile2 b/Makefile2
index a69d6735c5b4abbf13a2b7885d6ac8f706d2c3c9..67b4c52b9bf6cbe4131d50ce1a115ad2e378527f 100755 (executable)
--- a/Makefile2
+++ b/Makefile2
@@ -11,6 +11,7 @@
 
                  NETLISTS = $(shell cat nets2.txt)
 
+                VST_FLAGS = --vst-use-concat
 
  include ./mk/design-flow.mk
 

diff --git a/Makefile3 b/Makefile3
index 10cf7612745b7d8c0ad51ad3059f61a8868c01e4..f7f0e15ad8a130de08fdaf1223b7593af443b291 100755 (executable)
--- a/Makefile3
+++ b/Makefile3
@@ -11,6 +11,7 @@
 
                  NETLISTS = $(shell cat nets3.txt)
 
+                VST_FLAGS = --vst-use-concat
 
  include ./mk/design-flow.mk
 

diff --git a/examples/part_sig_add.py b/examples/part_sig_add.py
index 2caf2b471f5a8d5289abd2d9b73f72b3271c2d1b..b6af3b3bf01602622b809bdd2f0a1b0f4d813818 100644 (file)
--- a/examples/part_sig_add.py
+++ b/examples/part_sig_add.py
@@ -1,5 +1,5 @@
 from nmigen.cli import rtlil
-from ieee754.part.test.test_partsig import TestAddMod
+from ieee754.part.test.test_partsig import TestAddMod2
 import subprocess
 import os
 from nmigen import Signal
@@ -7,13 +7,12 @@ from nmigen import Signal
 def test():
     width = 16
     pmask = Signal(4)  # divide into 4-bits
-    module = TestAddMod(width, pmask)
+    module = TestAddMod2(width, pmask)
     sim = create_ilang(module,
                                [pmask,
                                 module.a.sig,
                                 module.b.sig,
                                 module.add_output,
-                                module.eq_output,
                                 module.ls_output,
                                 module.sub_output,
                                 module.eq_output,

diff --git a/examples/test_part_add.py b/examples/test_part_add.py
index 2e1b2341a027591ef186c6388b5e79638158298f..19527e4d0deb206fb19fd0e629f27b771c409008 100644 (file)
--- a/examples/test_part_add.py
+++ b/examples/test_part_add.py
@@ -36,6 +36,7 @@ class TestAddMod(Elaboratable):
         sync += self.add_carry_out.eq(add_carry)
 
         return m
+
 if __name__ == '__main__':
     width = 16
     pmask = Signal(3)  # divide into 4-bits
@@ -50,3 +51,15 @@ if __name__ == '__main__':
                             module.add_carry_out,
                            ],
                            "test_part_add")
+    print (dir(module))
+    add_1 = module.a.m.submodules.add_1
+    print (dir(add_1.part_pts))
+    create_ilang(add_1,
+                           [pmask,
+                            add_1.a,
+                            add_1.b,
+                            add_1.output,
+                            add_1.carry_in,
+                            add_1.carry_out,
+                           ],
+                           "test_add")

diff --git a/nets3.txt b/nets3.txt
index 82796b00662cdb89d96c8ead5e9df935f6c919ae..886cd9c00defb530859211bf18b86819067a0f11 100644 (file)
--- a/nets3.txt
+++ b/nets3.txt
@@ -1,3 +1 @@
-test_part_add
-ripple
-add1
+test_part_add add_1 ripple