make cxxsim optional and print warning

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index a8a62f1c33efbe779d7bb62a60946160e00c946f..d905f68c1405ad5c6575099cf03c834846c156bd 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -1,8 +1,15 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
-cxxsim = True
+# NOTE: to use this (set to True), at present it is necessary to check
+# out the cxxsim nmigen branch
+cxxsim = False
 if cxxsim:
-    from nmigen.sim.cxxsim import Simulator
+    try:
+        from nmigen.sim.cxxsim import Simulator
+    except ImportError:
+        print("nope, sorry, have to use nmigen cxxsim branch for now")
+        cxxsim = False
+        from nmigen.back.pysim import Simulator
 else:
     from nmigen.back.pysim import Simulator
 

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index fdb2089a989ac4f6ffb353454a420c63fd4c293b..4abdfd1207af2bb0082ca808d5160d44052dcab7 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -1,10 +1,18 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Delay, Settle
+# NOTE: to use this (set to True), at present it is necessary to check
+# out the cxxsim nmigen branch
 cxxsim = False
 if cxxsim:
-    from nmigen.sim.cxxsim import Simulator
+    try:
+        from nmigen.sim.cxxsim import Simulator
+    except ImportError:
+        print("nope, sorry, have to use nmigen cxxsim branch for now")
+        cxxsim = False
+        from nmigen.back.pysim import Simulator
 else:
     from nmigen.back.pysim import Simulator
+
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest