missing ports from issuer, when doing verilog

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 38f94077ff97062fb44ba06920d26ed5a8572b47..1b8d82ebffc7ea348305a874798bd2f6a22f2d7a 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -198,6 +198,11 @@ class TestIssuer(Elaboratable):
         yield self.memerr_o
         yield from self.core.ports()
         yield from self.imem.ports()
+        yield self.core_start_i
+        yield self.core_stop_i
+        yield self.core_bigendian_i
+        yield self.busy_o
+        yield self.halted_o
 
     def ports(self):
         return list(self)