--- /dev/null
+/builds
+
+# sbt directories
+/target
+/project/target
--- /dev/null
+
+ Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
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+ any Contribution intentionally submitted for inclusion in the Work
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+ 7. Disclaimer of Warranty. Unless required by applicable law or
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+ 8. Limitation of Liability. In no event and under no legal theory,
+ whether in tort (including negligence), contract, or otherwise,
+ unless required by applicable law (such as deliberate and grossly
+ negligent acts) or agreed to in writing, shall any Contributor be
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+
+ END OF TERMS AND CONDITIONS
+
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "[]"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
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+
+ Copyright 2016 SiFive, Inc.
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
--- /dev/null
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/e300artydevkit
+FPGA_DIR := $(base_dir)/fpga/e300artydevkit
+MODEL := E300ArtyDevKitTop
+PROJECT := sifive.freedom.everywhere.e300artydevkit
+CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
+CONFIG := E300ArtyDevKitConfig
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+EXTRA_FPGA_VSRCS := \
+ $(rocketchip_dir)/vsrc/AsyncResetReg.v \
+ $(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
+ $(sifiveblocks_dir)/vsrc/SRLatch.v
+
+include common.mk
--- /dev/null
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/u500vc707devkit
+FPGA_DIR := $(base_dir)/fpga/u500vc707devkit
+MODEL := U500VC707DevKitTop
+PROJECT := sifive.freedom.unleashed.u500vc707devkit
+CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
+CONFIG := U500VC707DevKitConfig
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+EXTRA_FPGA_VSRCS := \
+ $(rocketchip_dir)/vsrc/AsyncResetReg.v \
+ $(rocketchip_dir)/vsrc/DebugTransportModuleJtag.v \
+ $(sifiveblocks_dir)/vsrc/SRLatch.v \
+ $(sifiveblocks_dir)/vsrc/vc707reset.v
+
+PATCHVERILOG = \
+sed -i -s "s/ *output\(.*\)__inout\(.*\)/inout \1__inout\2/g" $@ && \
+grep -q -F " .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq)," $@ && \
+sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dq(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dq),/ .io_xilinxvc707mig__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
+grep -q -F " .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n)," $@ && \
+sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dqs_n(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_n),/ .io_xilinxvc707mig__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
+grep -q -F " .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p)," $@ && \
+sed -i -s "s/ .io_xilinxvc707mig__inout_ddr3_dqs_p(U500VC707DevKitSystem_1_io_xilinxvc707mig__inout_ddr3_dqs_p),/ .io_xilinxvc707mig__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p),/g" $@ && \
+grep -q -F " .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq)," $@ && \
+sed -i -s "s/ .io_port__inout_ddr3_dq(xilinxvc707mig_io_port__inout_ddr3_dq),/ .io_port__inout_ddr3_dq(io_xilinxvc707mig__inout_ddr3_dq),/g" $@ && \
+grep -q -F " .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n)," $@ && \
+sed -i -s "s/ .io_port__inout_ddr3_dqs_n(xilinxvc707mig_io_port__inout_ddr3_dqs_n),/ .io_port__inout_ddr3_dqs_n(io_xilinxvc707mig__inout_ddr3_dqs_n),/g" $@ && \
+grep -q -F " .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)" $@ && \
+sed -i -s "s/ .io_port__inout_ddr3_dqs_p(xilinxvc707mig_io_port__inout_ddr3_dqs_p)/ .io_port__inout_ddr3_dqs_p(io_xilinxvc707mig__inout_ddr3_dqs_p)/g" $@ && \
+grep -q -F " .ddr3_dq(blackbox_ddr3_dq)," $@ && \
+sed -i -s "s/ .ddr3_dq(blackbox_ddr3_dq),/ .ddr3_dq(io_port__inout_ddr3_dq),/g" $@ && \
+grep -q -F " .ddr3_dqs_n(blackbox_ddr3_dqs_n)," $@ && \
+sed -i -s "s/ .ddr3_dqs_n(blackbox_ddr3_dqs_n),/ .ddr3_dqs_n(io_port__inout_ddr3_dqs_n),/g" $@ && \
+grep -q -F " .ddr3_dqs_p(blackbox_ddr3_dqs_p)," $@ && \
+sed -i -s "s/ .ddr3_dqs_p(blackbox_ddr3_dqs_p),/ .ddr3_dqs_p(io_port__inout_ddr3_dqs_p),/g" $@
+
+include common.mk
--- /dev/null
+Freedom
+=======
+
+This repository contains the RTL created by SiFive for its Freedom E300 and U500
+platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
+Platform and is designed to be mapped onto an [Arty FPGA Evaluation
+Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
+U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
+be mapped onto a [VC707 FPGA Evaluation
+Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
+
+Please read the section corresponding to the kit you are interested in for
+instructions on how to use this repo.
+
+
+Freedom E310 Arty FPGA Dev Kit
+------------------------------
+
+The Freedom E310 Arty FPGA Dev Kit implements a Freedom E310 chip.
+
+### How to build
+
+The Makefile corresponding to the Freedom E310 Arty FPGA Dev Kit is
+`Makefile.e300artydevkit` and it consists of two main targets:
+
+- `verilog`: to compile the Chisel source files and generate the Verilog files.
+- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
+onto an Arty FPGA board.
+
+To execute these targets, you can run the following commands:
+
+```sh
+$ make -f Makefile.e300artydevkit verilog
+$ make -f Makefile.e300artydevkit mcs
+```
+
+These will place the files under `builds/e300artydevkit`.
+
+Note that in order to run the `mcs` target, you need to have the `vivado`
+executable on your `PATH`.
+
+### Bootrom
+
+The default bootrom consists of a program that immediately jumps to address
+0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
+board.
+
+
+Freedom U500 VC707 FPGA Dev Kit
+-------------------------------
+
+The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
+
+### How to build
+
+The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
+`Makefile.u500vc707devkit` and it consists of two main targets:
+
+- `verilog`: to compile the Chisel source files and generate the Verilog files.
+- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
+onto an VC707 FPGA board.
+
+To execute these targets, you can run the following commands:
+
+```sh
+$ make -f Makefile.u500vc707devkit verilog
+$ make -f Makefile.u500vc707devkit mcs
+```
+
+These will place the files under `builds/u500vc707devkit`.
+
+Note that in order to run the `mcs` target, you need to have the `vivado`
+executable on your `PATH`.
+
+### Bootrom
+
+The default bootrom consists of a bootloader that loads a program off the SD
+card slot on the VC707 board.
--- /dev/null
+// See LICENSE for license details.
+// Execute in place
+// Jump directly to XIP_TARGET_ADDR
+
+ .text
+ .option norvc
+ .globl _start
+_start:
+ j 1f
+ nop
+ nop
+#ifdef CONFIG_STRING
+ .word cfg_string
+#else
+ .word 0 // Filled in by GenerateBootROM in Chisel
+#endif
+
+1:
+ li t0, XIP_TARGET_ADDR
+ jr t0
+
+ .section .rodata
+#ifdef CONFIG_STRING
+cfg_string:
+ .incbin CONFIG_STRING
+#endif
--- /dev/null
+// See LICENSE for license details.
+organization := "com.sifive"
+name := "freedom"
+version := "0.1.0"
+
+lazy val commonSettings = Seq(
+ scalaVersion := "2.11.7", // This needs to match rocket-chip's scalaVersion
+ scalacOptions ++= Seq(
+ "-deprecation",
+ "-feature",
+ "-unchecked",
+ "-Xfatal-warnings",
+ "-language:reflectiveCalls"
+ )
+)
+
+// A RootProject (not well-documented) tells sbt to treat the target directory
+// as its own root project, reading its build settings. If we instead used the
+// normal `project in file()` declaration, sbt would ignore all of rocket-chip's
+// build settings, and therefore not understand that it has its own dependencies
+// on chisel, etc.
+lazy val rocketChip = RootProject(file("rocket-chip"))
+
+lazy val sifiveBlocks = (project in file("sifive-blocks")).
+ dependsOn(rocketChip).
+ settings(commonSettings: _*)
+
+lazy val freedomPlatforms = (project in file(".")).
+ dependsOn(rocketChip, sifiveBlocks).
+ settings(commonSettings: _*)
--- /dev/null
+# See LICENSE for license details.
+
+# Required variables:
+# - MODEL
+# - PROJECT
+# - CONFIG_PROJECT
+# - CONFIG
+# - BUILD_DIR
+# - FPGA_DIR
+
+# Optional variables:
+# - EXTRA_FPGA_VSRCS
+
+EXTRA_FPGA_VSRCS ?=
+PATCHVERILOG ?= ""
+
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+rocketchip_dir := $(base_dir)/rocket-chip
+SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
+
+# Build firrtl.jar and put it where chisel3 can find it.
+FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
+FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
+
+$(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
+ $(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
+ touch $(FIRRTL_JAR)
+ mkdir -p $(rocketchip_dir)/chisel3/lib
+ cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
+
+# Build .fir
+firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
+firrtl_prm := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).prm
+$(firrtl) $(firrtl_prm): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
+ mkdir -p $(dir $@)
+ $(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
+
+.PHONY: firrtl
+firrtl: $(firrtl)
+
+# Build .v
+verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+$(verilog): $(firrtl) $(FIRRTL_JAR)
+ $(FIRRTL) -i $(firrtl) -o $@ -X verilog
+ifneq ($(PATCHVERILOG),"")
+ $(PATCHVERILOG)
+endif
+
+
+verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
+$(verilog_consts_vh): $(firrtl_prm)
+ echo "\`ifndef CONST_VH" > $@
+ echo "\`define CONST_VH" >> $@
+ sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
+ echo "\`endif // CONST_VH" >> $@
+
+.PHONY: verilog
+verilog: $(verilog) $(verilog_consts_vh)
+
+# Build .mcs
+mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
+$(mcs): $(verilog) $(verilog_consts_vh)
+ VSRC_TOP=$(verilog) VSRC_CONSTS=$(verilog_consts_vh) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+ cp $(FPGA_DIR)/obj/system.mcs $@
+
+.PHONY: mcs
+mcs: $(mcs)
+
+# Clean
+.PHONY: clean
+clean:
+ $(MAKE) -C $(FPGA_DIR) clean
+ rm -rf $(BUILD_DIR)
--- /dev/null
+.Xil
+.ip_user_files
+*.log
+*.html
+*.xml
+fsm_encoding.os
+obj
+src/generated
--- /dev/null
+VIVADO ?= vivado
+VIVADOFLAGS := \
+ -nojournal -mode batch \
+ -source script/board.tcl \
+ -source script/prologue.tcl
+
+bit := obj/system.bit
+$(bit): script/impl.tcl script/init.tcl
+ VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
+
+.PHONY: bit
+bit: $(bit)
+
+mcs := obj/system.mcs
+$(mcs): $(bit)
+ $(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^
+
+.PHONY: mcs
+mcs: $(mcs)
+
+.PHONY: clean
+clean::
+ rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log
--- /dev/null
+set_property -dict [list \
+ CONFIG_VOLTAGE {3.3} \
+ CFGBVS {VCCO} \
+ BITSTREAM.CONFIG.SPI_BUSWIDTH {4} \
+ ] [current_design]
--- /dev/null
+## This file is a general .xdc for the ARTY Rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+
+set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+
+##Switches
+
+set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw_0 }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
+set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw_1 }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
+set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw_2 }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
+set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw_3 }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
+
+##RGB LEDs
+
+set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
+set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
+set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
+set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
+set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
+set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
+set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
+set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
+set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
+#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
+#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
+#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
+
+##LEDs
+
+set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led_0 }]; #IO_L24N_T3_35 Sch=led[4]
+set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led_1 }]; #IO_25_35 Sch=led[5]
+set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led_2 }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led_3 }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
+
+##Buttons
+
+set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn_0 }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
+set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn_1 }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
+set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn_2 }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
+set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn_3 }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
+
+##Pmod Header JA
+
+set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja_0 }]; #IO_0_15 Sch=ja[1]
+set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja_1 }]; #IO_L4P_T0_15 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja_2 }]; #IO_L4N_T0_15 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja_3 }]; #IO_L6P_T0_15 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja_4 }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja_5 }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja_6 }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_7 }]; #IO_25_15 Sch=ja[10]
+
+##Pmod Header JB
+
+#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb_0 }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
+#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb_1 }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
+#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb_2 }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
+#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb_3 }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
+#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb_4 }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb_5 }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
+#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb_6 }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
+#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb_7 }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
+
+##Pmod Header JC
+
+#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
+#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
+#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
+#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
+#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
+#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
+
+##Pmod Header JD
+
+set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd_0 }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
+set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd_1 }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
+set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd_2 }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
+#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd_3 }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
+set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd_4 }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
+set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd_5 }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
+set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd_6 }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
+#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd_7 }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
+
+##USB-UART Interface (FTDI FT2232H)
+
+set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
+set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+
+
+##ChipKit Single Ended Analog Inputs
+##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
+## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
+
+#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]
+#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0]
+#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1]
+#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1]
+#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2]
+#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2]
+#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3]
+#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3]
+#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4]
+#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4]
+#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5]
+#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5]
+
+##ChipKit Digital I/O Low
+
+set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
+set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
+set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
+set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
+set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
+set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
+set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
+set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
+set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
+set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
+set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
+
+##ChipKit Digital I/O On Outer Analog Header
+##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19)
+
+set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0]
+set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1]
+set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2]
+set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3]
+set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
+set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
+
+##ChipKit Digital I/O On Inner Analog Header
+##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
+
+#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
+#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
+#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
+#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
+#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
+#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
+
+##ChipKit Digital I/O High
+
+#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
+#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
+#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
+#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29]
+#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30]
+#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
+#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
+#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
+#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
+#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
+#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
+#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
+#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
+#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
+#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
+#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
+
+## ChipKit SPI
+
+set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
+set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
+set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
+set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
+
+## ChipKit I2C
+
+#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
+#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
+#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
+
+##Misc. ChipKit signals
+
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
+set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
+
+##SMSC Ethernet PHY
+
+#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
+#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
+#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
+#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
+#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
+#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
+#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
+#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
+#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
+#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
+#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
+#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
+#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
+#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
+#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
+#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
+#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
+#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
+
+##Quad SPI Flash
+
+set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 IOB TRUE } [get_ports { qspi_sck }];
+create_clock -add -name qspi_sck_pin -period 20.00 -waveform {0 10} [get_ports { qspi_sck }];
+set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 IOB TRUE } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 IOB TRUE PULLUP TRUE } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+##Power Measurements
+
+#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
+#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
+#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
+#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
+#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
+#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
+#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
+#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
--- /dev/null
+set name {arty_e300devkit}
+set part_fpga {xc7a35ticsg324-1L}
+set part_board {digilentinc.com:arty:part0:1.1}
+set bootrom_inst {rom}
--- /dev/null
+lassign $argv mcsfile bitfile datafile
+
+set iface spix4
+set size 16
+set bitaddr 0x0
+
+write_cfgmem -format mcs -interface $iface -size $size \
+ -loadbit "up ${bitaddr} ${bitfile}" \
+ -loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
+ -file $mcsfile -force
--- /dev/null
+set_param {messaging.defaultLimit} 1000000
+
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+synth_design -top $top -flatten_hierarchy rebuilt
+write_checkpoint -force [file join $wrkdir post_synth]
+
+opt_design
+write_checkpoint -force [file join $wrkdir post_opt]
+
+place_design
+write_checkpoint -force [file join $wrkdir post_place]
+
+phys_opt_design
+power_opt_design
+route_design
+write_checkpoint -force [file join $wrkdir post_route]
+
+write_bitstream -force [file join $wrkdir "${top}.bit"]
+write_sdf -force [file join $wrkdir "${top}.sdf"]
+write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
+write_debug_probes -force [file join $wrkdir "${top}.ltx"]
+
+# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
+# Work around the write_mem_info command not supporting "processor-less"
+# (non-Microblaze) designs.
+set bram_inst [get_cells -hierarchical "bram"]
+if {$bram_inst ne ""} {
+ source [file join $scriptdir "bram.tcl"]
+ write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
+}
+
+if {[info exists bootrom_inst]} {
+ puts "Generating bootrom.mmi ..."
+ set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
+ if {$rom_inst ne ""} {
+ source [file join $scriptdir "bram.tcl"]
+ write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
+ }
+}
+
+set rptdir [file join $wrkdir report]
+file mkdir $rptdir
+set rptutil [file join $rptdir utilization.txt]
+report_datasheet -file [file join $rptdir datasheet.txt]
+report_utilization -hierarchical -file $rptutil
+report_clock_utilization -file $rptutil -append
+report_ram_utilization -file $rptutil -append -detail
+report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
+report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
+report_drc -file [file join $rptdir drc.txt]
+report_io -file [file join $rptdir io.txt]
+report_clocks -file [file join $rptdir clocks.txt]
--- /dev/null
+proc recglob { basedir pattern } {
+ set dirlist [glob -nocomplain -directory $basedir -type d *]
+ set findlist [glob -nocomplain -directory $basedir $pattern]
+ foreach dir $dirlist {
+ set reclist [recglob $dir $pattern]
+ set findlist [concat $findlist $reclist]
+ }
+ return $findlist
+}
+
+proc findincludedir { basedir pattern } {
+ #find all subdirectories containing ".vh" files
+ set vhfiles [recglob $basedir $pattern]
+ set vhdirs {}
+ foreach match $vhfiles {
+ lappend vhdirs [file dir $match]
+ }
+ set uniquevhdirs [lsort -unique $vhdirs]
+ return $uniquevhdirs
+}
+
+file mkdir $ipdir
+update_ip_catalog -rebuild
+
+source [file join $scriptdir ip.tcl]
+
+# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+set obj [get_ips]
+generate_target all $obj
+export_ip_user_files -of_objects $obj -no_script -force
+
+set obj [current_fileset]
+
+# Xilinx bug workaround
+# scrape IP tree for directories containing .vh files
+# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
+set property_include_dirs [get_property include_dirs $obj]
+set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
--- /dev/null
+create_ip -vendor xilinx.com -library ip -name clk_wiz -module_name mmcm -dir $ipdir -force
+set_property -dict [list \
+ CONFIG.PRIMITIVE {MMCM} \
+ CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ CONFIG.CLKOUT1_USED {true} \
+ CONFIG.CLKOUT2_USED {true} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {8.388} \
+ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {65.000} \
+ ] [get_ips mmcm]
+
+create_ip -vendor xilinx.com -library ip -name proc_sys_reset -module_name reset_sys -dir $ipdir -force
+set_property -dict [list \
+ CONFIG.C_EXT_RESET_HIGH {false} \
+ CONFIG.C_AUX_RESET_HIGH {false} \
+ CONFIG.C_NUM_BUS_RST {1} \
+ CONFIG.C_NUM_PERP_RST {1} \
+ CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
+ CONFIG.C_NUM_PERP_ARESETN {1} \
+ ] [get_ips reset_sys]
--- /dev/null
+set scriptdir [file dirname [info script]]
+set commondir [file dirname $scriptdir]
+set srcdir [file join $commondir src]
+set constrsdir [file join $commondir constrs]
+
+set wrkdir [file join [pwd] obj]
+set ipdir [file join $wrkdir ip]
+
+set top {system}
+
+create_project -part $part_fpga -in_memory
+set_property -dict [list \
+ BOARD_PART $part_board \
+ TARGET_LANGUAGE {Verilog} \
+ SIMULATOR_LANGUAGE {Mixed} \
+ TARGET_SIMULATOR {XSim} \
+ DEFAULT_LIB {xil_defaultlib} \
+ IP_REPO_PATHS $ipdir \
+ ] [current_project]
+
+proc recglob { basedir pattern } {
+ set dirlist [glob -nocomplain -directory $basedir -type d *]
+ set findlist [glob -nocomplain -directory $basedir $pattern]
+ foreach dir $dirlist {
+ set reclist [recglob $dir $pattern]
+ set findlist [concat $findlist $reclist]
+ }
+ return $findlist
+}
+
+
+if {[get_filesets -quiet sources_1] eq ""} {
+ create_fileset -srcset sources_1
+}
+set obj [current_fileset]
+
+set srcmainverilogfiles [recglob $srcdir "*.v"]
+add_files -norecurse -fileset $obj $srcmainverilogfiles
+
+if {[info exists ::env(EXTRA_VSRCS)]} {
+ set extra_vsrcs [split $::env(EXTRA_VSRCS)]
+ foreach extra_vsrc $extra_vsrcs {
+ add_files -norecurse -fileset $obj $extra_vsrc
+ }
+}
+## TODO: These paths and files should come from the caller, not within this script.
+#if {[file exists [file join $srcdir include verilog]]} {
+# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
+# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
+#}
+
+set vsrc_top $::env(VSRC_TOP)
+set vsrc_consts $::env(VSRC_CONSTS)
+
+set_property verilog_define [list \
+ "VSRC_CONSTS=${vsrc_consts}" \
+ "VSRC_TOP=${vsrc_top}" \
+ ] $obj
+
+add_files -norecurse -fileset $obj $vsrc_top
+add_files -norecurse -fileset $obj $vsrc_consts
+
+if {[get_filesets -quiet sim_1] eq ""} {
+ create_fileset -simset sim_1
+}
+set obj [current_fileset -simset]
+add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
+set_property TOP {tb} $obj
+
+if {[get_filesets -quiet constrs_1] eq ""} {
+ create_fileset -constrset constrs_1
+}
+set obj [current_fileset -constrset]
+add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
--- /dev/null
+`timescale 1ns/1ps
+
+`define STRINGIFY(x) `"x`"
+`include `STRINGIFY(`VSRC_CONSTS)
+
+module system
+(
+ input wire CLK100MHZ,
+ input wire ck_rst,
+
+ // Green LEDs
+ inout wire led_0,
+ inout wire led_1,
+ inout wire led_2,
+ inout wire led_3,
+
+ // RGB LEDs, 3 pins each
+ output wire led0_r,
+ output wire led0_g,
+ output wire led0_b,
+ output wire led1_r,
+ output wire led1_g,
+ output wire led1_b,
+ output wire led2_r,
+ output wire led2_g,
+ output wire led2_b,
+
+ // Sliding switches, 3 used as GPIOs
+ // sw_3 selects input to UART0
+ inout wire sw_0,
+ inout wire sw_1,
+ inout wire sw_2,
+ input wire sw_3,
+
+ // Buttons. First 3 used as GPIOs, the last is used as wakeup
+ inout wire btn_0,
+ inout wire btn_1,
+ inout wire btn_2,
+ inout wire btn_3,
+
+ // Dedicated QSPI interface
+ output wire qspi_cs,
+ output wire qspi_sck,
+ inout wire [3:0] qspi_dq,
+
+ // UART0 (GPIO 16,17)
+ output wire uart_rxd_out,
+ input wire uart_txd_in,
+
+ // UART1 (GPIO 24,25) (not present on 48-pin)
+ inout wire ja_0,
+ inout wire ja_1,
+
+ // Arduino (aka chipkit) shield digital IO pins, 14 is not connected to the
+ // chip, used for debug.
+ inout wire [19:0] ck_io,
+
+ // Dedicated SPI pins on 6 pin header standard on later arduino models
+ // connected to SPI2 (on FPGA)
+ inout wire ck_miso,
+ inout wire ck_mosi,
+ inout wire ck_ss,
+ inout wire ck_sck,
+
+ // JD (used for JTAG connection)
+ inout wire jd_0, // TDO
+ inout wire jd_1, // TRST_n
+ inout wire jd_2, // TCK
+ inout wire jd_4, // TDI
+ inout wire jd_5, // TMS
+ input wire jd_6 // SRST_n
+);
+
+ wire clk_out1;
+ wire hfclk;
+ wire mmcm_locked;
+
+ wire reset_core;
+ wire reset_bus;
+ wire reset_periph;
+ wire reset_intcon_n;
+ wire reset_periph_n;
+
+ // All wires connected to the chip top
+ wire dut_clock;
+ wire dut_reset;
+ wire dut_io_pads_jtag_TCK_i_ival;
+ wire dut_io_pads_jtag_TCK_o_oval;
+ wire dut_io_pads_jtag_TCK_o_oe;
+ wire dut_io_pads_jtag_TCK_o_ie;
+ wire dut_io_pads_jtag_TCK_o_pue;
+ wire dut_io_pads_jtag_TCK_o_ds;
+ wire dut_io_pads_jtag_TMS_i_ival;
+ wire dut_io_pads_jtag_TMS_o_oval;
+ wire dut_io_pads_jtag_TMS_o_oe;
+ wire dut_io_pads_jtag_TMS_o_ie;
+ wire dut_io_pads_jtag_TMS_o_pue;
+ wire dut_io_pads_jtag_TMS_o_ds;
+ wire dut_io_pads_jtag_TDI_i_ival;
+ wire dut_io_pads_jtag_TDI_o_oval;
+ wire dut_io_pads_jtag_TDI_o_oe;
+ wire dut_io_pads_jtag_TDI_o_ie;
+ wire dut_io_pads_jtag_TDI_o_pue;
+ wire dut_io_pads_jtag_TDI_o_ds;
+ wire dut_io_pads_jtag_TDO_i_ival;
+ wire dut_io_pads_jtag_TDO_o_oval;
+ wire dut_io_pads_jtag_TDO_o_oe;
+ wire dut_io_pads_jtag_TDO_o_ie;
+ wire dut_io_pads_jtag_TDO_o_pue;
+ wire dut_io_pads_jtag_TDO_o_ds;
+ wire dut_io_pads_jtag_TRST_n_i_ival;
+ wire dut_io_pads_jtag_TRST_n_o_oval;
+ wire dut_io_pads_jtag_TRST_n_o_oe;
+ wire dut_io_pads_jtag_TRST_n_o_ie;
+ wire dut_io_pads_jtag_TRST_n_o_pue;
+ wire dut_io_pads_jtag_TRST_n_o_ds;
+ wire dut_io_pads_gpio_0_i_ival;
+ wire dut_io_pads_gpio_0_o_oval;
+ wire dut_io_pads_gpio_0_o_oe;
+ wire dut_io_pads_gpio_0_o_ie;
+ wire dut_io_pads_gpio_0_o_pue;
+ wire dut_io_pads_gpio_0_o_ds;
+ wire dut_io_pads_gpio_1_i_ival;
+ wire dut_io_pads_gpio_1_o_oval;
+ wire dut_io_pads_gpio_1_o_oe;
+ wire dut_io_pads_gpio_1_o_ie;
+ wire dut_io_pads_gpio_1_o_pue;
+ wire dut_io_pads_gpio_1_o_ds;
+ wire dut_io_pads_gpio_2_i_ival;
+ wire dut_io_pads_gpio_2_o_oval;
+ wire dut_io_pads_gpio_2_o_oe;
+ wire dut_io_pads_gpio_2_o_ie;
+ wire dut_io_pads_gpio_2_o_pue;
+ wire dut_io_pads_gpio_2_o_ds;
+ wire dut_io_pads_gpio_3_i_ival;
+ wire dut_io_pads_gpio_3_o_oval;
+ wire dut_io_pads_gpio_3_o_oe;
+ wire dut_io_pads_gpio_3_o_ie;
+ wire dut_io_pads_gpio_3_o_pue;
+ wire dut_io_pads_gpio_3_o_ds;
+ wire dut_io_pads_gpio_4_i_ival;
+ wire dut_io_pads_gpio_4_o_oval;
+ wire dut_io_pads_gpio_4_o_oe;
+ wire dut_io_pads_gpio_4_o_ie;
+ wire dut_io_pads_gpio_4_o_pue;
+ wire dut_io_pads_gpio_4_o_ds;
+ wire dut_io_pads_gpio_5_i_ival;
+ wire dut_io_pads_gpio_5_o_oval;
+ wire dut_io_pads_gpio_5_o_oe;
+ wire dut_io_pads_gpio_5_o_ie;
+ wire dut_io_pads_gpio_5_o_pue;
+ wire dut_io_pads_gpio_5_o_ds;
+ wire dut_io_pads_gpio_6_i_ival;
+ wire dut_io_pads_gpio_6_o_oval;
+ wire dut_io_pads_gpio_6_o_oe;
+ wire dut_io_pads_gpio_6_o_ie;
+ wire dut_io_pads_gpio_6_o_pue;
+ wire dut_io_pads_gpio_6_o_ds;
+ wire dut_io_pads_gpio_7_i_ival;
+ wire dut_io_pads_gpio_7_o_oval;
+ wire dut_io_pads_gpio_7_o_oe;
+ wire dut_io_pads_gpio_7_o_ie;
+ wire dut_io_pads_gpio_7_o_pue;
+ wire dut_io_pads_gpio_7_o_ds;
+ wire dut_io_pads_gpio_8_i_ival;
+ wire dut_io_pads_gpio_8_o_oval;
+ wire dut_io_pads_gpio_8_o_oe;
+ wire dut_io_pads_gpio_8_o_ie;
+ wire dut_io_pads_gpio_8_o_pue;
+ wire dut_io_pads_gpio_8_o_ds;
+ wire dut_io_pads_gpio_9_i_ival;
+ wire dut_io_pads_gpio_9_o_oval;
+ wire dut_io_pads_gpio_9_o_oe;
+ wire dut_io_pads_gpio_9_o_ie;
+ wire dut_io_pads_gpio_9_o_pue;
+ wire dut_io_pads_gpio_9_o_ds;
+ wire dut_io_pads_gpio_10_i_ival;
+ wire dut_io_pads_gpio_10_o_oval;
+ wire dut_io_pads_gpio_10_o_oe;
+ wire dut_io_pads_gpio_10_o_ie;
+ wire dut_io_pads_gpio_10_o_pue;
+ wire dut_io_pads_gpio_10_o_ds;
+ wire dut_io_pads_gpio_11_i_ival;
+ wire dut_io_pads_gpio_11_o_oval;
+ wire dut_io_pads_gpio_11_o_oe;
+ wire dut_io_pads_gpio_11_o_ie;
+ wire dut_io_pads_gpio_11_o_pue;
+ wire dut_io_pads_gpio_11_o_ds;
+ wire dut_io_pads_gpio_12_i_ival;
+ wire dut_io_pads_gpio_12_o_oval;
+ wire dut_io_pads_gpio_12_o_oe;
+ wire dut_io_pads_gpio_12_o_ie;
+ wire dut_io_pads_gpio_12_o_pue;
+ wire dut_io_pads_gpio_12_o_ds;
+ wire dut_io_pads_gpio_13_i_ival;
+ wire dut_io_pads_gpio_13_o_oval;
+ wire dut_io_pads_gpio_13_o_oe;
+ wire dut_io_pads_gpio_13_o_ie;
+ wire dut_io_pads_gpio_13_o_pue;
+ wire dut_io_pads_gpio_13_o_ds;
+ wire dut_io_pads_gpio_14_i_ival;
+ wire dut_io_pads_gpio_14_o_oval;
+ wire dut_io_pads_gpio_14_o_oe;
+ wire dut_io_pads_gpio_14_o_ie;
+ wire dut_io_pads_gpio_14_o_pue;
+ wire dut_io_pads_gpio_14_o_ds;
+ wire dut_io_pads_gpio_15_i_ival;
+ wire dut_io_pads_gpio_15_o_oval;
+ wire dut_io_pads_gpio_15_o_oe;
+ wire dut_io_pads_gpio_15_o_ie;
+ wire dut_io_pads_gpio_15_o_pue;
+ wire dut_io_pads_gpio_15_o_ds;
+ wire dut_io_pads_gpio_16_i_ival;
+ wire dut_io_pads_gpio_16_o_oval;
+ wire dut_io_pads_gpio_16_o_oe;
+ wire dut_io_pads_gpio_16_o_ie;
+ wire dut_io_pads_gpio_16_o_pue;
+ wire dut_io_pads_gpio_16_o_ds;
+ wire dut_io_pads_gpio_17_i_ival;
+ wire dut_io_pads_gpio_17_o_oval;
+ wire dut_io_pads_gpio_17_o_oe;
+ wire dut_io_pads_gpio_17_o_ie;
+ wire dut_io_pads_gpio_17_o_pue;
+ wire dut_io_pads_gpio_17_o_ds;
+ wire dut_io_pads_gpio_18_i_ival;
+ wire dut_io_pads_gpio_18_o_oval;
+ wire dut_io_pads_gpio_18_o_oe;
+ wire dut_io_pads_gpio_18_o_ie;
+ wire dut_io_pads_gpio_18_o_pue;
+ wire dut_io_pads_gpio_18_o_ds;
+ wire dut_io_pads_gpio_19_i_ival;
+ wire dut_io_pads_gpio_19_o_oval;
+ wire dut_io_pads_gpio_19_o_oe;
+ wire dut_io_pads_gpio_19_o_ie;
+ wire dut_io_pads_gpio_19_o_pue;
+ wire dut_io_pads_gpio_19_o_ds;
+ wire dut_io_pads_gpio_20_i_ival;
+ wire dut_io_pads_gpio_20_o_oval;
+ wire dut_io_pads_gpio_20_o_oe;
+ wire dut_io_pads_gpio_20_o_ie;
+ wire dut_io_pads_gpio_20_o_pue;
+ wire dut_io_pads_gpio_20_o_ds;
+ wire dut_io_pads_gpio_21_i_ival;
+ wire dut_io_pads_gpio_21_o_oval;
+ wire dut_io_pads_gpio_21_o_oe;
+ wire dut_io_pads_gpio_21_o_ie;
+ wire dut_io_pads_gpio_21_o_pue;
+ wire dut_io_pads_gpio_21_o_ds;
+ wire dut_io_pads_gpio_22_i_ival;
+ wire dut_io_pads_gpio_22_o_oval;
+ wire dut_io_pads_gpio_22_o_oe;
+ wire dut_io_pads_gpio_22_o_ie;
+ wire dut_io_pads_gpio_22_o_pue;
+ wire dut_io_pads_gpio_22_o_ds;
+ wire dut_io_pads_gpio_23_i_ival;
+ wire dut_io_pads_gpio_23_o_oval;
+ wire dut_io_pads_gpio_23_o_oe;
+ wire dut_io_pads_gpio_23_o_ie;
+ wire dut_io_pads_gpio_23_o_pue;
+ wire dut_io_pads_gpio_23_o_ds;
+ wire dut_io_pads_gpio_24_i_ival;
+ wire dut_io_pads_gpio_24_o_oval;
+ wire dut_io_pads_gpio_24_o_oe;
+ wire dut_io_pads_gpio_24_o_ie;
+ wire dut_io_pads_gpio_24_o_pue;
+ wire dut_io_pads_gpio_24_o_ds;
+ wire dut_io_pads_gpio_25_i_ival;
+ wire dut_io_pads_gpio_25_o_oval;
+ wire dut_io_pads_gpio_25_o_oe;
+ wire dut_io_pads_gpio_25_o_ie;
+ wire dut_io_pads_gpio_25_o_pue;
+ wire dut_io_pads_gpio_25_o_ds;
+ wire dut_io_pads_gpio_26_i_ival;
+ wire dut_io_pads_gpio_26_o_oval;
+ wire dut_io_pads_gpio_26_o_oe;
+ wire dut_io_pads_gpio_26_o_ie;
+ wire dut_io_pads_gpio_26_o_pue;
+ wire dut_io_pads_gpio_26_o_ds;
+ wire dut_io_pads_gpio_27_i_ival;
+ wire dut_io_pads_gpio_27_o_oval;
+ wire dut_io_pads_gpio_27_o_oe;
+ wire dut_io_pads_gpio_27_o_ie;
+ wire dut_io_pads_gpio_27_o_pue;
+ wire dut_io_pads_gpio_27_o_ds;
+ wire dut_io_pads_gpio_28_i_ival;
+ wire dut_io_pads_gpio_28_o_oval;
+ wire dut_io_pads_gpio_28_o_oe;
+ wire dut_io_pads_gpio_28_o_ie;
+ wire dut_io_pads_gpio_28_o_pue;
+ wire dut_io_pads_gpio_28_o_ds;
+ wire dut_io_pads_gpio_29_i_ival;
+ wire dut_io_pads_gpio_29_o_oval;
+ wire dut_io_pads_gpio_29_o_oe;
+ wire dut_io_pads_gpio_29_o_ie;
+ wire dut_io_pads_gpio_29_o_pue;
+ wire dut_io_pads_gpio_29_o_ds;
+ wire dut_io_pads_gpio_30_i_ival;
+ wire dut_io_pads_gpio_30_o_oval;
+ wire dut_io_pads_gpio_30_o_oe;
+ wire dut_io_pads_gpio_30_o_ie;
+ wire dut_io_pads_gpio_30_o_pue;
+ wire dut_io_pads_gpio_30_o_ds;
+ wire dut_io_pads_gpio_31_i_ival;
+ wire dut_io_pads_gpio_31_o_oval;
+ wire dut_io_pads_gpio_31_o_oe;
+ wire dut_io_pads_gpio_31_o_ie;
+ wire dut_io_pads_gpio_31_o_pue;
+ wire dut_io_pads_gpio_31_o_ds;
+ wire dut_io_pads_qspi_sck_i_ival;
+ wire dut_io_pads_qspi_sck_o_oval;
+ wire dut_io_pads_qspi_sck_o_oe;
+ wire dut_io_pads_qspi_sck_o_ie;
+ wire dut_io_pads_qspi_sck_o_pue;
+ wire dut_io_pads_qspi_sck_o_ds;
+ wire dut_io_pads_qspi_dq_0_i_ival;
+ wire dut_io_pads_qspi_dq_0_o_oval;
+ wire dut_io_pads_qspi_dq_0_o_oe;
+ wire dut_io_pads_qspi_dq_0_o_ie;
+ wire dut_io_pads_qspi_dq_0_o_pue;
+ wire dut_io_pads_qspi_dq_0_o_ds;
+ wire dut_io_pads_qspi_dq_1_i_ival;
+ wire dut_io_pads_qspi_dq_1_o_oval;
+ wire dut_io_pads_qspi_dq_1_o_oe;
+ wire dut_io_pads_qspi_dq_1_o_ie;
+ wire dut_io_pads_qspi_dq_1_o_pue;
+ wire dut_io_pads_qspi_dq_1_o_ds;
+ wire dut_io_pads_qspi_dq_2_i_ival;
+ wire dut_io_pads_qspi_dq_2_o_oval;
+ wire dut_io_pads_qspi_dq_2_o_oe;
+ wire dut_io_pads_qspi_dq_2_o_ie;
+ wire dut_io_pads_qspi_dq_2_o_pue;
+ wire dut_io_pads_qspi_dq_2_o_ds;
+ wire dut_io_pads_qspi_dq_3_i_ival;
+ wire dut_io_pads_qspi_dq_3_o_oval;
+ wire dut_io_pads_qspi_dq_3_o_oe;
+ wire dut_io_pads_qspi_dq_3_o_ie;
+ wire dut_io_pads_qspi_dq_3_o_pue;
+ wire dut_io_pads_qspi_dq_3_o_ds;
+ wire dut_io_pads_qspi_cs_0_i_ival;
+ wire dut_io_pads_qspi_cs_0_o_oval;
+ wire dut_io_pads_qspi_cs_0_o_oe;
+ wire dut_io_pads_qspi_cs_0_o_ie;
+ wire dut_io_pads_qspi_cs_0_o_pue;
+ wire dut_io_pads_qspi_cs_0_o_ds;
+ wire dut_io_pads_aon_erst_n_i_ival;
+ wire dut_io_pads_aon_erst_n_o_oval;
+ wire dut_io_pads_aon_erst_n_o_oe;
+ wire dut_io_pads_aon_erst_n_o_ie;
+ wire dut_io_pads_aon_erst_n_o_pue;
+ wire dut_io_pads_aon_erst_n_o_ds;
+ wire dut_io_pads_aon_lfextclk_i_ival;
+ wire dut_io_pads_aon_lfextclk_o_oval;
+ wire dut_io_pads_aon_lfextclk_o_oe;
+ wire dut_io_pads_aon_lfextclk_o_ie;
+ wire dut_io_pads_aon_lfextclk_o_pue;
+ wire dut_io_pads_aon_lfextclk_o_ds;
+ wire dut_io_pads_aon_pmu_dwakeup_n_i_ival;
+ wire dut_io_pads_aon_pmu_dwakeup_n_o_oval;
+ wire dut_io_pads_aon_pmu_dwakeup_n_o_oe;
+ wire dut_io_pads_aon_pmu_dwakeup_n_o_ie;
+ wire dut_io_pads_aon_pmu_dwakeup_n_o_pue;
+ wire dut_io_pads_aon_pmu_dwakeup_n_o_ds;
+ wire dut_io_pads_aon_pmu_vddpaden_i_ival;
+ wire dut_io_pads_aon_pmu_vddpaden_o_oval;
+ wire dut_io_pads_aon_pmu_vddpaden_o_oe;
+ wire dut_io_pads_aon_pmu_vddpaden_o_ie;
+ wire dut_io_pads_aon_pmu_vddpaden_o_pue;
+ wire dut_io_pads_aon_pmu_vddpaden_o_ds;
+
+ //=================================================
+ // Clock & Reset
+
+ wire SRST_n; // From FTDI Chip
+
+ mmcm ip_mmcm
+ (
+ .clk_in1(CLK100MHZ),
+ .clk_out1(clk_out1), // 8.388 MHz = 32.768 kHz * 256
+ .clk_out2(hfclk), // 65 MHz
+ .resetn(ck_rst),
+ .locked(mmcm_locked)
+ );
+
+ wire slowclk;
+ clkdivider slowclkgen
+ (
+ .clk(clk_out1),
+ .reset(~mmcm_locked),
+ .clk_out(slowclk)
+ );
+
+ reset_sys ip_reset_sys
+ (
+ .slowest_sync_clk(clk_out1),
+ .ext_reset_in(ck_rst & SRST_n), // Active-low
+ .aux_reset_in(1'b1),
+ .mb_debug_sys_rst(1'b0),
+ .dcm_locked(mmcm_locked),
+ .mb_reset(reset_core),
+ .bus_struct_reset(reset_bus),
+ .peripheral_reset(reset_periph),
+ .interconnect_aresetn(reset_intcon_n),
+ .peripheral_aresetn(reset_periph_n)
+ );
+
+ //=================================================
+ // SPI Interface
+
+ wire [3:0] qspi_ui_dq_o, qspi_ui_dq_oe;
+ wire [3:0] qspi_ui_dq_i;
+
+ PULLUP qspi_pullup[3:0]
+ (
+ .O(qspi_dq)
+ );
+
+ IOBUF qspi_iobuf[3:0]
+ (
+ .IO(qspi_dq),
+ .O(qspi_ui_dq_i),
+ .I(qspi_ui_dq_o),
+ .T(~qspi_ui_dq_oe)
+ );
+
+ //=================================================
+ // IOBUF instantiation for GPIOs
+
+ wire gpio_0;
+ wire gpio_1;
+ wire gpio_2;
+ wire gpio_3;
+ wire gpio_4;
+ wire gpio_5;
+ wire gpio_6;
+ wire gpio_7;
+ wire gpio_8;
+ wire gpio_9;
+ wire gpio_10;
+ wire gpio_11;
+ wire gpio_12;
+ wire gpio_13;
+ wire gpio_14;
+ wire gpio_15;
+ wire gpio_16;
+ wire gpio_17;
+ wire gpio_18;
+ wire gpio_19;
+ wire gpio_20;
+ wire gpio_21;
+ wire gpio_22;
+ wire gpio_23;
+ wire gpio_24;
+ wire gpio_25;
+ wire gpio_26;
+ wire gpio_27;
+ wire gpio_28;
+ wire gpio_29;
+ wire gpio_30;
+ wire gpio_31;
+
+ wire iobuf_gpio_0_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_0
+ (
+ .O(iobuf_gpio_0_o),
+ .IO(gpio_0),
+ .I(dut_io_pads_gpio_0_o_oval),
+ .T(~dut_io_pads_gpio_0_o_oe)
+ );
+ assign dut_io_pads_gpio_0_i_ival = iobuf_gpio_0_o & dut_io_pads_gpio_0_o_ie;
+
+ wire iobuf_gpio_1_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_1
+ (
+ .O(iobuf_gpio_1_o),
+ .IO(gpio_1),
+ .I(dut_io_pads_gpio_1_o_oval),
+ .T(~dut_io_pads_gpio_1_o_oe)
+ );
+ assign dut_io_pads_gpio_1_i_ival = iobuf_gpio_1_o & dut_io_pads_gpio_1_o_ie;
+
+ wire iobuf_gpio_2_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_2
+ (
+ .O(iobuf_gpio_2_o),
+ .IO(gpio_2),
+ .I(dut_io_pads_gpio_2_o_oval),
+ .T(~dut_io_pads_gpio_2_o_oe)
+ );
+ assign dut_io_pads_gpio_2_i_ival = iobuf_gpio_2_o & dut_io_pads_gpio_2_o_ie;
+
+ wire iobuf_gpio_3_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_3
+ (
+ .O(iobuf_gpio_3_o),
+ .IO(gpio_3),
+ .I(dut_io_pads_gpio_3_o_oval),
+ .T(~dut_io_pads_gpio_3_o_oe)
+ );
+ assign dut_io_pads_gpio_3_i_ival = iobuf_gpio_3_o & dut_io_pads_gpio_3_o_ie;
+
+ wire iobuf_gpio_4_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_4
+ (
+ .O(iobuf_gpio_4_o),
+ .IO(gpio_4),
+ .I(dut_io_pads_gpio_4_o_oval),
+ .T(~dut_io_pads_gpio_4_o_oe)
+ );
+ assign dut_io_pads_gpio_4_i_ival = iobuf_gpio_4_o & dut_io_pads_gpio_4_o_ie;
+
+ wire iobuf_gpio_5_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_5
+ (
+ .O(iobuf_gpio_5_o),
+ .IO(gpio_5),
+ .I(dut_io_pads_gpio_5_o_oval),
+ .T(~dut_io_pads_gpio_5_o_oe)
+ );
+ assign dut_io_pads_gpio_5_i_ival = iobuf_gpio_5_o & dut_io_pads_gpio_5_o_ie;
+
+ assign dut_io_pads_gpio_6_i_ival = 1'b0;
+
+ assign dut_io_pads_gpio_7_i_ival = 1'b0;
+
+ assign dut_io_pads_gpio_8_i_ival = 1'b0;
+
+ wire iobuf_gpio_9_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_9
+ (
+ .O(iobuf_gpio_9_o),
+ .IO(gpio_9),
+ .I(dut_io_pads_gpio_9_o_oval),
+ .T(~dut_io_pads_gpio_9_o_oe)
+ );
+ assign dut_io_pads_gpio_9_i_ival = iobuf_gpio_9_o & dut_io_pads_gpio_9_o_ie;
+
+ wire iobuf_gpio_10_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_10
+ (
+ .O(iobuf_gpio_10_o),
+ .IO(gpio_10),
+ .I(dut_io_pads_gpio_10_o_oval),
+ .T(~dut_io_pads_gpio_10_o_oe)
+ );
+ assign dut_io_pads_gpio_10_i_ival = iobuf_gpio_10_o & dut_io_pads_gpio_10_o_ie;
+
+ wire iobuf_gpio_11_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_11
+ (
+ .O(iobuf_gpio_11_o),
+ .IO(gpio_11),
+ .I(dut_io_pads_gpio_11_o_oval),
+ .T(~dut_io_pads_gpio_11_o_oe)
+ );
+ assign dut_io_pads_gpio_11_i_ival = iobuf_gpio_11_o & dut_io_pads_gpio_11_o_ie;
+
+ wire iobuf_gpio_12_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_12
+ (
+ .O(iobuf_gpio_12_o),
+ .IO(gpio_12),
+ .I(dut_io_pads_gpio_12_o_oval),
+ .T(~dut_io_pads_gpio_12_o_oe)
+ );
+ assign dut_io_pads_gpio_12_i_ival = iobuf_gpio_12_o & dut_io_pads_gpio_12_o_ie;
+
+ wire iobuf_gpio_13_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_13
+ (
+ .O(iobuf_gpio_13_o),
+ .IO(gpio_13),
+ .I(dut_io_pads_gpio_13_o_oval),
+ .T(~dut_io_pads_gpio_13_o_oe)
+ );
+ assign dut_io_pads_gpio_13_i_ival = iobuf_gpio_13_o & dut_io_pads_gpio_13_o_ie;
+
+ wire iobuf_gpio_14_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_14
+ (
+ .O(iobuf_gpio_14_o),
+ .IO(gpio_14),
+ .I(dut_io_pads_gpio_14_o_oval),
+ .T(~dut_io_pads_gpio_14_o_oe)
+ );
+ assign dut_io_pads_gpio_14_i_ival = iobuf_gpio_14_o & dut_io_pads_gpio_14_o_ie;
+
+ wire iobuf_gpio_15_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_15
+ (
+ .O(iobuf_gpio_15_o),
+ .IO(gpio_15),
+ .I(dut_io_pads_gpio_15_o_oval),
+ .T(~dut_io_pads_gpio_15_o_oe)
+ );
+ assign dut_io_pads_gpio_15_i_ival = iobuf_gpio_15_o & dut_io_pads_gpio_15_o_ie;
+
+ wire iobuf_gpio_16_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_16
+ (
+ .O(iobuf_gpio_16_o),
+ .IO(gpio_16),
+ .I(dut_io_pads_gpio_16_o_oval),
+ .T(~dut_io_pads_gpio_16_o_oe)
+ );
+ // This GPIO input is shared between FTDI TX pin and Arduino shield pin using SW[3]
+ // see below for details
+ assign dut_io_pads_gpio_16_i_ival = sw_3 ? (iobuf_gpio_16_o & dut_io_pads_gpio_16_o_ie) : (uart_txd_in & dut_io_pads_gpio_16_o_ie);
+
+ wire iobuf_gpio_17_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_17
+ (
+ .O(iobuf_gpio_17_o),
+ .IO(gpio_17),
+ .I(dut_io_pads_gpio_17_o_oval),
+ .T(~dut_io_pads_gpio_17_o_oe)
+ );
+ assign dut_io_pads_gpio_17_i_ival = iobuf_gpio_17_o & dut_io_pads_gpio_17_o_ie;
+ assign uart_rxd_out = (dut_io_pads_gpio_17_o_oval & dut_io_pads_gpio_17_o_oe);
+
+ wire iobuf_gpio_18_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_18
+ (
+ .O(iobuf_gpio_18_o),
+ .IO(gpio_18),
+ .I(dut_io_pads_gpio_18_o_oval),
+ .T(~dut_io_pads_gpio_18_o_oe)
+ );
+ assign dut_io_pads_gpio_18_i_ival = iobuf_gpio_18_o & dut_io_pads_gpio_18_o_ie;
+
+ wire iobuf_gpio_19_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_19
+ (
+ .O(iobuf_gpio_19_o),
+ .IO(gpio_19),
+ .I(dut_io_pads_gpio_19_o_oval),
+ .T(~dut_io_pads_gpio_19_o_oe)
+ );
+ assign dut_io_pads_gpio_19_i_ival = iobuf_gpio_19_o & dut_io_pads_gpio_19_o_ie;
+
+ wire iobuf_gpio_20_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_20
+ (
+ .O(iobuf_gpio_20_o),
+ .IO(gpio_20),
+ .I(dut_io_pads_gpio_20_o_oval),
+ .T(~dut_io_pads_gpio_20_o_oe)
+ );
+ assign dut_io_pads_gpio_20_i_ival = iobuf_gpio_20_o & dut_io_pads_gpio_20_o_ie;
+
+ wire iobuf_gpio_21_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_21
+ (
+ .O(iobuf_gpio_21_o),
+ .IO(gpio_21),
+ .I(dut_io_pads_gpio_21_o_oval),
+ .T(~dut_io_pads_gpio_21_o_oe)
+ );
+ assign dut_io_pads_gpio_21_i_ival = iobuf_gpio_21_o & dut_io_pads_gpio_21_o_ie;
+
+ wire iobuf_gpio_22_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_22
+ (
+ .O(iobuf_gpio_22_o),
+ .IO(gpio_22),
+ .I(dut_io_pads_gpio_22_o_oval),
+ .T(~dut_io_pads_gpio_22_o_oe)
+ );
+ assign dut_io_pads_gpio_22_i_ival = iobuf_gpio_22_o & dut_io_pads_gpio_22_o_ie;
+
+ wire iobuf_gpio_23_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_23
+ (
+ .O(iobuf_gpio_23_o),
+ .IO(gpio_23),
+ .I(dut_io_pads_gpio_23_o_oval),
+ .T(~dut_io_pads_gpio_23_o_oe)
+ );
+ assign dut_io_pads_gpio_23_i_ival = iobuf_gpio_23_o & dut_io_pads_gpio_23_o_ie;
+
+ wire iobuf_gpio_24_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_24
+ (
+ .O(iobuf_gpio_24_o),
+ .IO(gpio_24),
+ .I(dut_io_pads_gpio_24_o_oval),
+ .T(~dut_io_pads_gpio_24_o_oe)
+ );
+ assign dut_io_pads_gpio_24_i_ival = iobuf_gpio_24_o & dut_io_pads_gpio_24_o_ie;
+
+ wire iobuf_gpio_25_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_25
+ (
+ .O(iobuf_gpio_25_o),
+ .IO(gpio_25),
+ .I(dut_io_pads_gpio_25_o_oval),
+ .T(~dut_io_pads_gpio_25_o_oe)
+ );
+ assign dut_io_pads_gpio_25_i_ival = iobuf_gpio_25_o & dut_io_pads_gpio_25_o_ie;
+
+ wire iobuf_gpio_26_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_26
+ (
+ .O(iobuf_gpio_26_o),
+ .IO(gpio_26),
+ .I(dut_io_pads_gpio_26_o_oval),
+ .T(~dut_io_pads_gpio_26_o_oe)
+ );
+ assign dut_io_pads_gpio_26_i_ival = iobuf_gpio_26_o & dut_io_pads_gpio_26_o_ie;
+
+ wire iobuf_gpio_27_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_27
+ (
+ .O(iobuf_gpio_27_o),
+ .IO(gpio_27),
+ .I(dut_io_pads_gpio_27_o_oval),
+ .T(~dut_io_pads_gpio_27_o_oe)
+ );
+ assign dut_io_pads_gpio_27_i_ival = iobuf_gpio_27_o & dut_io_pads_gpio_27_o_ie;
+
+ wire iobuf_gpio_28_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_28
+ (
+ .O(iobuf_gpio_28_o),
+ .IO(gpio_28),
+ .I(dut_io_pads_gpio_28_o_oval),
+ .T(~dut_io_pads_gpio_28_o_oe)
+ );
+ assign dut_io_pads_gpio_28_i_ival = iobuf_gpio_28_o & dut_io_pads_gpio_28_o_ie;
+
+ wire iobuf_gpio_29_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_29
+ (
+ .O(iobuf_gpio_29_o),
+ .IO(gpio_29),
+ .I(dut_io_pads_gpio_29_o_oval),
+ .T(~dut_io_pads_gpio_29_o_oe)
+ );
+ assign dut_io_pads_gpio_29_i_ival = iobuf_gpio_29_o & dut_io_pads_gpio_29_o_ie;
+
+ wire iobuf_gpio_30_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_30
+ (
+ .O(iobuf_gpio_30_o),
+ .IO(gpio_30),
+ .I(dut_io_pads_gpio_30_o_oval),
+ .T(~dut_io_pads_gpio_30_o_oe)
+ );
+ assign dut_io_pads_gpio_30_i_ival = iobuf_gpio_30_o & dut_io_pads_gpio_30_o_ie;
+
+ wire iobuf_gpio_31_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_gpio_31
+ (
+ .O(iobuf_gpio_31_o),
+ .IO(gpio_31),
+ .I(dut_io_pads_gpio_31_o_oval),
+ .T(~dut_io_pads_gpio_31_o_oe)
+ );
+ assign dut_io_pads_gpio_31_i_ival = iobuf_gpio_31_o & dut_io_pads_gpio_31_o_ie;
+
+ //=================================================
+ // JTAG IOBUFs
+
+ wire iobuf_jtag_TCK_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_jtag_TCK
+ (
+ .O(iobuf_jtag_TCK_o),
+ .IO(jd_2),
+ .I(dut_io_pads_jtag_TCK_o_oval),
+ .T(~dut_io_pads_jtag_TCK_o_oe)
+ );
+ assign dut_io_pads_jtag_TCK_i_ival = iobuf_jtag_TCK_o & dut_io_pads_jtag_TCK_o_ie;
+ PULLUP pullup_TCK (.O(jd_2));
+
+ wire iobuf_jtag_TMS_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_jtag_TMS
+ (
+ .O(iobuf_jtag_TMS_o),
+ .IO(jd_5),
+ .I(dut_io_pads_jtag_TMS_o_oval),
+ .T(~dut_io_pads_jtag_TMS_o_oe)
+ );
+ assign dut_io_pads_jtag_TMS_i_ival = iobuf_jtag_TMS_o & dut_io_pads_jtag_TMS_o_ie;
+ PULLUP pullup_TMS (.O(jd_5));
+
+ wire iobuf_jtag_TDI_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_jtag_TDI
+ (
+ .O(iobuf_jtag_TDI_o),
+ .IO(jd_4),
+ .I(dut_io_pads_jtag_TDI_o_oval),
+ .T(~dut_io_pads_jtag_TDI_o_oe)
+ );
+ assign dut_io_pads_jtag_TDI_i_ival = iobuf_jtag_TDI_o & dut_io_pads_jtag_TDI_o_ie;
+ PULLUP pullup_TDI (.O(jd_4));
+
+ wire iobuf_jtag_TDO_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_jtag_TDO
+ (
+ .O(iobuf_jtag_TDO_o),
+ .IO(jd_0),
+ .I(dut_io_pads_jtag_TDO_o_oval),
+ .T(~dut_io_pads_jtag_TDO_o_oe)
+ );
+ assign dut_io_pads_jtag_TDO_i_ival = iobuf_jtag_TDO_o & dut_io_pads_jtag_TDO_o_ie;
+
+ wire iobuf_jtag_TRST_n_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_jtag_TRST_n
+ (
+ .O(iobuf_jtag_TRST_n_o),
+ .IO(jd_1),
+ .I(dut_io_pads_jtag_TRST_n_o_oval),
+ .T(~dut_io_pads_jtag_TRST_n_o_oe)
+ );
+ assign dut_io_pads_jtag_TRST_n_i_ival = iobuf_jtag_TRST_n_o & dut_io_pads_jtag_TRST_n_o_ie;
+ PULLUP pullup_TRST_n(.O(jd_1));
+
+ // Mimic putting a pullup on this line (part of reset vote).
+ assign SRST_n = jd_6;
+ PULLUP pullup_SRST_n(.O(SRST_n));
+
+ //=================================================
+ // Assignment of IOBUF "IO" pins to package pins
+
+ // Pins IO0-IO13
+ // Shield header row 0: PD0-PD7
+
+ // FTDI UART TX/RX are not connected to ck_io[1,2]
+ // the way they are on Arduino boards. We copy outgoing
+ // data to both places, switch 3 (sw[3]) determines whether
+ // input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
+
+ assign ck_io[0] = gpio_16; // UART0 RX
+ assign ck_io[1] = gpio_17; // UART0 TX
+ assign ck_io[2] = gpio_18;
+ assign ck_io[3] = gpio_19; // PWM1(1)
+ assign ck_io[4] = gpio_20; // PWM1(0)
+ assign ck_io[5] = gpio_21; // PWM1(2)
+ assign ck_io[6] = gpio_22; // PWM1(3)
+ assign ck_io[7] = gpio_23;
+ // Header row 1: PB0-PB5
+ assign ck_io[8] = gpio_0; // PWM0(0)
+ assign ck_io[9] = gpio_1; // PWM0(1)
+ assign ck_io[10] = gpio_2; // SPI1 CS(0) / PWM0(2)
+ assign ck_io[11] = gpio_3; // SPI1 MOSI / PWM0(3)
+ assign ck_io[12] = gpio_4; // SPI1 MISO
+ assign ck_io[13] = gpio_5; // SPI1 SCK
+
+ // Header row 3: A0-A5 (we don't support using them as analog inputs)
+ // just treat them as regular digital GPIOs
+ assign ck_io[14] = uart_txd_in; //gpio_9; // A0 = <unconnected> CS(1)
+ assign ck_io[15] = gpio_9; // A1 = CS(2)
+ assign ck_io[16] = gpio_10; // A2 = CS(3) / PWM2(0)
+ assign ck_io[17] = gpio_11; // A3 = PWM2(1)
+ assign ck_io[18] = gpio_12; // A4 = PWM2(2) / SDA
+ assign ck_io[19] = gpio_13; // A5 = PWM2(3) / SCL
+
+ // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty
+ // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active
+ assign led0_r = dut_io_pads_gpio_1_o_oval & dut_io_pads_gpio_1_o_oe;
+ assign led0_g = dut_io_pads_gpio_2_o_oval & dut_io_pads_gpio_2_o_oe;
+ assign led0_b = dut_io_pads_gpio_3_o_oval & dut_io_pads_gpio_2_o_oe;
+ // Note that this is the one which is actually connected on the HiFive/Crazy88
+ // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active
+ assign led1_r = dut_io_pads_gpio_19_o_oval & dut_io_pads_gpio_19_o_oe;
+ assign led1_g = dut_io_pads_gpio_21_o_oval & dut_io_pads_gpio_21_o_oe;
+ assign led1_b = dut_io_pads_gpio_22_o_oval & dut_io_pads_gpio_22_o_oe;
+ // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active
+ assign led2_r = dut_io_pads_gpio_11_o_oval & dut_io_pads_gpio_11_o_oe;
+ assign led2_g = dut_io_pads_gpio_12_o_oval & dut_io_pads_gpio_12_o_oe;
+ assign led2_b = dut_io_pads_gpio_13_o_oval & dut_io_pads_gpio_13_o_oe;
+
+ // Only 19 out of 20 shield pins connected to GPIO pads
+ // Shield pin A5 (pin 14) left unconnected
+ // The buttons are connected to some extra GPIO pads not connected on the
+ // HiFive1 board
+
+ assign btn_0 = gpio_15;
+ assign btn_1 = gpio_30;
+ assign btn_2 = gpio_31;
+
+ // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1
+ assign ja_0 = gpio_25; // UART1 TX
+ assign ja_1 = gpio_24; // UART1 RX
+
+ // SPI2 pins mapped to 6 pin ICSP connector (standard on later arduinos)
+ // These are connected to some extra GPIO pads not connected on the HiFive1
+ // board
+ assign ck_ss = gpio_26;
+ assign ck_mosi = gpio_27;
+ assign ck_miso = gpio_28;
+ assign ck_sck = gpio_29;
+
+ // Use the LEDs for some more useful debugging things.
+ assign led_0 = ck_rst;
+ assign led_1 = SRST_n;
+ assign led_2 = dut_io_pads_aon_pmu_dwakeup_n_i_ival;
+ assign led_3 = gpio_14;
+
+ E300ArtyDevKitTop dut
+ (
+ .clock(hfclk),
+ .reset(1'b1),
+ .io_pads_jtag_TCK_i_ival(dut_io_pads_jtag_TCK_i_ival),
+ .io_pads_jtag_TCK_o_oval(dut_io_pads_jtag_TCK_o_oval),
+ .io_pads_jtag_TCK_o_oe(dut_io_pads_jtag_TCK_o_oe),
+ .io_pads_jtag_TCK_o_ie(dut_io_pads_jtag_TCK_o_ie),
+ .io_pads_jtag_TCK_o_pue(dut_io_pads_jtag_TCK_o_pue),
+ .io_pads_jtag_TCK_o_ds(dut_io_pads_jtag_TCK_o_ds),
+ .io_pads_jtag_TMS_i_ival(dut_io_pads_jtag_TMS_i_ival),
+ .io_pads_jtag_TMS_o_oval(dut_io_pads_jtag_TMS_o_oval),
+ .io_pads_jtag_TMS_o_oe(dut_io_pads_jtag_TMS_o_oe),
+ .io_pads_jtag_TMS_o_ie(dut_io_pads_jtag_TMS_o_ie),
+ .io_pads_jtag_TMS_o_pue(dut_io_pads_jtag_TMS_o_pue),
+ .io_pads_jtag_TMS_o_ds(dut_io_pads_jtag_TMS_o_ds),
+ .io_pads_jtag_TDI_i_ival(dut_io_pads_jtag_TDI_i_ival),
+ .io_pads_jtag_TDI_o_oval(dut_io_pads_jtag_TDI_o_oval),
+ .io_pads_jtag_TDI_o_oe(dut_io_pads_jtag_TDI_o_oe),
+ .io_pads_jtag_TDI_o_ie(dut_io_pads_jtag_TDI_o_ie),
+ .io_pads_jtag_TDI_o_pue(dut_io_pads_jtag_TDI_o_pue),
+ .io_pads_jtag_TDI_o_ds(dut_io_pads_jtag_TDI_o_ds),
+ .io_pads_jtag_TDO_i_ival(dut_io_pads_jtag_TDO_i_ival),
+ .io_pads_jtag_TDO_o_oval(dut_io_pads_jtag_TDO_o_oval),
+ .io_pads_jtag_TDO_o_oe(dut_io_pads_jtag_TDO_o_oe),
+ .io_pads_jtag_TDO_o_ie(dut_io_pads_jtag_TDO_o_ie),
+ .io_pads_jtag_TDO_o_pue(dut_io_pads_jtag_TDO_o_pue),
+ .io_pads_jtag_TDO_o_ds(dut_io_pads_jtag_TDO_o_ds),
+ .io_pads_jtag_TRST_n_i_ival(dut_io_pads_jtag_TRST_n_i_ival),
+ .io_pads_jtag_TRST_n_o_oval(dut_io_pads_jtag_TRST_n_o_oval),
+ .io_pads_jtag_TRST_n_o_oe(dut_io_pads_jtag_TRST_n_o_oe),
+ .io_pads_jtag_TRST_n_o_ie(dut_io_pads_jtag_TRST_n_o_ie),
+ .io_pads_jtag_TRST_n_o_pue(dut_io_pads_jtag_TRST_n_o_pue),
+ .io_pads_jtag_TRST_n_o_ds(dut_io_pads_jtag_TRST_n_o_ds),
+ .io_pads_gpio_0_i_ival(dut_io_pads_gpio_0_i_ival),
+ .io_pads_gpio_0_o_oval(dut_io_pads_gpio_0_o_oval),
+ .io_pads_gpio_0_o_oe(dut_io_pads_gpio_0_o_oe),
+ .io_pads_gpio_0_o_ie(dut_io_pads_gpio_0_o_ie),
+ .io_pads_gpio_0_o_pue(dut_io_pads_gpio_0_o_pue),
+ .io_pads_gpio_0_o_ds(dut_io_pads_gpio_0_o_ds),
+ .io_pads_gpio_1_i_ival(dut_io_pads_gpio_1_i_ival),
+ .io_pads_gpio_1_o_oval(dut_io_pads_gpio_1_o_oval),
+ .io_pads_gpio_1_o_oe(dut_io_pads_gpio_1_o_oe),
+ .io_pads_gpio_1_o_ie(dut_io_pads_gpio_1_o_ie),
+ .io_pads_gpio_1_o_pue(dut_io_pads_gpio_1_o_pue),
+ .io_pads_gpio_1_o_ds(dut_io_pads_gpio_1_o_ds),
+ .io_pads_gpio_2_i_ival(dut_io_pads_gpio_2_i_ival),
+ .io_pads_gpio_2_o_oval(dut_io_pads_gpio_2_o_oval),
+ .io_pads_gpio_2_o_oe(dut_io_pads_gpio_2_o_oe),
+ .io_pads_gpio_2_o_ie(dut_io_pads_gpio_2_o_ie),
+ .io_pads_gpio_2_o_pue(dut_io_pads_gpio_2_o_pue),
+ .io_pads_gpio_2_o_ds(dut_io_pads_gpio_2_o_ds),
+ .io_pads_gpio_3_i_ival(dut_io_pads_gpio_3_i_ival),
+ .io_pads_gpio_3_o_oval(dut_io_pads_gpio_3_o_oval),
+ .io_pads_gpio_3_o_oe(dut_io_pads_gpio_3_o_oe),
+ .io_pads_gpio_3_o_ie(dut_io_pads_gpio_3_o_ie),
+ .io_pads_gpio_3_o_pue(dut_io_pads_gpio_3_o_pue),
+ .io_pads_gpio_3_o_ds(dut_io_pads_gpio_3_o_ds),
+ .io_pads_gpio_4_i_ival(dut_io_pads_gpio_4_i_ival),
+ .io_pads_gpio_4_o_oval(dut_io_pads_gpio_4_o_oval),
+ .io_pads_gpio_4_o_oe(dut_io_pads_gpio_4_o_oe),
+ .io_pads_gpio_4_o_ie(dut_io_pads_gpio_4_o_ie),
+ .io_pads_gpio_4_o_pue(dut_io_pads_gpio_4_o_pue),
+ .io_pads_gpio_4_o_ds(dut_io_pads_gpio_4_o_ds),
+ .io_pads_gpio_5_i_ival(dut_io_pads_gpio_5_i_ival),
+ .io_pads_gpio_5_o_oval(dut_io_pads_gpio_5_o_oval),
+ .io_pads_gpio_5_o_oe(dut_io_pads_gpio_5_o_oe),
+ .io_pads_gpio_5_o_ie(dut_io_pads_gpio_5_o_ie),
+ .io_pads_gpio_5_o_pue(dut_io_pads_gpio_5_o_pue),
+ .io_pads_gpio_5_o_ds(dut_io_pads_gpio_5_o_ds),
+ .io_pads_gpio_6_i_ival(dut_io_pads_gpio_6_i_ival),
+ .io_pads_gpio_6_o_oval(dut_io_pads_gpio_6_o_oval),
+ .io_pads_gpio_6_o_oe(dut_io_pads_gpio_6_o_oe),
+ .io_pads_gpio_6_o_ie(dut_io_pads_gpio_6_o_ie),
+ .io_pads_gpio_6_o_pue(dut_io_pads_gpio_6_o_pue),
+ .io_pads_gpio_6_o_ds(dut_io_pads_gpio_6_o_ds),
+ .io_pads_gpio_7_i_ival(dut_io_pads_gpio_7_i_ival),
+ .io_pads_gpio_7_o_oval(dut_io_pads_gpio_7_o_oval),
+ .io_pads_gpio_7_o_oe(dut_io_pads_gpio_7_o_oe),
+ .io_pads_gpio_7_o_ie(dut_io_pads_gpio_7_o_ie),
+ .io_pads_gpio_7_o_pue(dut_io_pads_gpio_7_o_pue),
+ .io_pads_gpio_7_o_ds(dut_io_pads_gpio_7_o_ds),
+ .io_pads_gpio_8_i_ival(dut_io_pads_gpio_8_i_ival),
+ .io_pads_gpio_8_o_oval(dut_io_pads_gpio_8_o_oval),
+ .io_pads_gpio_8_o_oe(dut_io_pads_gpio_8_o_oe),
+ .io_pads_gpio_8_o_ie(dut_io_pads_gpio_8_o_ie),
+ .io_pads_gpio_8_o_pue(dut_io_pads_gpio_8_o_pue),
+ .io_pads_gpio_8_o_ds(dut_io_pads_gpio_8_o_ds),
+ .io_pads_gpio_9_i_ival(dut_io_pads_gpio_9_i_ival),
+ .io_pads_gpio_9_o_oval(dut_io_pads_gpio_9_o_oval),
+ .io_pads_gpio_9_o_oe(dut_io_pads_gpio_9_o_oe),
+ .io_pads_gpio_9_o_ie(dut_io_pads_gpio_9_o_ie),
+ .io_pads_gpio_9_o_pue(dut_io_pads_gpio_9_o_pue),
+ .io_pads_gpio_9_o_ds(dut_io_pads_gpio_9_o_ds),
+ .io_pads_gpio_10_i_ival(dut_io_pads_gpio_10_i_ival),
+ .io_pads_gpio_10_o_oval(dut_io_pads_gpio_10_o_oval),
+ .io_pads_gpio_10_o_oe(dut_io_pads_gpio_10_o_oe),
+ .io_pads_gpio_10_o_ie(dut_io_pads_gpio_10_o_ie),
+ .io_pads_gpio_10_o_pue(dut_io_pads_gpio_10_o_pue),
+ .io_pads_gpio_10_o_ds(dut_io_pads_gpio_10_o_ds),
+ .io_pads_gpio_11_i_ival(dut_io_pads_gpio_11_i_ival),
+ .io_pads_gpio_11_o_oval(dut_io_pads_gpio_11_o_oval),
+ .io_pads_gpio_11_o_oe(dut_io_pads_gpio_11_o_oe),
+ .io_pads_gpio_11_o_ie(dut_io_pads_gpio_11_o_ie),
+ .io_pads_gpio_11_o_pue(dut_io_pads_gpio_11_o_pue),
+ .io_pads_gpio_11_o_ds(dut_io_pads_gpio_11_o_ds),
+ .io_pads_gpio_12_i_ival(dut_io_pads_gpio_12_i_ival),
+ .io_pads_gpio_12_o_oval(dut_io_pads_gpio_12_o_oval),
+ .io_pads_gpio_12_o_oe(dut_io_pads_gpio_12_o_oe),
+ .io_pads_gpio_12_o_ie(dut_io_pads_gpio_12_o_ie),
+ .io_pads_gpio_12_o_pue(dut_io_pads_gpio_12_o_pue),
+ .io_pads_gpio_12_o_ds(dut_io_pads_gpio_12_o_ds),
+ .io_pads_gpio_13_i_ival(dut_io_pads_gpio_13_i_ival),
+ .io_pads_gpio_13_o_oval(dut_io_pads_gpio_13_o_oval),
+ .io_pads_gpio_13_o_oe(dut_io_pads_gpio_13_o_oe),
+ .io_pads_gpio_13_o_ie(dut_io_pads_gpio_13_o_ie),
+ .io_pads_gpio_13_o_pue(dut_io_pads_gpio_13_o_pue),
+ .io_pads_gpio_13_o_ds(dut_io_pads_gpio_13_o_ds),
+ .io_pads_gpio_14_i_ival(dut_io_pads_gpio_14_i_ival),
+ .io_pads_gpio_14_o_oval(dut_io_pads_gpio_14_o_oval),
+ .io_pads_gpio_14_o_oe(dut_io_pads_gpio_14_o_oe),
+ .io_pads_gpio_14_o_ie(dut_io_pads_gpio_14_o_ie),
+ .io_pads_gpio_14_o_pue(dut_io_pads_gpio_14_o_pue),
+ .io_pads_gpio_14_o_ds(dut_io_pads_gpio_14_o_ds),
+ .io_pads_gpio_15_i_ival(dut_io_pads_gpio_15_i_ival),
+ .io_pads_gpio_15_o_oval(dut_io_pads_gpio_15_o_oval),
+ .io_pads_gpio_15_o_oe(dut_io_pads_gpio_15_o_oe),
+ .io_pads_gpio_15_o_ie(dut_io_pads_gpio_15_o_ie),
+ .io_pads_gpio_15_o_pue(dut_io_pads_gpio_15_o_pue),
+ .io_pads_gpio_15_o_ds(dut_io_pads_gpio_15_o_ds),
+ .io_pads_gpio_16_i_ival(dut_io_pads_gpio_16_i_ival),
+ .io_pads_gpio_16_o_oval(dut_io_pads_gpio_16_o_oval),
+ .io_pads_gpio_16_o_oe(dut_io_pads_gpio_16_o_oe),
+ .io_pads_gpio_16_o_ie(dut_io_pads_gpio_16_o_ie),
+ .io_pads_gpio_16_o_pue(dut_io_pads_gpio_16_o_pue),
+ .io_pads_gpio_16_o_ds(dut_io_pads_gpio_16_o_ds),
+ .io_pads_gpio_17_i_ival(dut_io_pads_gpio_17_i_ival),
+ .io_pads_gpio_17_o_oval(dut_io_pads_gpio_17_o_oval),
+ .io_pads_gpio_17_o_oe(dut_io_pads_gpio_17_o_oe),
+ .io_pads_gpio_17_o_ie(dut_io_pads_gpio_17_o_ie),
+ .io_pads_gpio_17_o_pue(dut_io_pads_gpio_17_o_pue),
+ .io_pads_gpio_17_o_ds(dut_io_pads_gpio_17_o_ds),
+ .io_pads_gpio_18_i_ival(dut_io_pads_gpio_18_i_ival),
+ .io_pads_gpio_18_o_oval(dut_io_pads_gpio_18_o_oval),
+ .io_pads_gpio_18_o_oe(dut_io_pads_gpio_18_o_oe),
+ .io_pads_gpio_18_o_ie(dut_io_pads_gpio_18_o_ie),
+ .io_pads_gpio_18_o_pue(dut_io_pads_gpio_18_o_pue),
+ .io_pads_gpio_18_o_ds(dut_io_pads_gpio_18_o_ds),
+ .io_pads_gpio_19_i_ival(dut_io_pads_gpio_19_i_ival),
+ .io_pads_gpio_19_o_oval(dut_io_pads_gpio_19_o_oval),
+ .io_pads_gpio_19_o_oe(dut_io_pads_gpio_19_o_oe),
+ .io_pads_gpio_19_o_ie(dut_io_pads_gpio_19_o_ie),
+ .io_pads_gpio_19_o_pue(dut_io_pads_gpio_19_o_pue),
+ .io_pads_gpio_19_o_ds(dut_io_pads_gpio_19_o_ds),
+ .io_pads_gpio_20_i_ival(dut_io_pads_gpio_20_i_ival),
+ .io_pads_gpio_20_o_oval(dut_io_pads_gpio_20_o_oval),
+ .io_pads_gpio_20_o_oe(dut_io_pads_gpio_20_o_oe),
+ .io_pads_gpio_20_o_ie(dut_io_pads_gpio_20_o_ie),
+ .io_pads_gpio_20_o_pue(dut_io_pads_gpio_20_o_pue),
+ .io_pads_gpio_20_o_ds(dut_io_pads_gpio_20_o_ds),
+ .io_pads_gpio_21_i_ival(dut_io_pads_gpio_21_i_ival),
+ .io_pads_gpio_21_o_oval(dut_io_pads_gpio_21_o_oval),
+ .io_pads_gpio_21_o_oe(dut_io_pads_gpio_21_o_oe),
+ .io_pads_gpio_21_o_ie(dut_io_pads_gpio_21_o_ie),
+ .io_pads_gpio_21_o_pue(dut_io_pads_gpio_21_o_pue),
+ .io_pads_gpio_21_o_ds(dut_io_pads_gpio_21_o_ds),
+ .io_pads_gpio_22_i_ival(dut_io_pads_gpio_22_i_ival),
+ .io_pads_gpio_22_o_oval(dut_io_pads_gpio_22_o_oval),
+ .io_pads_gpio_22_o_oe(dut_io_pads_gpio_22_o_oe),
+ .io_pads_gpio_22_o_ie(dut_io_pads_gpio_22_o_ie),
+ .io_pads_gpio_22_o_pue(dut_io_pads_gpio_22_o_pue),
+ .io_pads_gpio_22_o_ds(dut_io_pads_gpio_22_o_ds),
+ .io_pads_gpio_23_i_ival(dut_io_pads_gpio_23_i_ival),
+ .io_pads_gpio_23_o_oval(dut_io_pads_gpio_23_o_oval),
+ .io_pads_gpio_23_o_oe(dut_io_pads_gpio_23_o_oe),
+ .io_pads_gpio_23_o_ie(dut_io_pads_gpio_23_o_ie),
+ .io_pads_gpio_23_o_pue(dut_io_pads_gpio_23_o_pue),
+ .io_pads_gpio_23_o_ds(dut_io_pads_gpio_23_o_ds),
+ .io_pads_gpio_24_i_ival(dut_io_pads_gpio_24_i_ival),
+ .io_pads_gpio_24_o_oval(dut_io_pads_gpio_24_o_oval),
+ .io_pads_gpio_24_o_oe(dut_io_pads_gpio_24_o_oe),
+ .io_pads_gpio_24_o_ie(dut_io_pads_gpio_24_o_ie),
+ .io_pads_gpio_24_o_pue(dut_io_pads_gpio_24_o_pue),
+ .io_pads_gpio_24_o_ds(dut_io_pads_gpio_24_o_ds),
+ .io_pads_gpio_25_i_ival(dut_io_pads_gpio_25_i_ival),
+ .io_pads_gpio_25_o_oval(dut_io_pads_gpio_25_o_oval),
+ .io_pads_gpio_25_o_oe(dut_io_pads_gpio_25_o_oe),
+ .io_pads_gpio_25_o_ie(dut_io_pads_gpio_25_o_ie),
+ .io_pads_gpio_25_o_pue(dut_io_pads_gpio_25_o_pue),
+ .io_pads_gpio_25_o_ds(dut_io_pads_gpio_25_o_ds),
+ .io_pads_gpio_26_i_ival(dut_io_pads_gpio_26_i_ival),
+ .io_pads_gpio_26_o_oval(dut_io_pads_gpio_26_o_oval),
+ .io_pads_gpio_26_o_oe(dut_io_pads_gpio_26_o_oe),
+ .io_pads_gpio_26_o_ie(dut_io_pads_gpio_26_o_ie),
+ .io_pads_gpio_26_o_pue(dut_io_pads_gpio_26_o_pue),
+ .io_pads_gpio_26_o_ds(dut_io_pads_gpio_26_o_ds),
+ .io_pads_gpio_27_i_ival(dut_io_pads_gpio_27_i_ival),
+ .io_pads_gpio_27_o_oval(dut_io_pads_gpio_27_o_oval),
+ .io_pads_gpio_27_o_oe(dut_io_pads_gpio_27_o_oe),
+ .io_pads_gpio_27_o_ie(dut_io_pads_gpio_27_o_ie),
+ .io_pads_gpio_27_o_pue(dut_io_pads_gpio_27_o_pue),
+ .io_pads_gpio_27_o_ds(dut_io_pads_gpio_27_o_ds),
+ .io_pads_gpio_28_i_ival(dut_io_pads_gpio_28_i_ival),
+ .io_pads_gpio_28_o_oval(dut_io_pads_gpio_28_o_oval),
+ .io_pads_gpio_28_o_oe(dut_io_pads_gpio_28_o_oe),
+ .io_pads_gpio_28_o_ie(dut_io_pads_gpio_28_o_ie),
+ .io_pads_gpio_28_o_pue(dut_io_pads_gpio_28_o_pue),
+ .io_pads_gpio_28_o_ds(dut_io_pads_gpio_28_o_ds),
+ .io_pads_gpio_29_i_ival(dut_io_pads_gpio_29_i_ival),
+ .io_pads_gpio_29_o_oval(dut_io_pads_gpio_29_o_oval),
+ .io_pads_gpio_29_o_oe(dut_io_pads_gpio_29_o_oe),
+ .io_pads_gpio_29_o_ie(dut_io_pads_gpio_29_o_ie),
+ .io_pads_gpio_29_o_pue(dut_io_pads_gpio_29_o_pue),
+ .io_pads_gpio_29_o_ds(dut_io_pads_gpio_29_o_ds),
+ .io_pads_gpio_30_i_ival(dut_io_pads_gpio_30_i_ival),
+ .io_pads_gpio_30_o_oval(dut_io_pads_gpio_30_o_oval),
+ .io_pads_gpio_30_o_oe(dut_io_pads_gpio_30_o_oe),
+ .io_pads_gpio_30_o_ie(dut_io_pads_gpio_30_o_ie),
+ .io_pads_gpio_30_o_pue(dut_io_pads_gpio_30_o_pue),
+ .io_pads_gpio_30_o_ds(dut_io_pads_gpio_30_o_ds),
+ .io_pads_gpio_31_i_ival(dut_io_pads_gpio_31_i_ival),
+ .io_pads_gpio_31_o_oval(dut_io_pads_gpio_31_o_oval),
+ .io_pads_gpio_31_o_oe(dut_io_pads_gpio_31_o_oe),
+ .io_pads_gpio_31_o_ie(dut_io_pads_gpio_31_o_ie),
+ .io_pads_gpio_31_o_pue(dut_io_pads_gpio_31_o_pue),
+ .io_pads_gpio_31_o_ds(dut_io_pads_gpio_31_o_ds),
+ .io_pads_qspi_sck_i_ival(dut_io_pads_qspi_sck_i_ival),
+ .io_pads_qspi_sck_o_oval(dut_io_pads_qspi_sck_o_oval),
+ .io_pads_qspi_sck_o_oe(dut_io_pads_qspi_sck_o_oe),
+ .io_pads_qspi_sck_o_ie(dut_io_pads_qspi_sck_o_ie),
+ .io_pads_qspi_sck_o_pue(dut_io_pads_qspi_sck_o_pue),
+ .io_pads_qspi_sck_o_ds(dut_io_pads_qspi_sck_o_ds),
+ .io_pads_qspi_dq_0_i_ival(dut_io_pads_qspi_dq_0_i_ival),
+ .io_pads_qspi_dq_0_o_oval(dut_io_pads_qspi_dq_0_o_oval),
+ .io_pads_qspi_dq_0_o_oe(dut_io_pads_qspi_dq_0_o_oe),
+ .io_pads_qspi_dq_0_o_ie(dut_io_pads_qspi_dq_0_o_ie),
+ .io_pads_qspi_dq_0_o_pue(dut_io_pads_qspi_dq_0_o_pue),
+ .io_pads_qspi_dq_0_o_ds(dut_io_pads_qspi_dq_0_o_ds),
+ .io_pads_qspi_dq_1_i_ival(dut_io_pads_qspi_dq_1_i_ival),
+ .io_pads_qspi_dq_1_o_oval(dut_io_pads_qspi_dq_1_o_oval),
+ .io_pads_qspi_dq_1_o_oe(dut_io_pads_qspi_dq_1_o_oe),
+ .io_pads_qspi_dq_1_o_ie(dut_io_pads_qspi_dq_1_o_ie),
+ .io_pads_qspi_dq_1_o_pue(dut_io_pads_qspi_dq_1_o_pue),
+ .io_pads_qspi_dq_1_o_ds(dut_io_pads_qspi_dq_1_o_ds),
+ .io_pads_qspi_dq_2_i_ival(dut_io_pads_qspi_dq_2_i_ival),
+ .io_pads_qspi_dq_2_o_oval(dut_io_pads_qspi_dq_2_o_oval),
+ .io_pads_qspi_dq_2_o_oe(dut_io_pads_qspi_dq_2_o_oe),
+ .io_pads_qspi_dq_2_o_ie(dut_io_pads_qspi_dq_2_o_ie),
+ .io_pads_qspi_dq_2_o_pue(dut_io_pads_qspi_dq_2_o_pue),
+ .io_pads_qspi_dq_2_o_ds(dut_io_pads_qspi_dq_2_o_ds),
+ .io_pads_qspi_dq_3_i_ival(dut_io_pads_qspi_dq_3_i_ival),
+ .io_pads_qspi_dq_3_o_oval(dut_io_pads_qspi_dq_3_o_oval),
+ .io_pads_qspi_dq_3_o_oe(dut_io_pads_qspi_dq_3_o_oe),
+ .io_pads_qspi_dq_3_o_ie(dut_io_pads_qspi_dq_3_o_ie),
+ .io_pads_qspi_dq_3_o_pue(dut_io_pads_qspi_dq_3_o_pue),
+ .io_pads_qspi_dq_3_o_ds(dut_io_pads_qspi_dq_3_o_ds),
+ .io_pads_qspi_cs_0_i_ival(dut_io_pads_qspi_cs_0_i_ival),
+ .io_pads_qspi_cs_0_o_oval(dut_io_pads_qspi_cs_0_o_oval),
+ .io_pads_qspi_cs_0_o_oe(dut_io_pads_qspi_cs_0_o_oe),
+ .io_pads_qspi_cs_0_o_ie(dut_io_pads_qspi_cs_0_o_ie),
+ .io_pads_qspi_cs_0_o_pue(dut_io_pads_qspi_cs_0_o_pue),
+ .io_pads_qspi_cs_0_o_ds(dut_io_pads_qspi_cs_0_o_ds),
+ .io_pads_aon_erst_n_i_ival(dut_io_pads_aon_erst_n_i_ival),
+ .io_pads_aon_erst_n_o_oval(dut_io_pads_aon_erst_n_o_oval),
+ .io_pads_aon_erst_n_o_oe(dut_io_pads_aon_erst_n_o_oe),
+ .io_pads_aon_erst_n_o_ie(dut_io_pads_aon_erst_n_o_ie),
+ .io_pads_aon_erst_n_o_pue(dut_io_pads_aon_erst_n_o_pue),
+ .io_pads_aon_erst_n_o_ds(dut_io_pads_aon_erst_n_o_ds),
+ .io_pads_aon_lfextclk_i_ival(dut_io_pads_aon_lfextclk_i_ival),
+ .io_pads_aon_lfextclk_o_oval(dut_io_pads_aon_lfextclk_o_oval),
+ .io_pads_aon_lfextclk_o_oe(dut_io_pads_aon_lfextclk_o_oe),
+ .io_pads_aon_lfextclk_o_ie(dut_io_pads_aon_lfextclk_o_ie),
+ .io_pads_aon_lfextclk_o_pue(dut_io_pads_aon_lfextclk_o_pue),
+ .io_pads_aon_lfextclk_o_ds(dut_io_pads_aon_lfextclk_o_ds),
+ .io_pads_aon_pmu_dwakeup_n_i_ival(dut_io_pads_aon_pmu_dwakeup_n_i_ival),
+ .io_pads_aon_pmu_dwakeup_n_o_oval(dut_io_pads_aon_pmu_dwakeup_n_o_oval),
+ .io_pads_aon_pmu_dwakeup_n_o_oe(dut_io_pads_aon_pmu_dwakeup_n_o_oe),
+ .io_pads_aon_pmu_dwakeup_n_o_ie(dut_io_pads_aon_pmu_dwakeup_n_o_ie),
+ .io_pads_aon_pmu_dwakeup_n_o_pue(dut_io_pads_aon_pmu_dwakeup_n_o_pue),
+ .io_pads_aon_pmu_dwakeup_n_o_ds(dut_io_pads_aon_pmu_dwakeup_n_o_ds),
+ .io_pads_aon_pmu_vddpaden_i_ival(dut_io_pads_aon_pmu_vddpaden_i_ival),
+ .io_pads_aon_pmu_vddpaden_o_oval(dut_io_pads_aon_pmu_vddpaden_o_oval),
+ .io_pads_aon_pmu_vddpaden_o_oe(dut_io_pads_aon_pmu_vddpaden_o_oe),
+ .io_pads_aon_pmu_vddpaden_o_ie(dut_io_pads_aon_pmu_vddpaden_o_ie),
+ .io_pads_aon_pmu_vddpaden_o_pue(dut_io_pads_aon_pmu_vddpaden_o_pue),
+ .io_pads_aon_pmu_vddpaden_o_ds(dut_io_pads_aon_pmu_vddpaden_o_ds)
+ );
+
+ // Assign reasonable values to otherwise unconnected inputs to chip top
+
+ wire iobuf_dwakeup_o;
+ IOBUF
+ #(
+ .DRIVE(12),
+ .IBUF_LOW_PWR("TRUE"),
+ .IOSTANDARD("DEFAULT"),
+ .SLEW("SLOW")
+ )
+ IOBUF_dwakeup_n
+ (
+ .O(iobuf_dwakeup_o),
+ .IO(btn_3),
+ .I(~dut_io_pads_aon_pmu_dwakeup_n_o_oval),
+ .T(~dut_io_pads_aon_pmu_dwakeup_n_o_oe)
+ );
+ assign dut_io_pads_aon_pmu_dwakeup_n_i_ival = (~iobuf_dwakeup_o) & dut_io_pads_aon_pmu_dwakeup_n_o_ie;
+
+ assign dut_io_pads_aon_erst_n_i_ival = ~reset_periph;
+ assign dut_io_pads_aon_lfextclk_i_ival = slowclk;
+
+ assign dut_io_pads_aon_pmu_vddpaden_i_ival = 1'b1;
+
+ assign qspi_cs = dut_io_pads_qspi_cs_0_o_oval;
+ assign qspi_ui_dq_o = {
+ dut_io_pads_qspi_dq_3_o_oval,
+ dut_io_pads_qspi_dq_2_o_oval,
+ dut_io_pads_qspi_dq_1_o_oval,
+ dut_io_pads_qspi_dq_0_o_oval
+ };
+ assign qspi_ui_dq_oe = {
+ dut_io_pads_qspi_dq_3_o_oe,
+ dut_io_pads_qspi_dq_2_o_oe,
+ dut_io_pads_qspi_dq_1_o_oe,
+ dut_io_pads_qspi_dq_0_o_oe
+ };
+ assign dut_io_pads_qspi_dq_0_i_ival = qspi_ui_dq_i[0];
+ assign dut_io_pads_qspi_dq_1_i_ival = qspi_ui_dq_i[1];
+ assign dut_io_pads_qspi_dq_2_i_ival = qspi_ui_dq_i[2];
+ assign dut_io_pads_qspi_dq_3_i_ival = qspi_ui_dq_i[3];
+ assign qspi_sck = dut_io_pads_qspi_sck_o_oval;
+endmodule
+
+// Divide clock by 256, used to generate 32.768 kHz clock for AON block
+module clkdivider
+(
+ input wire clk,
+ input wire reset,
+ output reg clk_out
+);
+
+ reg [7:0] counter;
+
+ always @(posedge clk)
+ begin
+ if (reset)
+ begin
+ counter <= 8'd0;
+ clk_out <= 1'b0;
+ end
+ else if (counter == 8'hff)
+ begin
+ counter <= 8'd0;
+ clk_out <= ~clk_out;
+ end
+ else
+ begin
+ counter <= counter+1;
+ end
+ end
+endmodule
--- /dev/null
+VIVADO ?= vivado
+VIVADOFLAGS := \
+ -nojournal -mode batch \
+ -source script/board.tcl \
+ -source script/prologue.tcl
+
+bit := obj/system.bit
+$(bit): script/impl.tcl script/init.tcl
+ VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
+
+.PHONY: bit
+bit: $(bit)
+
+mcs := obj/system.mcs
+$(mcs): $(bit)
+ $(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^
+
+.PHONY: mcs
+mcs: $(mcs)
+
+.PHONY: clean
+clean::
+ rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log
--- /dev/null
+#---------------Physical Constraints-----------------
+
+set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
+set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
+set_property BOARD_PIN {reset} [get_ports reset]
+
+# The MIG has its own create_clock
+#create_clock -name ddr_ref_clk -period 5.0 [get_ports sys_diff_clock_clk_p]
+set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5
+
+set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led[0]]
+set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led[1]]
+set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led[2]]
+set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led[3]]
+set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led[4]]
+set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led[5]]
+set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led[6]]
+set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led[7]]
+
+set_property PACKAGE_PIN AU33 [get_ports uart_rx]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
+set_property IOB TRUE [get_ports uart_rx]
+set_property PACKAGE_PIN AT32 [get_ports uart_ctsn]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn]
+set_property IOB TRUE [get_ports uart_ctsn]
+set_property PACKAGE_PIN AU36 [get_ports uart_tx]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_tx]
+set_property IOB TRUE [get_ports uart_tx]
+set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
+set_property IOB TRUE [get_ports uart_rtsn]
+
+set_property IOB TRUE [get_cells "top/uart0/txm/out_reg"]
+set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
+
+
+# PCI Express
+#FMC 1 refclk
+#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports {pci_exp_refclk_rxp}]
+set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
+set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
+create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
+set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
+
+set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
+set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
+
+set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
+set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
+
+# JTAG
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
+set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
+set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
+set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
+set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
+
+# SDIO
+#set_property -dict { PACKAGE_PIN AR32 IOSTANDARD LVCMOS18 } [get_ports {sdio_sdwp}]
+#set_property -dict { PACKAGE_PIN AP32 IOSTANDARD LVCMOS18 } [get_ports {sdio_sddet}]
+set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
+set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
+set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[0]}]
+set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
+set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
+set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
+
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up_d"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_cs*"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/pcie_bme"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/arready_int"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/en_barhit"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_ns*"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/illegal_burst_int"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_req_sent"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/slot_request"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/open_slot"]
+#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
+
+#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_2/state*"]
+#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_1_1/*acquire*"]
+#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/io_*"]
+
+set_clock_groups -asynchronous \
+ -group [list \
+ [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]] \
+ -group [list \
+ [get_clocks -include_generated_clocks -of_objects [get_ports sys_diff_clock_clk_p]]]
--- /dev/null
+# See LICENSE for license details.
+set name {vc707}
+set part_fpga {xc7vx485tffg1761-2}
+set part_board {xilinx.com:vc707:part0:1.3}
+set bootrom_inst {rom}
--- /dev/null
+lassign $argv mcsfile bitfile datafile
+
+set iface bpix16
+set size 128
+set bitaddr 0x3000000
+
+write_cfgmem -format mcs -interface $iface -size $size \
+ -loadbit "up ${bitaddr} ${bitfile}" \
+ -loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
+ -file $mcsfile -force
--- /dev/null
+set_param {messaging.defaultLimit} 1000000
+
+read_ip [glob -directory $ipdir [file join * {*.xci}]]
+
+synth_design -top $top -flatten_hierarchy rebuilt
+write_checkpoint -force [file join $wrkdir post_synth]
+
+opt_design
+write_checkpoint -force [file join $wrkdir post_opt]
+
+place_design
+write_checkpoint -force [file join $wrkdir post_place]
+
+phys_opt_design
+power_opt_design
+route_design
+write_checkpoint -force [file join $wrkdir post_route]
+
+write_bitstream -force [file join $wrkdir "${top}.bit"]
+write_sdf -force [file join $wrkdir "${top}.sdf"]
+write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
+write_debug_probes -force [file join $wrkdir "${top}.ltx"]
+
+# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
+# Work around the write_mem_info command not supporting "processor-less"
+# (non-Microblaze) designs.
+set bram_inst [get_cells -hierarchical "bram"]
+if {$bram_inst ne ""} {
+ source [file join $scriptdir "bram.tcl"]
+ write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
+}
+
+if {[info exists bootrom_inst]} {
+ puts "Generating bootrom.mmi ..."
+ set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
+ if {$rom_inst ne ""} {
+ source [file join $scriptdir "bram.tcl"]
+ write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
+ }
+}
+
+set rptdir [file join $wrkdir report]
+file mkdir $rptdir
+set rptutil [file join $rptdir utilization.txt]
+report_datasheet -file [file join $rptdir datasheet.txt]
+report_utilization -hierarchical -file $rptutil
+report_clock_utilization -file $rptutil -append
+report_ram_utilization -file $rptutil -append -detail
+report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
+report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
+report_drc -file [file join $rptdir drc.txt]
+report_io -file [file join $rptdir io.txt]
+report_clocks -file [file join $rptdir clocks.txt]
--- /dev/null
+proc recglob { basedir pattern } {
+ set dirlist [glob -nocomplain -directory $basedir -type d *]
+ set findlist [glob -nocomplain -directory $basedir $pattern]
+ foreach dir $dirlist {
+ set reclist [recglob $dir $pattern]
+ set findlist [concat $findlist $reclist]
+ }
+ return $findlist
+}
+
+proc findincludedir { basedir pattern } {
+ #find all subdirectories containing ".vh" files
+ set vhfiles [recglob $basedir $pattern]
+ set vhdirs {}
+ foreach match $vhfiles {
+ lappend vhdirs [file dir $match]
+ }
+ set uniquevhdirs [lsort -unique $vhdirs]
+ return $uniquevhdirs
+}
+
+file mkdir $ipdir
+update_ip_catalog -rebuild
+
+source [file join $scriptdir ip.tcl]
+
+# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
+set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
+set obj [get_ips]
+generate_target all $obj
+export_ip_user_files -of_objects $obj -no_script -force
+
+set obj [current_fileset]
+
+# Xilinx bug workaround
+# scrape IP tree for directories containing .vh files
+# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
+set property_include_dirs [get_property include_dirs $obj]
+set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
+set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]
--- /dev/null
+#MIG
+create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force
+set migprj [file join [pwd] $scriptdir {mig.prj}]
+set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig]
+
+puts "SCRIPTDIR $scriptdir"
+
+#AXI_PCIE
+create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
+set_property -dict [list \
+CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
+CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
+CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
+CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
+CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
+CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
+CONFIG.AXIBAR_0 {0x60000000} \
+CONFIG.AXIBAR_1 {0xFFFFFFFF} \
+CONFIG.AXIBAR_2 {0xFFFFFFFF} \
+CONFIG.AXIBAR_3 {0xFFFFFFFF} \
+CONFIG.AXIBAR_4 {0xFFFFFFFF} \
+CONFIG.AXIBAR_5 {0xFFFFFFFF} \
+CONFIG.AXIBAR_AS_0 {true} \
+CONFIG.AXIBAR_AS_1 {false} \
+CONFIG.AXIBAR_AS_2 {false} \
+CONFIG.AXIBAR_AS_3 {false} \
+CONFIG.AXIBAR_AS_4 {false} \
+CONFIG.AXIBAR_AS_5 {false} \
+CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
+CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
+CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
+CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
+CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \
+CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \
+CONFIG.AXIBAR_NUM {1} \
+CONFIG.BAR0_ENABLED {true} \
+CONFIG.BAR0_SCALE {Gigabytes} \
+CONFIG.BAR0_SIZE {4} \
+CONFIG.BAR0_TYPE {Memory} \
+CONFIG.BAR1_ENABLED {false} \
+CONFIG.BAR1_SCALE {N/A} \
+CONFIG.BAR1_SIZE {8} \
+CONFIG.BAR1_TYPE {N/A} \
+CONFIG.BAR2_ENABLED {false} \
+CONFIG.BAR2_SCALE {N/A} \
+CONFIG.BAR2_SIZE {8} \
+CONFIG.BAR2_TYPE {N/A} \
+CONFIG.BAR_64BIT {true} \
+CONFIG.BASEADDR {0x50000000} \
+CONFIG.BASE_CLASS_MENU {Bridge_device} \
+CONFIG.CLASS_CODE {0x060400} \
+CONFIG.COMP_TIMEOUT {50us} \
+CONFIG.Component_Name {design_1_axi_pcie_1_0} \
+CONFIG.DEVICE_ID {0x7111} \
+CONFIG.ENABLE_CLASS_CODE {true} \
+CONFIG.HIGHADDR {0x53FFFFFF} \
+CONFIG.INCLUDE_BAROFFSET_REG {true} \
+CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
+CONFIG.INTERRUPT_PIN {false} \
+CONFIG.MAX_LINK_SPEED {2.5_GT/s} \
+CONFIG.MSI_DECODE_ENABLED {true} \
+CONFIG.M_AXI_ADDR_WIDTH {32} \
+CONFIG.M_AXI_DATA_WIDTH {64} \
+CONFIG.NO_OF_LANES {X1} \
+CONFIG.NUM_MSI_REQ {0} \
+CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \
+CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \
+CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \
+CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \
+CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \
+CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \
+CONFIG.PCIE_BLK_LOCN {X1Y1} \
+CONFIG.PCIE_USE_MODE {GES_and_Production} \
+CONFIG.REF_CLK_FREQ {100_MHz} \
+CONFIG.REV_ID {0x00} \
+CONFIG.SLOT_CLOCK_CONFIG {true} \
+CONFIG.SUBSYSTEM_ID {0x0007} \
+CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \
+CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \
+CONFIG.S_AXI_ADDR_WIDTH {32} \
+CONFIG.S_AXI_DATA_WIDTH {64} \
+CONFIG.S_AXI_ID_WIDTH {4} \
+CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \
+CONFIG.VENDOR_ID {0x10EE} \
+CONFIG.XLNX_REF_BOARD {None} \
+CONFIG.axi_aclk_loopback {false} \
+CONFIG.en_ext_ch_gt_drp {false} \
+CONFIG.en_ext_clk {false} \
+CONFIG.en_ext_gt_common {false} \
+CONFIG.en_ext_pipe_interface {false} \
+CONFIG.en_transceiver_status_ports {false} \
+CONFIG.no_slv_err {false} \
+CONFIG.rp_bar_hide {true} \
+CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]
+
+
+
--- /dev/null
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+ <ModuleName>vc707mig</ModuleName>
+ <dci_inouts_inputs>1</dci_inouts_inputs>
+ <dci_inputs>1</dci_inputs>
+ <Debug_En>OFF</Debug_En>
+ <DataDepth_En>1024</DataDepth_En>
+ <LowPower_En>ON</LowPower_En>
+ <XADC_En>Enabled</XADC_En>
+ <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
+ <Version>3.0</Version>
+ <SystemClock>Differential</SystemClock>
+ <ReferenceClock>Use System Clock</ReferenceClock>
+ <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+ <BankSelectionFlag>FALSE</BankSelectionFlag>
+ <InternalVref>0</InternalVref>
+ <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+ <dci_cascade>0</dci_cascade>
+ <Controller number="0" >
+ <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
+ <TimePeriod>1250</TimePeriod>
+ <VccAuxIO>2.0V</VccAuxIO>
+ <PHYRatio>4:1</PHYRatio>
+ <InputClkFreq>200</InputClkFreq>
+ <UIExtraClocks>0</UIExtraClocks>
+ <MMCM_VCO>800</MMCM_VCO>
+ <MMCMClkOut0> 1.000</MMCMClkOut0>
+ <MMCMClkOut1>1</MMCMClkOut1>
+ <MMCMClkOut2>1</MMCMClkOut2>
+ <MMCMClkOut3>1</MMCMClkOut3>
+ <MMCMClkOut4>1</MMCMClkOut4>
+ <DataWidth>64</DataWidth>
+ <DeepMemory>1</DeepMemory>
+ <DataMask>1</DataMask>
+ <ECC>Disabled</ECC>
+ <Ordering>Normal</Ordering>
+ <CustomPart>FALSE</CustomPart>
+ <NewPartName></NewPartName>
+ <RowAddress>14</RowAddress>
+ <ColAddress>10</ColAddress>
+ <BankAddress>3</BankAddress>
+ <MemoryVoltage>1.5V</MemoryVoltage>
+ <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+ <PinSelection>
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
+ <Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
+ </PinSelection>
+ <System_Clock>
+ <Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
+ </System_Clock>
+ <System_Control>
+ <Pin PADName="AV40" Bank="15" name="sys_rst" />
+ <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+ <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+ </System_Control>
+ <TimingParameters>
+ <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
+ </TimingParameters>
+ <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+ <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+ <mrCasLatency name="CAS Latency" >11</mrCasLatency>
+ <mrMode name="Mode" >Normal</mrMode>
+ <mrDllReset name="DLL Reset" >No</mrDllReset>
+ <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+ <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+ <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
+ <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+ <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+ <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+ <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+ <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+ <emrDQS name="TDQS enable" >Enabled</emrDQS>
+ <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+ <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+ <mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
+ <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+ <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+ <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+ <PortInterface>AXI</PortInterface>
+ <AXIParameters>
+ <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+ <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
+ <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
+ <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+ <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+ </AXIParameters>
+ </Controller>
+
+</Project>
--- /dev/null
+set scriptdir [file dirname [info script]]
+set commondir [file dirname $scriptdir]
+set srcdir [file join $commondir src]
+set constrsdir [file join $commondir constrs]
+
+set wrkdir [file join [pwd] obj]
+set ipdir [file join $wrkdir ip]
+
+set top {system}
+
+create_project -part $part_fpga -in_memory
+set_property -dict [list \
+ BOARD_PART $part_board \
+ TARGET_LANGUAGE {Verilog} \
+ SIMULATOR_LANGUAGE {Mixed} \
+ TARGET_SIMULATOR {XSim} \
+ DEFAULT_LIB {xil_defaultlib} \
+ IP_REPO_PATHS $ipdir \
+ ] [current_project]
+
+proc recglob { basedir pattern } {
+ set dirlist [glob -nocomplain -directory $basedir -type d *]
+ set findlist [glob -nocomplain -directory $basedir $pattern]
+ foreach dir $dirlist {
+ set reclist [recglob $dir $pattern]
+ set findlist [concat $findlist $reclist]
+ }
+ return $findlist
+}
+
+
+if {[get_filesets -quiet sources_1] eq ""} {
+ create_fileset -srcset sources_1
+}
+set obj [current_fileset]
+
+set srcmainverilogfiles [recglob $srcdir "*.v"]
+add_files -norecurse -fileset $obj $srcmainverilogfiles
+
+if {[info exists ::env(EXTRA_VSRCS)]} {
+ set extra_vsrcs [split $::env(EXTRA_VSRCS)]
+ foreach extra_vsrc $extra_vsrcs {
+ add_files -norecurse -fileset $obj $extra_vsrc
+ }
+}
+## TODO: These paths and files should come from the caller, not within this script.
+#if {[file exists [file join $srcdir include verilog]]} {
+# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
+# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
+#}
+
+set vsrc_top $::env(VSRC_TOP)
+set vsrc_consts $::env(VSRC_CONSTS)
+
+set_property verilog_define [list \
+ "VSRC_CONSTS=${vsrc_consts}" \
+ "VSRC_TOP=${vsrc_top}" \
+ ] $obj
+
+add_files -norecurse -fileset $obj $vsrc_top
+add_files -norecurse -fileset $obj $vsrc_consts
+
+if {[get_filesets -quiet sim_1] eq ""} {
+ create_fileset -simset sim_1
+}
+set obj [current_fileset -simset]
+add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
+set_property TOP {tb} $obj
+
+if {[get_filesets -quiet constrs_1] eq ""} {
+ create_fileset -constrset constrs_1
+}
+set obj [current_fileset -constrset]
+add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]
--- /dev/null
+// See LICENSE for license details.
+`timescale 1ns/1ps
+`default_nettype none
+
+module sdio_spi_bridge (
+ input wire clk,
+ input wire reset,
+ // SDIO
+ inout wire sd_cmd,
+ inout wire [3:0] sd_dat,
+ output wire sd_sck,
+ // QUAD SPI
+ input wire spi_sck,
+ input wire [3:0] spi_dq_o,
+ output wire [3:0] spi_dq_i,
+ output wire spi_cs
+);
+
+ wire mosi, miso;
+ reg miso_sync [1:0];
+
+ assign mosi = spi_dq_o[0];
+ assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
+
+ assign sd_sck = spi_sck;
+
+ IOBUF buf_cmd (
+ .IO(sd_cmd),
+ .I(mosi),
+ .O(),
+ .T(1'b0)
+ );
+
+ IOBUF buf_dat0 (
+ .IO(sd_dat[0]),
+ .I(),
+ .O(miso),
+ .T(1'b1)
+ );
+
+ IOBUF buf_dat3 (
+ .IO(sd_dat[3]),
+ .I(spi_cs),
+ .O(),
+ .T(1'b0)
+ );
+
+ always @(posedge clk) begin
+ if (reset) begin
+ miso_sync[0] <= 1'b0;
+ miso_sync[1] <= 1'b0;
+ end else begin
+ miso_sync[0] <= miso;
+ miso_sync[1] <= miso_sync[0];
+ end
+ end
+endmodule
+
+`default_nettype wire
--- /dev/null
+// See LICENSE for license details.
+`timescale 1ns/1ps
+`default_nettype none
+
+`define STRINGIFY(x) `"x`"
+`include `STRINGIFY(`VSRC_CONSTS)
+
+module system
+(
+ //200Mhz differential sysclk
+ input wire sys_diff_clock_clk_n,
+ input wire sys_diff_clock_clk_p,
+ //active high reset
+ input wire reset,
+ // DDR3 SDRAM
+ output wire [13:0] ddr3_addr,
+ output wire [2:0] ddr3_ba,
+ output wire ddr3_cas_n,
+ output wire [0:0] ddr3_ck_n,
+ output wire [0:0] ddr3_ck_p,
+ output wire [0:0] ddr3_cke,
+ output wire [0:0] ddr3_cs_n,
+ output wire [7:0] ddr3_dm,
+ inout wire [63:0] ddr3_dq,
+ inout wire [7:0] ddr3_dqs_n,
+ inout wire [7:0] ddr3_dqs_p,
+ output wire [0:0] ddr3_odt,
+ output wire ddr3_ras_n,
+ output wire ddr3_reset_n,
+ output wire ddr3_we_n,
+ // LED
+ output wire [7:0] led,
+ //UART
+ output wire uart_tx,
+ input wire uart_rx,
+ output wire uart_rtsn,
+ input wire uart_ctsn,
+ //SDIO
+ output wire sdio_clk,
+ inout wire sdio_cmd,
+ inout wire [3:0] sdio_dat,
+ //JTAG
+ input wire jtag_TCK,
+ input wire jtag_TMS,
+ input wire jtag_TDI,
+ output wire jtag_TDO,
+ //PCIe
+ output wire [0:0] pci_exp_txp,
+ output wire [0:0] pci_exp_txn,
+ input wire [0:0] pci_exp_rxp,
+ input wire [0:0] pci_exp_rxn,
+ input wire pci_exp_refclk_rxp,
+ input wire pci_exp_refclk_rxn
+);
+
+reg [1:0] uart_rx_sync;
+wire [3:0] sd_spi_dq_i;
+wire [3:0] sd_spi_dq_o;
+wire sd_spi_sck;
+wire sd_spi_cs;
+wire top_clock,top_reset;
+
+U500VC707DevKitTop top
+(
+ //UART
+ .io_uarts_0_rxd(uart_rx_sync[1]),
+ .io_uarts_0_txd(uart_tx),
+ //SPI
+ .io_spis_0_sck(sd_spi_sck),
+ .io_spis_0_dq_0_i(sd_spi_dq_i[0]),
+ .io_spis_0_dq_1_i(sd_spi_dq_i[1]),
+ .io_spis_0_dq_2_i(sd_spi_dq_i[2]),
+ .io_spis_0_dq_3_i(sd_spi_dq_i[3]),
+ .io_spis_0_dq_0_o(sd_spi_dq_o[0]),
+ .io_spis_0_dq_1_o(sd_spi_dq_o[1]),
+ .io_spis_0_dq_2_o(sd_spi_dq_o[2]),
+ .io_spis_0_dq_3_o(sd_spi_dq_o[3]),
+ .io_spis_0_dq_0_oe(),
+ .io_spis_0_dq_1_oe(),
+ .io_spis_0_dq_2_oe(),
+ .io_spis_0_dq_3_oe(),
+ .io_spis_0_cs_0(sd_spi_cs),
+ //GPIO
+ .io_gpio_pins_0_i_ival(1'b0),
+ .io_gpio_pins_1_i_ival(1'b0),
+ .io_gpio_pins_2_i_ival(1'b0),
+ .io_gpio_pins_3_i_ival(1'b0),
+ .io_gpio_pins_0_o_oval(led[0]),
+ .io_gpio_pins_1_o_oval(led[1]),
+ .io_gpio_pins_2_o_oval(led[2]),
+ .io_gpio_pins_3_o_oval(led[3]),
+ .io_gpio_pins_0_o_oe(),
+ .io_gpio_pins_1_o_oe(),
+ .io_gpio_pins_2_o_oe(),
+ .io_gpio_pins_3_o_oe(),
+ .io_gpio_pins_0_o_pue(),
+ .io_gpio_pins_1_o_pue(),
+ .io_gpio_pins_2_o_pue(),
+ .io_gpio_pins_3_o_pue(),
+ .io_gpio_pins_0_o_ds(),
+ .io_gpio_pins_1_o_ds(),
+ .io_gpio_pins_2_o_ds(),
+ .io_gpio_pins_3_o_ds(),
+ //JTAG
+ .io_jtag_TRST(1'b0),
+ .io_jtag_TCK(jtag_TCK),
+ .io_jtag_TMS(jtag_TMS),
+ .io_jtag_TDI(jtag_TDI),
+ .io_jtag_DRV_TDO(),
+ .io_jtag_TDO(jtag_TDO),
+ //MIG
+ .io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
+ .io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
+ .io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
+ .io_xilinxvc707mig_ddr3_addr(ddr3_addr),
+ .io_xilinxvc707mig_ddr3_ba(ddr3_ba),
+ .io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
+ .io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
+ .io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
+ .io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
+ .io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
+ .io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
+ .io_xilinxvc707mig_ddr3_cke(ddr3_cke),
+ .io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
+ .io_xilinxvc707mig_ddr3_dm(ddr3_dm),
+ .io_xilinxvc707mig_ddr3_odt(ddr3_odt),
+ //PCIe
+ .io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
+ .io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
+ .io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
+ .io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
+ //Clock + Reset
+ .io_pcie_refclk_p(pci_exp_refclk_rxp),
+ .io_pcie_refclk_n(pci_exp_refclk_rxn),
+ .io_sys_clk_p(sys_diff_clock_clk_p),
+ .io_sys_clk_n(sys_diff_clock_clk_n),
+ .io_sys_reset(reset),
+ //Misc outputs for system.v
+ .io_core_clock(top_clock),
+ .io_core_reset(top_reset)
+);
+
+ sdio_spi_bridge ip_sdio_spi
+ (
+ .clk(top_clock),
+ .reset(top_reset),
+ .sd_cmd(sdio_cmd),
+ .sd_dat(sdio_dat),
+ .sd_sck(sdio_clk),
+ .spi_sck(sd_spi_sck),
+ .spi_dq_o(sd_spi_dq_o),
+ .spi_dq_i(sd_spi_dq_i),
+ .spi_cs(sd_spi_cs)
+ );
+
+ //UART
+ assign uart_rtsn =1'b0;
+ always @(posedge top_clock) begin
+ if (top_reset) begin
+ uart_rx_sync <= 2'b11;
+ end else begin
+ uart_rx_sync[0] <= uart_rx;
+ uart_rx_sync[1] <= uart_rx_sync[0];
+ end
+ end
+
+ assign led[7:4] = 4'b0000;
+
+endmodule
+
+`default_nettype wire
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.everywhere.e300artydevkit
+
+import config._
+import coreplex._
+import rocketchip._
+
+
+class DefaultFreedomEConfig extends Config(
+ new WithStatelessBridge ++
+ new WithNBreakpoints(2) ++
+ new WithRV32 ++
+ new DefaultSmallConfig
+)
+
+class WithBootROMFile(bootROMFile: String) extends Config(
+ (pname, site, here) => pname match {
+ case BootROMFile => bootROMFile
+ case _ => throw new CDEMatchError
+ }
+)
+
+class E300ArtyDevKitConfig extends Config(
+ new WithBootROMFile("./bootrom/e300artydevkit.img") ++
+ new WithNExtTopInterrupts(0) ++
+ new WithJtagDTM ++
+ new WithL1ICacheSets(8192/32) ++ // 8 KiB **per set**
+ new WithCacheBlockBytes(32) ++
+ new WithL1ICacheWays(2) ++
+ new WithDefaultBtb ++
+ new WithFastMulDiv ++
+ new WithDataScratchpad(16384) ++
+ new WithNMemoryChannels(0) ++
+ new WithoutFPU ++
+ new WithTLMonitors ++
+ new DefaultFreedomEConfig
+)
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.everywhere.e300artydevkit
+
+import Chisel._
+import config._
+import diplomacy._
+import coreplex._
+import rocketchip._
+import uncore.devices.DebugBusIO
+import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule, GPIOPin, GPIOPinToIOF, GPIOPinIOFCtrl, GPIOInputPinCtrl, JTAGPinsIO, JTAGGPIOPort}
+import sifive.blocks.devices.mockaon.{MockAONConfig, PeripheryMockAON, PeripheryMockAONBundle, PeripheryMockAONModule, MockAONWrapperPadsIO}
+import sifive.blocks.devices.pwm.{PWMConfig, PeripheryPWM, PeripheryPWMBundle, PeripheryPWMModule, PWMGPIOPort}
+import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule, SPIFlashConfig, PeripherySPIFlash, PeripherySPIFlashBundle, PeripherySPIFlashModule, SPIPinsIO, SPIGPIOPort}
+import sifive.blocks.devices.uart.{UARTConfig, PeripheryUART, PeripheryUARTBundle, PeripheryUARTModule, UARTGPIOPort}
+import sifive.blocks.util.ResetCatchAndSync
+import util._
+
+// Coreplex and Periphery
+
+trait E300ArtyDevKitPeripheryConfigs {
+ val mockAONConfig = MockAONConfig(address = 0x10000000)
+ val gpioConfig = GPIOConfig(address = 0x10012000, width = 32)
+ val pwmConfigs = List(
+ PWMConfig(address = 0x10015000, cmpWidth = 8),
+ PWMConfig(address = 0x10025000, cmpWidth = 16),
+ PWMConfig(address = 0x10035000, cmpWidth = 16))
+ val spiConfigs = List(
+ SPIConfig(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
+ SPIConfig(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
+ val spiFlashConfig = SPIFlashConfig(
+ fAddress = 0x20000000, rAddress = 0x10014000, sampleDelay = 3)
+ val uartConfigs = List(
+ UARTConfig(address = 0x10013000),
+ UARTConfig(address = 0x10023000))
+}
+
+// This custom E300ArtyDevKit coreplex has no port into the L2 and no memory subsystem
+
+class E300ArtyDevKitCoreplex(implicit p: Parameters) extends BareCoreplex
+ with CoreplexNetwork
+ with CoreplexRISCVPlatform
+ with RocketTiles {
+ override lazy val module = new E300ArtyDevKitCoreplexModule(this, () => new E300ArtyDevKitCoreplexBundle(this))
+}
+
+class E300ArtyDevKitCoreplexBundle[+L <: E300ArtyDevKitCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
+ with CoreplexNetworkBundle
+ with CoreplexRISCVPlatformBundle
+ with RocketTilesBundle
+
+class E300ArtyDevKitCoreplexModule[+L <: E300ArtyDevKitCoreplex, +B <: E300ArtyDevKitCoreplexBundle[L]](_outer: L, _io: () => B)
+ extends BareCoreplexModule(_outer, _io)
+ with CoreplexNetworkModule
+ with CoreplexRISCVPlatformModule
+ with RocketTilesModule
+
+class E300ArtyDevKitSystem(implicit p: Parameters) extends BaseTop
+ with E300ArtyDevKitPeripheryConfigs
+ with PeripheryBootROM
+ with PeripheryDebug
+ with PeripheryMockAON
+ with PeripheryUART
+ with PeripherySPIFlash
+ with PeripherySPI
+ with PeripheryGPIO
+ with PeripheryPWM
+ with HardwiredResetVector {
+ override lazy val module = new E300ArtyDevKitSystemModule(this, () => new E300ArtyDevKitSystemBundle(this))
+
+ val coreplex = LazyModule(new E300ArtyDevKitCoreplex)
+ socBus.node := coreplex.mmio
+ coreplex.mmioInt := intBus.intnode
+}
+
+class E300ArtyDevKitSystemBundle[+L <: E300ArtyDevKitSystem](_outer: L) extends BaseTopBundle(_outer)
+ with E300ArtyDevKitPeripheryConfigs
+ with PeripheryBootROMBundle
+ with PeripheryDebugBundle
+ with PeripheryUARTBundle
+ with PeripherySPIBundle
+ with PeripheryGPIOBundle
+ with PeripherySPIFlashBundle
+ with PeripheryMockAONBundle
+ with PeripheryPWMBundle
+ with HardwiredResetVectorBundle
+
+class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem, +B <: E300ArtyDevKitSystemBundle[L]](_outer: L, _io: () => B)
+ extends BaseTopModule(_outer, _io)
+ with E300ArtyDevKitPeripheryConfigs
+ with PeripheryBootROMModule
+ with PeripheryDebugModule
+ with PeripheryUARTModule
+ with PeripherySPIModule
+ with PeripheryGPIOModule
+ with PeripherySPIFlashModule
+ with PeripheryMockAONModule
+ with PeripheryPWMModule
+ with HardwiredResetVectorModule
+
+// Top
+
+class E300ArtyDevKitTopIO(implicit val p: Parameters) extends Bundle with E300ArtyDevKitPeripheryConfigs {
+ val pads = new Bundle {
+ val jtag = new JTAGPinsIO
+ val gpio = Vec(gpioConfig.width, new GPIOPin)
+ val qspi = new SPIPinsIO(spiFlashConfig)
+ val aon = new MockAONWrapperPadsIO()
+ }
+}
+
+class E300ArtyDevKitTop(implicit val p: Parameters) extends Module with E300ArtyDevKitPeripheryConfigs {
+ val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
+ val io = new E300ArtyDevKitTopIO
+
+ // This needs to be de-asserted synchronously to the coreClk.
+ val async_corerst = sys.io.aon.rsts.corerst
+ sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
+
+ // ------------------------------------------------------------
+ // Check for unsupported RCT Connections
+ // ------------------------------------------------------------
+
+ require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
+
+ // ------------------------------------------------------------
+ // Build GPIO Pin Mux
+ // ------------------------------------------------------------
+
+ // Pin Mux for UART, SPI, PWM
+ // First convert the System outputs into "IOF" using the respective *GPIOPort
+ // converters.
+ val sys_uarts = sys.io.uarts
+ val sys_pwms = sys.io.pwms
+ val sys_spis = sys.io.spis
+
+ val uart_pins = uartConfigs.map { c => Module (new UARTGPIOPort) }
+ val pwm_pins = pwmConfigs.map { c => Module (new PWMGPIOPort(c.bc)) }
+ val spi_pins = spiConfigs.map { c => Module (new SPIGPIOPort(c)) }
+
+ (uart_pins zip sys_uarts) map {case (p, r) => p.io.uart <> r}
+ (pwm_pins zip sys_pwms) map {case (p, r) => p.io.pwm <> r}
+ (spi_pins zip sys_spis) map {case (p, r) => p.io.spi <> r}
+
+ // ------------------------------------------------------------
+ // Default Pin connections before attaching pinmux
+
+ for (iof_0 <- sys.io.gpio.iof_0) {
+ iof_0.o := GPIOPinIOFCtrl()
+ }
+
+ for (iof_1 <- sys.io.gpio.iof_1) {
+ iof_1.o := GPIOPinIOFCtrl()
+ }
+
+ // ------------------------------------------------------------
+ // TODO: Make this mapping more programmatic.
+
+ val iof_0 = sys.io.gpio.iof_0
+ val iof_1 = sys.io.gpio.iof_1
+
+ // SPI1 (0 is the dedicated)
+ GPIOPinToIOF(spi_pins(0).io.pins.cs(0), iof_0(2))
+ GPIOPinToIOF(spi_pins(0).io.pins.dq(0), iof_0(3))
+ GPIOPinToIOF(spi_pins(0).io.pins.dq(1), iof_0(4))
+ GPIOPinToIOF(spi_pins(0).io.pins.sck, iof_0(5))
+ GPIOPinToIOF(spi_pins(0).io.pins.dq(2), iof_0(6))
+ GPIOPinToIOF(spi_pins(0).io.pins.dq(3), iof_0(7))
+ GPIOPinToIOF(spi_pins(0).io.pins.cs(1), iof_0(8))
+ GPIOPinToIOF(spi_pins(0).io.pins.cs(2), iof_0(9))
+ GPIOPinToIOF(spi_pins(0).io.pins.cs(3), iof_0(10))
+
+ // SPI2
+ GPIOPinToIOF(spi_pins(1).io.pins.cs(0), iof_0(26))
+ GPIOPinToIOF(spi_pins(1).io.pins.dq(0), iof_0(27))
+ GPIOPinToIOF(spi_pins(1).io.pins.dq(1), iof_0(28))
+ GPIOPinToIOF(spi_pins(1).io.pins.sck, iof_0(29))
+ GPIOPinToIOF(spi_pins(1).io.pins.dq(2), iof_0(30))
+ GPIOPinToIOF(spi_pins(1).io.pins.dq(3), iof_0(31))
+
+ // UART0
+ GPIOPinToIOF(uart_pins(0).io.pins.rxd, iof_0(16))
+ GPIOPinToIOF(uart_pins(0).io.pins.txd, iof_0(17))
+
+ // UART1
+ GPIOPinToIOF(uart_pins(1).io.pins.rxd, iof_0(24))
+ GPIOPinToIOF(uart_pins(1).io.pins.txd, iof_0(25))
+
+ //PWM
+ GPIOPinToIOF(pwm_pins(0).io.pins.pwm(0), iof_1(0) )
+ GPIOPinToIOF(pwm_pins(0).io.pins.pwm(1), iof_1(1) )
+ GPIOPinToIOF(pwm_pins(0).io.pins.pwm(2), iof_1(2) )
+ GPIOPinToIOF(pwm_pins(0).io.pins.pwm(3), iof_1(3) )
+
+ GPIOPinToIOF(pwm_pins(1).io.pins.pwm(1), iof_1(19))
+ GPIOPinToIOF(pwm_pins(1).io.pins.pwm(0), iof_1(20))
+ GPIOPinToIOF(pwm_pins(1).io.pins.pwm(2), iof_1(21))
+ GPIOPinToIOF(pwm_pins(1).io.pins.pwm(3), iof_1(22))
+
+ GPIOPinToIOF(pwm_pins(2).io.pins.pwm(0), iof_1(10))
+ GPIOPinToIOF(pwm_pins(2).io.pins.pwm(1), iof_1(11))
+ GPIOPinToIOF(pwm_pins(2).io.pins.pwm(2), iof_1(12))
+ GPIOPinToIOF(pwm_pins(2).io.pins.pwm(3), iof_1(13))
+
+ // ------------------------------------------------------------
+ // Drive actual Pads
+ // ------------------------------------------------------------
+
+ // Result of Pin Mux
+ io.pads.gpio <> sys.io.gpio.pins
+
+ val dedicated_spi_pins = Module (new SPIGPIOPort(spiFlashConfig, syncStages=3, driveStrength=Bool(true)))
+ dedicated_spi_pins.clock := sys.clock
+ dedicated_spi_pins.reset := sys.reset
+ io.pads.qspi <> dedicated_spi_pins.io.pins
+ dedicated_spi_pins.io.spi <> sys.io.qspi
+
+ // JTAG Debug Interface
+
+ val jtag_pins = Module (new JTAGGPIOPort(true))
+ io.pads.jtag <> jtag_pins.io.pins
+ sys.io.jtag.get <> jtag_pins.io.jtag
+ // Override TRST to reset this logic IFF the core is in reset.
+ // This will require 3 ticks of TCK before the debug logic
+ // comes out of reset, but JTAG needs 5 ticks anyway.
+ // This means that the "real" TRST is never actually used in this design.
+ sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, async_corerst)
+
+ // AON Pads
+ io.pads.aon <> sys.io.aon.pads
+}
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500vc707devkit
+
+import config._
+import coreplex.{WithL1DCacheWays, WithSmallCores, WithoutFPU, BootROMFile}
+import rocketchip.{BaseConfig,WithRTCPeriod,WithJtagDTM}
+
+// Don't use directly. Requires additional bootfile configuration
+class DefaultFreedomUConfig extends Config(
+ new WithJtagDTM ++ new BaseConfig
+)
+
+class WithBootROMFile(bootROMFile: String) extends Config(
+ (pname, site, here) => pname match {
+ case BootROMFile => bootROMFile
+ case _ => throw new CDEMatchError
+ }
+)
+
+//----------------------------------------------------------------------------------
+// Freedom U500 VC707 Dev Kit
+
+class U500VC707DevKitConfig extends Config(
+ new WithBootROMFile("./bootrom/u500vc707devkit.img") ++
+ new WithRTCPeriod(62) ++ //Default value of 100 generates 1 Mhz clock @ 100Mhz, then corrected in sbi_entry.c
+ //Value 62 generates ~ 1Mhz clock @ 62.5Mhz
+ new WithoutFPU ++
+ new DefaultFreedomUConfig)
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500vc707devkit
+
+import Chisel._
+import config._
+import util._
+import junctions._
+import diplomacy._
+import uncore.tilelink._
+import uncore.devices._
+import uncore.util._
+import uncore.converters._
+import rocket._
+import coreplex._
+import rocketchip._
+
+import sifive.blocks.devices.xilinxvc707mig._
+import sifive.blocks.devices.xilinxvc707pciex1._
+import sifive.blocks.devices.gpio.{GPIOConfig, PeripheryGPIO, PeripheryGPIOBundle, PeripheryGPIOModule}
+import sifive.blocks.devices.spi.{SPIConfig, PeripherySPI, PeripherySPIBundle, PeripherySPIModule}
+import sifive.blocks.devices.uart._
+import sifive.blocks.util.ResetCatchAndSync
+
+trait PeripheryConfigs {
+ val uartConfigs = List(UARTConfig(address = BigInt(0x54000000L)))
+ val spiConfigs = List(SPIConfig(rAddress = BigInt(0x54001000L)))
+ val gpioConfig = GPIOConfig(address = BigInt(0x54002000L), width = 4)
+}
+
+class U500VC707DevKitSystem(implicit p: Parameters) extends BaseTop
+ with PeripheryConfigs
+ with PeripheryBootROM
+ with PeripheryDebug
+ with PeripheryCounter
+ with PeripheryUART
+ with PeripherySPI
+ with PeripheryGPIO
+ with PeripheryXilinxVC707MIG
+ with PeripheryXilinxVC707PCIeX1
+ with HardwiredResetVector
+ with RocketPlexMaster {
+ override lazy val module = new U500VC707DevKitSystemModule(this, () => new U500VC707DevKitSystemBundle(this))
+
+ // scalastyle:off method.length
+ ConfigStringOutput.contents = Some {
+ """platform {
+ | vendor ucb;
+ | arch spike;
+ |};
+ |plic {
+ | interface "plic";
+ | ndevs 9;
+ | priority { mem { 0x0c000000 0x0c00ffff; }; };
+ | pending { mem { 0x0c001000 0x0c00107f; }; };
+ | 0 {
+ | 0 {
+ | m {
+ | ie { mem { 0x0c002000 0x0c00207f; }; };
+ | ctl { mem { 0x0c200000 0x0c200007; }; };
+ | };
+ | s {
+ | ie { mem { 0x0c002080 0x0c0020ff; }; };
+ | ctl { mem { 0x0c201000 0x0c201007; }; };
+ | };
+ | };
+ | };
+ |};
+ |pcie {
+ | interface "xilinx-pcie-rv";
+ | bus {
+ | mem { 0x60000000 0x7fffffff; } { 0x200000000 0x3ffffffff; };
+ | bus { 1 63; };
+ | };
+ | bridge {
+ | mem { 0x50000000 0x53ffffff; };
+ | bus 0;
+ | irq 6;
+ | };
+ |};
+ |leds {
+ | interface "gpio";
+ | ngpio 4;
+ | mem { 0x54002000 0x54002003; };
+ |};
+ |rtc {
+ | addr 0x200bff8;
+ |};
+ |ram {
+ | 0 {
+ | addr 0x80000000;
+ | size 0x10000000;
+ | };
+ |};
+ |uart {
+ | addr 0x54000000;
+ |};
+ |core {
+ | 0 {
+ | 0 {
+ | isa rv64ima;
+ | timecmp 0x02004000;
+ | ipi 0x02000000;
+ | };
+ | };
+ |};
+ |\u0000""".stripMargin
+ }
+ // scalastyle:on method.length
+}
+
+class U500VC707DevKitSystemBundle[+L <: U500VC707DevKitSystem](_outer: L) extends BaseTopBundle(_outer)
+ with PeripheryConfigs
+ with PeripheryBootROMBundle
+ with PeripheryDebugBundle
+ with PeripheryCounterBundle
+ with PeripheryUARTBundle
+ with PeripherySPIBundle
+ with PeripheryGPIOBundle
+ with PeripheryXilinxVC707MIGBundle
+ with PeripheryXilinxVC707PCIeX1Bundle
+ with HardwiredResetVectorBundle
+ with RocketPlexMasterBundle
+
+class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem, +B <: U500VC707DevKitSystemBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
+ with PeripheryConfigs
+ with PeripheryBootROMModule
+ with PeripheryDebugModule
+ with PeripheryCounterModule
+ with PeripheryUARTModule
+ with PeripherySPIModule
+ with PeripheryGPIOModule
+ with PeripheryXilinxVC707MIGModule
+ with PeripheryXilinxVC707PCIeX1Module
+ with HardwiredResetVectorModule
+ with RocketPlexMasterModule
+
+/////
+
+class ResetDone extends Module {
+ //unused - in future io.resetdone can set rocketchip STOP_COND/PRINTF_COND
+ val io = new Bundle{
+ val reset = Bool(INPUT)
+ val resetdone = Bool(OUTPUT)
+ }
+ val resetdonereg = Reg(init = Bool(false))
+ val resetff = Reg(init = Bool(false))
+ resetff := io.reset;
+ resetdonereg := Mux( ((!io.reset)&&resetff), UInt("b1"), resetdonereg)
+ io.resetdone := resetdonereg
+}
+
+/////
+
+class U500VC707DevKitIO(implicit val p: Parameters) extends Bundle
+ with PeripheryConfigs
+ with PeripheryUARTBundle
+ with PeripherySPIBundle
+ with PeripheryGPIOBundle
+{
+ val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO()(p).flip)
+ val jtag = p(IncludeJtagDTM).option(new JTAGIO(true).flip)
+ //MIG
+ val xilinxvc707mig = new XilinxVC707MIGPads
+ //PCIe
+ val xilinxvc707pcie = new XilinxVC707PCIeX1Pads
+ //Clocks
+ val sys_clk_n = Bool(INPUT)
+ val sys_clk_p = Bool(INPUT)
+ val pcie_refclk_p = Bool(INPUT)
+ val pcie_refclk_n = Bool(INPUT)
+ //Reset
+ val sys_reset = Bool(INPUT)
+ //Misc outputs used in system.v
+ val core_reset = Bool(OUTPUT)
+ val core_clock = Clock(OUTPUT)
+}
+
+/////
+
+class U500VC707DevKitTop(implicit val p: Parameters) extends Module {
+
+ // ------------------------------------------------------------
+ // Instantiate U500 VC707 Dev Kit system (sys)
+ // ------------------------------------------------------------
+ val sys = Module(LazyModule(new U500VC707DevKitSystem).module)
+ val io = new U500VC707DevKitIO
+
+ // ------------------------------------------------------------
+ // Clock and Reset
+ // ------------------------------------------------------------
+ val mig_mmcm_locked = Wire(Bool())
+ val mig_sys_reset = Wire(Bool())
+ val init_calib_complete = Wire(Bool())
+ val mmcm_lock_pcie = Wire(Bool())
+ val do_reset = Wire(Bool())
+ val mig_clock = Wire(Clock())
+ val mig_resetn = Wire(Bool())
+ val top_resetn = Wire(Bool())
+ val pcie_dat_reset = Wire(Bool())
+ val pcie_dat_resetn = Wire(Bool())
+ val pcie_cfg_reset = Wire(Bool())
+ val pcie_cfg_resetn = Wire(Bool())
+ val pcie_dat_clock = Wire(Clock())
+ val pcie_cfg_clock = Wire(Clock())
+ val top_clock = Wire(Clock())
+ val top_reset = Wire(Bool())
+ val mig_reset = Wire(Bool())
+
+ do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
+ mig_resetn := !mig_reset
+ top_resetn := !top_reset
+ pcie_dat_resetn := !pcie_dat_reset
+ pcie_cfg_resetn := !pcie_cfg_reset
+ // For now, run the CPU synchronous to the PCIe data bus
+ top_clock := pcie_dat_clock
+ val safe_reset = Module(new vc707reset)
+ safe_reset.io.areset := do_reset
+ safe_reset.io.clock1 := mig_clock
+ mig_reset := safe_reset.io.reset1
+ safe_reset.io.clock2 := pcie_dat_clock
+ pcie_dat_reset := safe_reset.io.reset2
+ safe_reset.io.clock3 := pcie_cfg_clock
+ pcie_cfg_reset := safe_reset.io.reset3
+ safe_reset.io.clock4 := top_clock
+ top_reset := safe_reset.io.reset4
+
+ sys.clock := top_clock
+ sys.reset := top_reset
+
+ // ------------------------------------------------------------
+ // UART
+ // ------------------------------------------------------------
+ io.uarts <> sys.io.uarts
+
+ // ------------------------------------------------------------
+ // SPI
+ // ------------------------------------------------------------
+ io.spis <> sys.io.spis
+
+ // ------------------------------------------------------------
+ // GPIO
+ // ------------------------------------------------------------
+ io.gpio <> sys.io.gpio
+
+ // ------------------------------------------------------------
+ // MIG
+ // ------------------------------------------------------------
+ sys.io.xilinxvc707mig.sys_clk_p := io.sys_clk_p
+ sys.io.xilinxvc707mig.sys_clk_n := io.sys_clk_n
+ mig_clock := sys.io.xilinxvc707mig.ui_clk
+ mig_sys_reset := sys.io.xilinxvc707mig.ui_clk_sync_rst
+ mig_mmcm_locked := sys.io.xilinxvc707mig.mmcm_locked
+ sys.io.xilinxvc707mig.aresetn := mig_resetn
+ init_calib_complete := sys.io.xilinxvc707mig.init_calib_complete
+ sys.io.xilinxvc707mig.sys_rst := io.sys_reset
+ //the below bundle assignment is dangerous and relies on matching signal names
+ // io.xilinxvc707 is of type XilinxVC707MIGPads
+ // sys.io.xilinxvc707mig is of type XilinxVC707MIGIO
+ io.xilinxvc707mig <> sys.io.xilinxvc707mig
+
+ // ------------------------------------------------------------
+ // PCIe
+ // ------------------------------------------------------------
+ sys.io.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
+ pcie_dat_clock := sys.io.xilinxvc707pcie.axi_aclk_out
+ pcie_cfg_clock := sys.io.xilinxvc707pcie.axi_ctl_aclk_out
+ mmcm_lock_pcie := sys.io.xilinxvc707pcie.mmcm_lock
+ sys.io.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
+ sys.io.xilinxvc707pcie.REFCLK_rxp := io.pcie_refclk_p
+ sys.io.xilinxvc707pcie.REFCLK_rxn := io.pcie_refclk_n
+ //another dangerous bundle assignment which relies on matching signal names
+ // io.xilinxvc707pcie is of type XilinxVC707PCIeX1Pads
+ // sys.io.xilinxvc707pcie is of type XilinxVC707PCIeX1IO
+ io.xilinxvc707pcie <> sys.io.xilinxvc707pcie
+
+ // ------------------------------------------------------------
+ // Debug
+ // ------------------------------------------------------------
+ if (p(IncludeJtagDTM)) {
+ sys.io.jtag.get <> io.jtag.get
+ //Override TRST to reset this logic IFF the core is in reset.
+ // This will require 3 ticks of TCK before the debug logic
+ // comes out of reset, but JTAG needs 5 ticks anyway.
+ // This means that the "real" TRST is never actually used.
+ sys.io.jtag.get.TRST := ResetCatchAndSync(sys.io.jtag.get.TCK, top_reset)
+ }else{
+ // SimDTM; only for simulation use
+ sys.io.debug.get := io.debug.get
+ // test_mode_clk shouldn't be used for simulation
+ //sys.io.test_mode_clk := Bool(false).asClock
+ }
+
+ // ------------------------------------------------------------
+ // Misc outputs used in system.v
+ // ------------------------------------------------------------
+ io.core_clock := top_clock
+ io.core_reset := top_reset
+
+}
--- /dev/null
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500vc707devkit
+
+import Chisel._
+
+//scalastyle:off
+//turn off linter: blackbox name must match verilog module
+class vc707reset() extends BlackBox
+{
+ val io = new Bundle{
+ val areset = Bool(INPUT)
+ val clock1 = Clock(INPUT)
+ val reset1 = Bool(OUTPUT)
+ val clock2 = Clock(INPUT)
+ val reset2 = Bool(OUTPUT)
+ val clock3 = Clock(INPUT)
+ val reset3 = Bool(OUTPUT)
+ val clock4 = Clock(INPUT)
+ val reset4 = Bool(OUTPUT)
+ }
+}
+//scalastyle:on
projects / freedom-sifive.git / commitdiff