Increase dual-core RV64 timeouts.
authorTim Newsome <tim@sifive.com>
Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)
committerTim Newsome <tim@sifive.com>
Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)
I need this for CompareSections to pass when I instrument spike to be
really slow.

debug/targets/RISC-V/spike64-2-rtos.py
debug/targets/RISC-V/spike64-2.py

index d65d2abb24f80fd41b38051e8551a620574f9ce2..7e3fc7e2748b5a8ddeb1d75b63ac14a0e24b8260 100644 (file)
@@ -6,7 +6,7 @@ import spike64  # pylint: disable=import-error
 class spike64_2_rtos(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-rtos.cfg"
-    timeout_sec = 30
+    timeout_sec = 60
 
     def create(self):
         return testlib.Spike(self)
index 709ebbeabef93cae0ce6cb5a85f5ff946c1a18a1..79aab3e696721e4b59265fbd868a8f2a6c9e545c 100644 (file)
@@ -6,7 +6,7 @@ import spike64  # pylint: disable=import-error
 class spike64_2(targets.Target):
     harts = [spike64.spike64_hart(), spike64.spike64_hart()]
     openocd_config_path = "spike-2.cfg"
-    timeout_sec = 30
+    timeout_sec = 60
 
     def create(self):
         return testlib.Spike(self)