whoops, fake pll/mem need vss/vdd

diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py
index 56163ae98ec24f7bc4348cdd27d120b469e24f1b..03a6cccb2cc409ea891ffc8c1226988aa645ba0b 100644 (file)
--- a/experiments10_verilog/pll.py
+++ b/experiments10_verilog/pll.py
@@ -224,7 +224,11 @@ def _load():
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
             'out_v': Net.create(cell, 'out_v'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vdd'].setGlobal(True)
+        nets['vss'].setGlobal(True)
 
         # set net directions
         nets['ref_v'].setDirection( Net.Direction.IN )

diff --git a/experiments9/LibreSOCMem.py b/experiments9/LibreSOCMem.py
index 8489df4d4cad4d0a250926107683a90cd5e78a4a..4c4753daf8104e93c0aafc9cb934680de6a9c52d 100644 (file)
--- a/experiments9/LibreSOCMem.py
+++ b/experiments9/LibreSOCMem.py
@@ -219,9 +219,11 @@ def _load():
         nets = {
             '*': Net.create(cell, '*'),
             'clk': Net.create(cell, 'clk'),
-            #'vdd': Net.create(cell, 'vdd'),
-            #'vss': Net.create(cell, 'vss'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vss'].setGlobal(True)
+        nets['vdd'].setGlobal(True)
         for name, qty in (('a', 9),
                           ('d', 64),
                           ('q', 64),

diff --git a/experiments9/pll.py b/experiments9/pll.py
index 56163ae98ec24f7bc4348cdd27d120b469e24f1b..03a6cccb2cc409ea891ffc8c1226988aa645ba0b 100644 (file)
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -224,7 +224,11 @@ def _load():
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
             'out_v': Net.create(cell, 'out_v'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vdd'].setGlobal(True)
+        nets['vss'].setGlobal(True)
 
         # set net directions
         nets['ref_v'].setDirection( Net.Direction.IN )