Sorta kinda working bl and blr - need to properly implement lr
authorMichael Nolan <mtnolan2640@gmail.com>
Wed, 6 May 2020 14:32:24 +0000 (10:32 -0400)
committerMichael Nolan <mtnolan2640@gmail.com>
Wed, 6 May 2020 14:32:24 +0000 (10:32 -0400)
src/soc/decoder/isa/caller.py
src/soc/decoder/isa/test_caller.py
src/soc/decoder/selectable_int.py

index 03503330a3b2a50e9a35aad27c038be4d84195ad..48377dc0c9ba5ed8777e46fc3d8aff1052ac6ec9 100644 (file)
@@ -161,7 +161,9 @@ class ISACaller:
                           'CIA': self.pc.CIA,
                           'CR': self.cr,
                           'LR': self.undefined,
+                          'CTR': self.undefined,
                           'undefined': self.undefined,
+                          'mode_is_64bit': True,
                           }
 
         # field-selectable versions of Condition Register TODO check bitranges?
index 5d4869fab207aa18cd819512bb49b4168ce9286c..c693f86e5694b0b4dd0c8935cdb198ce91cc12be 100644 (file)
@@ -106,6 +106,16 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
             self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
 
+    def test_branch_link(self):
+        lst = ["bl 0xc",
+               "addi 2, 1, 0x1234",
+               "ba 0x1000",
+               "addi 1, 0, 0x1234",
+               "bclr 20, 0, 0"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+
+
     @unittest.skip("broken")  # FIXME
     def test_mtcrf(self):
         for i in range(4):
index c4698c014c3df71382f2c539c940f6fcc47c11d7..239162f3e046bdbe04db279e63a69a28eb9568e2 100644 (file)
@@ -44,10 +44,14 @@ class FieldSelectableInt:
 
     def __getitem__(self, key):
         print ("getitem", key, self.br)
+        if isinstance(key, SelectableInt):
+            key = key.value
         key = self.br[key] # don't do POWER 1.3.4 bit-inversion
         return self.si[key]
 
     def __setitem__(self, key, value):
+        if isinstance(key, SelectableInt):
+            key = key.value
         key = self.br[key] # don't do POWER 1.3.4 bit-inversion
         return self.si.__setitem__(key, value)