--- /dev/null
+© IBM Corp. 2019
+This softcore is licensed under and subject to the terms of the CC-BY 4.0
+license (https://creativecommons.org/licenses/by/4.0/legalcode).
+Additional rights, including the right to physically implement a softcore
+that is compliant with the required sections of the Power ISA
+Specification, will be available at no cost via the OpenPOWER Foundation.
+This README will be updated with additional information when OpenPOWER's
+license is available.
+// Copyright (C) IBM 2019, see LICENSE.CC4
+// based on code from microwatt https://github.com/antonblanchard/microwatt
+
#include <stdlib.h>
#include "Vtop.h"
#include "verilated.h"
+// Copyright (C) IBM 2019, see LICENSE.CC4
+// based on code from microwatt https://github.com/antonblanchard/microwatt
+
#include <signal.h>
#include <poll.h>
#include <unistd.h>
+// Copyright (C) IBM 2019, see LICENSE.CC4
+// based on code from microwatt https://github.com/antonblanchard/microwatt
+
/*
* Our UART uses 16x oversampling, so at 50 MHz and 115200 baud
* each sample is: 50000000/(115200*16) = 27 clock cycles. This