adding immediates, tracking down a bug

diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py
index 2fe8c408ae284bd78511270db08f9638b8f31a2c..2e7602ca71413849ede31d4ad50d0c8f8690ab3d 100644 (file)
--- a/src/soc/experiment/score6600.py
+++ b/src/soc/experiment/score6600.py
@@ -1104,13 +1104,16 @@ def scoreboard_sim(dut, alusim):
             instrs.append((7, 6, 6, 2, 0, 0, (0, 0)))
             instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
 
-        if True:
+        if False:
             instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
                            0, 0, (0, 0)))
             instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
                            0, 0, (0, 0)))
         if True:
             instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+                           1, 7, (0, 0)))
+        if False:
+            instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
                            0, 0, (0, 0)))
 
         if False:
@@ -1232,8 +1235,9 @@ def scoreboard_sim(dut, alusim):
 
 
 def test_scoreboard():
-    dut = IssueToScoreboard(2, 1, 1, 16, 8, 8)
-    alusim = RegSim(16, 8)
+    regwidth = 64
+    dut = IssueToScoreboard(2, 1, 1, regwidth, 8, 8)
+    alusim = RegSim(regwidth, 8)
     memsim = MemSim(16, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard6600.il", "w") as f:

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index 66b37ee878b424ebccb23029ca0afed1fe788a8a..a96f90a8f9753dde7d60fc07707afef40a740562 100644 (file)
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -46,6 +46,7 @@ class RegSim:
             val = src1 + src2
         elif op == InternalOp.OP_MUL_L64:
             val = src1 * src2
+            print ("mul src1, src2", src1, src2, val)
         elif op == ISUB:
             val = src1 - src2
         elif op == ISHF: