Fix test_bc_reg

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 03c65118efd401b5ba6807413c668b84da29aa68..f145a63254cf9918a94955d812b6b5337a2e57fe 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -58,6 +58,7 @@ class BranchMainStage(PipeModBase):
         op = self.i.ctx.op
         lk = op.lk # see PowerDecode2 as to why this is done
         cr, cia, ctr, spr1 = self.i.cr, self.i.cia, self.i.ctr, self.i.spr1
+        spr2 = self.i.spr2
         nia_o, lr_o, ctr_o = self.o.nia, self.o.lr, self.o.ctr
 
         # obtain relevant instruction field AA, "Absolute Address" mode
@@ -133,7 +134,7 @@ class BranchMainStage(PipeModBase):
                 comb += ctr_o.ok.eq(ctr_write)
             #### branch conditional reg ####
             with m.Case(InternalOp.OP_BCREG):
-                comb += br_imm_addr.eq(spr1) # SPR1 is set by decode unit
+                comb += br_imm_addr.eq(Cat(Const(0, 2), spr2[2:]))
                 comb += br_taken.eq(bc_taken)
                 comb += ctr_o.ok.eq(ctr_write)
 

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 66020211592b0b61ef7734c02f64eced6ea0fd6c..0028fb4146a6122c8c90e250dc24cc5d06d3adb0 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -10,6 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
+from soc.regfile.regfiles import FastRegs
 
 from soc.fu.branch.pipeline import BranchBasePipe
 from soc.fu.branch.pipe_data import BranchPipeSpec
@@ -98,12 +99,11 @@ class BranchTestCase(FHDLTestCase):
 
     def test_bc_reg(self):
         # XXX: bcctr and bcctrl time out (irony: they're counters)
-        #choices = ["bclr", "bclrl", "bctar", "bctarl", "bcctr", "bcctrl"]
-        choices = ["bclr", "bclrl", "bctar", "bctarl", ]
+        choices = ["bclr", "bclrl", "bcctr", "bcctrl"]
         for insn in choices:
             for i in range(20):
                 bh = random.randrange(0, 3)
-                bo = random.choice([0, 2, 8, 10, 16, 18])
+                bo = random.choice([4, 12])
                 bi = random.randrange(0, 31)
                 cr = random.randrange(0, (1<<32)-1)
                 ctr = random.randint(0, (1<<32)-1)
@@ -113,6 +113,8 @@ class BranchTestCase(FHDLTestCase):
                                      initial_sprs=initial_sprs,
                                      initial_cr=cr)
 
+        
+
     def test_ilang(self):
         pspec = BranchPipeSpec(id_wid=2)
         alu = BranchBasePipe(pspec)
@@ -174,17 +176,8 @@ class TestRunner(FHDLTestCase):
                     # set to TAR, op_bclr* require spr2 to be set to LR.
                     # if op_sc*, op_rf* and op_hrfid are to be added here
                     # then additional op-decoding is required, accordingly
-                    yield branch.p.data_i.spr1.eq(simulator.spr['CTR'].value)
-                    print(f"cr0: {simulator.crl[0].get_range()}")
                     yield Settle()
-
-                    cr_en = yield pdecode2.e.read_cr1.ok
-                    if cr_en:
-                        cr_sel = yield pdecode2.e.read_cr1.data
-                        cr = simulator.crl[cr_sel].get_range().value
-                        yield branch.p.data_i.cr.eq(cr)
-                        full_cr = simulator.cr.get_range().value
-                        print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+                    yield from self.set_inputs(branch, pdecode2, simulator)
                     fn_unit = yield pdecode2.e.fn_unit
                     self.assertEqual(fn_unit, Function.BRANCH.value, code)
                     yield
@@ -208,6 +201,7 @@ class TestRunner(FHDLTestCase):
         self.assertEqual(branch_taken, sim_branch_taken, code)
         if branch_taken:
             branch_addr = yield branch.n.data_o.nia.data
+            print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}")
             self.assertEqual(branch_addr, sim.pc.CIA.value, code)
 
         lk = yield dec2.e.lk
@@ -217,6 +211,27 @@ class TestRunner(FHDLTestCase):
             branch_lr = yield branch.n.data_o.lr.data
             self.assertEqual(sim.spr['LR'], branch_lr, code)
 
+    def set_inputs(self, branch, dec2, sim):
+        yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
+        print(f"cr0: {sim.crl[0].get_range()}")
+
+        spr2_en = yield dec2.e.read_spr2.ok
+        if spr2_en:
+            spr2_sel = yield dec2.e.read_spr2.data
+            if spr2_sel == FastRegs.LR:
+                spr2_data = sim.spr['LR'].value
+            elif spr2_sel == FastRegs.CTR:
+                spr2_data = sim.spr['CTR'].value
+            yield branch.p.data_i.spr2.eq(spr2_data)
+
+        cr_en = yield dec2.e.read_cr1.ok
+        if cr_en:
+            cr_sel = yield dec2.e.read_cr1.data
+            cr = sim.crl[cr_sel].get_range().value
+            yield branch.p.data_i.cr.eq(cr)
+            full_cr = sim.cr.get_range().value
+            print(f"full cr: {full_cr:x}, sel: {cr_sel}, cr: {cr:x}")
+
 
 if __name__ == "__main__":
     unittest.main(exit=False)

diff --git a/src/soc/simulator/program.py b/src/soc/simulator/program.py
index 59590a0965c46819847bc072bb4f4417f3e1c1ad..cd515a8d0ebd175094913ad2ce1c47a3c481a399 100644 (file)
--- a/src/soc/simulator/program.py
+++ b/src/soc/simulator/program.py
@@ -8,6 +8,7 @@ import tempfile
 import subprocess
 import struct
 import os
+import sys
 
 filedir = os.path.dirname(os.path.realpath(__file__))
 memmap = os.path.join(filedir, "memmap")
@@ -57,7 +58,10 @@ class Program:
                     outfile.name]
             p = subprocess.Popen(args, stdin=subprocess.PIPE)
             p.communicate(self.assembly.encode('utf-8'))
-            assert(p.wait() == 0)
+            if p.wait() != 0:
+                print("Error in program:")
+                print(self.assembly)
+                sys.exit(1)
             self._link(outfile)
 
     def generate_instructions(self):