fix a series of random imports

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 2a10ed151071085ae9533912c34ea5a83aed91e7..72de48749c042eafc9f4f0b9b3bbfaa96e3d9893 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -17,7 +17,7 @@ from nmigen.compat.sim import run_simulation
 
 from soc.decoder.power_enums import InternalOp, Function, CryIn
 
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 
 import operator
 

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index f9cb83ea13184bb6ff9ceedb7627b7ea67295c55..0a9541a7d59086b25059905d2abab9738510f569 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -7,7 +7,7 @@ from nmutil.latch import SRLatch, latchregister
 from soc.decoder.power_decoder2 import Data
 from soc.decoder.power_enums import InternalOp
 
-from alu_hier import CompALUOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 
 """ Computation Unit (aka "ALU Manager").
 

diff --git a/src/soc/scoreboard/test_mem_fu_matrix.py b/src/soc/scoreboard/test_mem_fu_matrix.py
index b85ce898addd51fedaace38f04962e96421dc12b..12dba0ccdd8ef74e229d8dfa39a7c258ea1e7082 100644 (file)
--- a/src/soc/scoreboard/test_mem_fu_matrix.py
+++ b/src/soc/scoreboard/test_mem_fu_matrix.py
@@ -21,7 +21,9 @@ from math import log
 import unittest
 
 # FIXME: fixed up imports
-from ..experiment.score6600 import IssueToScoreboard, RegSim, instr_q, wait_for_busy_clear, wait_for_issue, CompUnitALUs, CompUnitBR
+from soc.experiment.score6600 import (IssueToScoreboard, RegSim, instr_q,
+                                      wait_for_busy_clear, wait_for_issue,
+                                      CompUnitALUs, CompUnitBR)
 
 
 class Memory(Elaboratable):