remove move unneeded signals from test_issuer.il

diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il
index 86f1d3a5123f290fa031cdd65ebb05c8d2c325e5..4bfeab1516cb073c9505d582dbb3c7b4459d652a 100644 (file)
--- a/experiments9/non_generated/test_issuer.il
+++ b/experiments9/non_generated/test_issuer.il
@@ -115680,50 +115680,32 @@ module \lsmem
   wire width 1 output 11 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 \dbus__cyc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 12 \x_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 13 \dbus__ack
+  wire width 1 input 12 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 14 \dbus__err
+  wire width 1 input 13 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 15 \dbus__stb
+  wire width 1 output 14 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 \dbus__stb$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 16 \dbus__dat_r
+  wire width 64 input 15 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 17 \dbus__adr
+  wire width 45 output 16 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 45 \dbus__adr$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 18 \dbus__sel
+  wire width 8 output 17 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 8 \dbus__sel$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 19 \dbus__we
+  wire width 1 output 18 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 \dbus__we$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 20 \dbus__dat_w
+  wire width 64 output 19 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 64 \dbus__dat_w$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 21 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 22 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 \m_load_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 23 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 \m_store_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 24 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 \m_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 25 \m_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
@@ -115752,6 +115734,8 @@ module \lsmem
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+  wire width 1 \x_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $6
     parameter \A_SIGNED 0
@@ -116351,6 +116335,10 @@ module \lsmem
     sync posedge \clk
       update \dbus__dat_w \dbus__dat_w$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 \m_load_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 \m_load_err_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
@@ -116366,6 +116354,8 @@ module \lsmem
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+  wire width 1 \m_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   cell $not $78
     parameter \A_SIGNED 0
@@ -116405,6 +116395,10 @@ module \lsmem
     sync posedge \clk
       update \m_load_err_o \m_load_err_o$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 \m_store_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 \m_store_err_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $81
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
@@ -116449,6 +116443,10 @@ module \lsmem
     sync posedge \clk
       update \m_store_err_o \m_store_err_o$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 \m_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 \m_badaddr_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $85
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
@@ -116497,6 +116495,8 @@ module \lsmem
     assign \x_busy_o \dbus__cyc
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+  wire width 1 \m_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
   wire width 1 $89
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
@@ -116523,6 +116523,8 @@ module \lsmem
     end
     sync init
   end
+  connect \x_stall_i 1'0
+  connect \m_stall_i 1'0
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0"
@@ -116553,54 +116555,24 @@ module \l0
   wire width 64 input 11 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 12 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 13 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 14 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 15 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 16 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 17 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 18 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 19 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 20 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 21 \x_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 22 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 23 \x_stall_i
+  wire width 1 output 13 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 24 \dbus__ack
+  wire width 1 input 14 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 25 \dbus__err
+  wire width 1 input 15 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 26 \dbus__stb
+  wire width 1 output 16 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 27 \dbus__dat_r
+  wire width 64 input 17 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 28 \dbus__adr
+  wire width 45 output 18 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 29 \dbus__sel
+  wire width 8 output 19 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 30 \dbus__we
+  wire width 1 output 20 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 31 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 32 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 33 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 34 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 35 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 36 \m_busy_o
+  wire width 64 output 21 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 \pimem_ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
@@ -116613,18 +116585,36 @@ module \l0
   wire width 48 \pimem_ldst_port0_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pimem_ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 \pimem_x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 \pimem_x_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 \pimem_ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 \pimem_m_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pimem_ldst_port0_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pimem_ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 \pimem_x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pimem_ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pimem_ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 \pimem_x_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 \pimem_ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 \pimem_x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 \pimem_x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 \pimem_m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 \pimem_x_valid_i
   cell \pimem \pimem
     connect \rst \rst
     connect \clk \clk
@@ -116634,21 +116624,21 @@ module \l0
     connect \ldst_port0_data_len \pimem_ldst_port0_data_len
     connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
     connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
-    connect \x_mask_i \x_mask_i
-    connect \x_addr_i \x_addr_i
+    connect \x_mask_i \pimem_x_mask_i
+    connect \x_addr_i \pimem_x_addr_i
     connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o
-    connect \m_ld_data_o \m_ld_data_o
+    connect \m_ld_data_o \pimem_m_ld_data_o
     connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
     connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
-    connect \x_busy_o \x_busy_o
+    connect \x_busy_o \pimem_x_busy_o
     connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
     connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
-    connect \x_st_data_i \x_st_data_i
+    connect \x_st_data_i \pimem_x_st_data_i
     connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
-    connect \x_ld_i \x_ld_i
-    connect \x_st_i \x_st_i
-    connect \m_valid_i \m_valid_i
-    connect \x_valid_i \x_valid_i
+    connect \x_ld_i \pimem_x_ld_i
+    connect \x_st_i \pimem_x_st_i
+    connect \m_valid_i \pimem_m_valid_i
+    connect \x_valid_i \pimem_x_valid_i
   end
   cell \l0$106 \l0
     connect \rst \rst
@@ -116680,17 +116670,16 @@ module \l0
   cell \lsmem \lsmem
     connect \rst \rst
     connect \clk \clk
-    connect \x_mask_i \x_mask_i
-    connect \x_addr_i \x_addr_i
-    connect \m_ld_data_o \m_ld_data_o
-    connect \x_busy_o \x_busy_o
-    connect \x_st_data_i \x_st_data_i
-    connect \x_ld_i \x_ld_i
-    connect \x_st_i \x_st_i
-    connect \m_valid_i \m_valid_i
-    connect \x_valid_i \x_valid_i
+    connect \x_mask_i \pimem_x_mask_i
+    connect \x_addr_i \pimem_x_addr_i
+    connect \m_ld_data_o \pimem_m_ld_data_o
+    connect \x_busy_o \pimem_x_busy_o
+    connect \x_st_data_i \pimem_x_st_data_i
+    connect \x_ld_i \pimem_x_ld_i
+    connect \x_st_i \pimem_x_st_i
+    connect \m_valid_i \pimem_m_valid_i
+    connect \x_valid_i \pimem_x_valid_i
     connect \dbus__cyc \dbus__cyc
-    connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
     connect \dbus__stb \dbus__stb
@@ -116699,11 +116688,6 @@ module \l0
     connect \dbus__sel \dbus__sel
     connect \dbus__we \dbus__we
     connect \dbus__dat_w \dbus__dat_w
-    connect \m_stall_i \m_stall_i
-    connect \m_load_err_o \m_load_err_o
-    connect \m_store_err_o \m_store_err_o
-    connect \m_badaddr_o \m_badaddr_o
-    connect \m_busy_o \m_busy_o
   end
   connect \pimem_ldst_port0_addr_exc_o 1'0
 end
@@ -146925,54 +146909,24 @@ module \core
   wire width 1 input 22 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 23 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 24 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 25 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 26 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 27 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 28 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 29 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 30 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 31 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 32 \x_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 33 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 34 \x_stall_i
+  wire width 1 output 24 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 35 \dbus__ack
+  wire width 1 input 25 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 36 \dbus__err
+  wire width 1 input 26 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 37 \dbus__stb
+  wire width 1 output 27 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 38 \dbus__dat_r
+  wire width 64 input 28 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 39 \dbus__adr
+  wire width 45 output 29 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 40 \dbus__sel
+  wire width 8 output 30 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 41 \dbus__we
+  wire width 1 output 31 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 42 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 43 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 44 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 45 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 46 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 47 \m_busy_o
+  wire width 64 output 32 \dbus__dat_w
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -149017,17 +148971,7 @@ module \core
     connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
     connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
-    connect \x_mask_i \x_mask_i
-    connect \x_addr_i \x_addr_i
-    connect \m_ld_data_o \m_ld_data_o
-    connect \x_busy_o \x_busy_o
-    connect \x_st_data_i \x_st_data_i
-    connect \x_ld_i \x_ld_i
-    connect \x_st_i \x_st_i
-    connect \m_valid_i \m_valid_i
-    connect \x_valid_i \x_valid_i
     connect \dbus__cyc \dbus__cyc
-    connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
     connect \dbus__stb \dbus__stb
@@ -149036,11 +148980,6 @@ module \core
     connect \dbus__sel \dbus__sel
     connect \dbus__we \dbus__we
     connect \dbus__dat_w \dbus__dat_w
-    connect \m_stall_i \m_stall_i
-    connect \m_load_err_o \m_load_err_o
-    connect \m_store_err_o \m_store_err_o
-    connect \m_badaddr_o \m_badaddr_o
-    connect \m_busy_o \m_busy_o
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 32 \int_src1__ren
@@ -157259,40 +157198,28 @@ module \imem
   wire width 1 output 7 \ibus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 \ibus__cyc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
-  wire width 1 input 8 \a_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 9 \ibus__ack
+  wire width 1 input 8 \ibus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 10 \ibus__err
+  wire width 1 input 9 \ibus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 11 \ibus__stb
+  wire width 1 output 10 \ibus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 \ibus__stb$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 output 12 \ibus__sel
+  wire width 8 output 11 \ibus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 8 \ibus__sel$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 13 \ibus__dat_r
+  wire width 64 input 12 \ibus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 14 \ibus__adr
+  wire width 45 output 13 \ibus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 45 \ibus__adr$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
-  wire width 1 input 15 \f_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 output 16 \f_fetch_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 \f_fetch_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 output 17 \f_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 \f_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
-  wire width 1 output 18 \a_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
+  wire width 1 \a_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $not $2
     parameter \A_SIGNED 0
@@ -157677,6 +157604,10 @@ module \imem
     sync posedge \clk
       update \ibus__adr \ibus__adr$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
+  wire width 1 \f_fetch_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
+  wire width 1 \f_fetch_err_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
   wire width 1 $45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
@@ -157692,6 +157623,8 @@ module \imem
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
   wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
+  wire width 1 \f_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
   cell $not $48
     parameter \A_SIGNED 0
@@ -157721,6 +157654,10 @@ module \imem
     sync posedge \clk
       update \f_fetch_err_o \f_fetch_err_o$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
+  wire width 45 \f_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
+  wire width 45 \f_badaddr_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
   wire width 1 $49
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
@@ -157764,6 +157701,8 @@ module \imem
     sync posedge \clk
       update \f_badaddr_o \f_badaddr_o$next
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+  wire width 1 \a_busy_o
   process $group_7
     assign \a_busy_o 1'0
     assign \a_busy_o \ibus__cyc
@@ -157794,6 +157733,8 @@ module \imem
     end
     sync init
   end
+  connect \a_stall_i 1'0
+  connect \f_stall_i 1'0
 end
 attribute \generator "nMigen"
 attribute \top 1
@@ -157810,113 +157751,63 @@ module \test_issuer
   attribute \src "simple/issuer.py:56"
   wire width 1 input 4 \memerr_o
   attribute \src "simple/issuer.py:51"
-  wire width 1 output 5 \core_start_i
+  wire width 1 input 5 \core_start_i
   attribute \src "simple/issuer.py:52"
-  wire width 1 output 6 \core_stop_i
+  wire width 1 input 6 \core_stop_i
   attribute \src "simple/issuer.py:53"
-  wire width 1 output 7 \core_bigendian_i
+  wire width 1 input 7 \core_bigendian_i
   attribute \src "simple/issuer.py:54"
   wire width 1 output 8 \busy_o
   attribute \src "simple/issuer.py:55"
   wire width 1 output 9 \halted_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
-  wire width 48 output 10 \a_pc_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
-  wire width 1 input 11 \a_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
-  wire width 1 output 12 \a_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
-  wire width 1 input 13 \f_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
-  wire width 1 output 14 \f_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
-  wire width 1 output 15 \a_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
-  wire width 1 output 16 \f_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
-  wire width 64 output 17 \f_instr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 output 18 \f_fetch_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 output 19 \f_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 20 \ibus__adr
+  wire width 45 output 10 \ibus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 21 \ibus__dat_w
+  wire width 64 input 11 \ibus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 22 \ibus__dat_r
+  wire width 64 input 12 \ibus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 output 23 \ibus__sel
+  wire width 8 output 13 \ibus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 24 \ibus__cyc
+  wire width 1 output 14 \ibus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 25 \ibus__stb
+  wire width 1 output 15 \ibus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 26 \ibus__ack
+  wire width 1 input 16 \ibus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 27 \ibus__we
+  wire width 1 input 17 \ibus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 3 input 28 \ibus__cti
+  wire width 3 input 18 \ibus__cti
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 2 input 29 \ibus__bte
+  wire width 2 input 19 \ibus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 30 \ibus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 31 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 32 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 33 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 34 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 35 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 36 \x_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 37 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 38 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 39 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 40 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 41 \m_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 42 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 43 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 44 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 45 \m_badaddr_o
+  wire width 1 input 20 \ibus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 46 \dbus__adr
+  wire width 45 output 21 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 47 \dbus__dat_w
+  wire width 64 output 22 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 48 \dbus__dat_r
+  wire width 64 input 23 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 49 \dbus__sel
+  wire width 8 output 24 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 50 \dbus__cyc
+  wire width 1 output 25 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 51 \dbus__stb
+  wire width 1 output 26 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 52 \dbus__ack
+  wire width 1 input 27 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 53 \dbus__we
+  wire width 1 output 28 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 3 input 54 \dbus__cti
+  wire width 3 input 29 \dbus__cti
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 2 input 55 \dbus__bte
+  wire width 2 input 30 \dbus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 56 \dbus__err
+  wire width 1 input 31 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 57 \clk
+  wire width 1 input 32 \clk
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 58 \rst
+  wire width 1 input 33 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
   wire width 1 \core_corebusy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
@@ -158059,17 +157950,7 @@ module \test_issuer
     connect \data_i \core_data_i
     connect \rst \rst
     connect \clk \clk
-    connect \x_mask_i \x_mask_i
-    connect \x_addr_i \x_addr_i
-    connect \m_ld_data_o \m_ld_data_o
-    connect \x_busy_o \x_busy_o
-    connect \x_st_data_i \x_st_data_i
-    connect \x_ld_i \x_ld_i
-    connect \x_st_i \x_st_i
-    connect \m_valid_i \m_valid_i
-    connect \x_valid_i \x_valid_i
     connect \dbus__cyc \dbus__cyc
-    connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
     connect \dbus__stb \dbus__stb
@@ -158078,32 +157959,32 @@ module \test_issuer
     connect \dbus__sel \dbus__sel
     connect \dbus__we \dbus__we
     connect \dbus__dat_w \dbus__dat_w
-    connect \m_stall_i \m_stall_i
-    connect \m_load_err_o \m_load_err_o
-    connect \m_store_err_o \m_store_err_o
-    connect \m_badaddr_o \m_badaddr_o
-    connect \m_busy_o \m_busy_o
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+  wire width 48 \imem_a_pc_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
+  wire width 1 \imem_a_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+  wire width 1 \imem_f_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+  wire width 1 \imem_f_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
+  wire width 64 \imem_f_instr_o
   cell \imem \imem
-    connect \a_pc_i \a_pc_i
-    connect \a_valid_i \a_valid_i
-    connect \f_valid_i \f_valid_i
-    connect \f_busy_o \f_busy_o
-    connect \f_instr_o \f_instr_o
+    connect \a_pc_i \imem_a_pc_i
+    connect \a_valid_i \imem_a_valid_i
+    connect \f_valid_i \imem_f_valid_i
+    connect \f_busy_o \imem_f_busy_o
+    connect \f_instr_o \imem_f_instr_o
     connect \rst \rst
     connect \clk \clk
     connect \ibus__cyc \ibus__cyc
-    connect \a_stall_i \a_stall_i
     connect \ibus__ack \ibus__ack
     connect \ibus__err \ibus__err
     connect \ibus__stb \ibus__stb
     connect \ibus__sel \ibus__sel
     connect \ibus__dat_r \ibus__dat_r
     connect \ibus__adr \ibus__adr
-    connect \f_stall_i \f_stall_i
-    connect \f_fetch_err_o \f_fetch_err_o
-    connect \f_badaddr_o \f_badaddr_o
-    connect \a_busy_o \a_busy_o
   end
   process $group_0
     assign \busy_o 1'0
@@ -158116,18 +157997,18 @@ module \test_issuer
     sync init
   end
   process $group_2
-    assign \core_start_i 1'0
-    assign \core_start_i \core_core_start_i
+    assign \core_core_start_i 1'0
+    assign \core_core_start_i \core_start_i
     sync init
   end
   process $group_3
-    assign \core_stop_i 1'0
-    assign \core_stop_i \core_core_stop_i
+    assign \core_core_stop_i 1'0
+    assign \core_core_stop_i \core_stop_i
     sync init
   end
   process $group_4
-    assign \core_bigendian_i 1'0
-    assign \core_bigendian_i \core_bigendian
+    assign \core_bigendian 1'0
+    assign \core_bigendian \core_bigendian_i
     sync init
   end
   process $group_5
@@ -158345,7 +158226,7 @@ module \test_issuer
     connect \Y $12
   end
   process $group_12
-    assign \a_pc_i 48'000000000000000000000000000000000000000000000000
+    assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
     switch { $12 }
       attribute \src "simple/issuer.py:114"
@@ -158359,7 +158240,7 @@ module \test_issuer
             switch { \go_insn_i }
               attribute \src "simple/issuer.py:126"
               case 1'1
-                assign \a_pc_i \pc [47:0]
+                assign \imem_a_pc_i \pc [47:0]
             end
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
@@ -158382,7 +158263,7 @@ module \test_issuer
     connect \Y $14
   end
   process $group_13
-    assign \a_valid_i 1'0
+    assign \imem_a_valid_i 1'0
     attribute \src "simple/issuer.py:114"
     switch { $14 }
       attribute \src "simple/issuer.py:114"
@@ -158396,16 +158277,16 @@ module \test_issuer
             switch { \go_insn_i }
               attribute \src "simple/issuer.py:126"
               case 1'1
-                assign \a_valid_i 1'1
+                assign \imem_a_valid_i 1'1
             end
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
-                assign \a_valid_i 1'1
+                assign \imem_a_valid_i 1'1
               attribute \src "simple/issuer.py:151"
               case
             end
@@ -158427,7 +158308,7 @@ module \test_issuer
     connect \Y $16
   end
   process $group_14
-    assign \f_valid_i 1'0
+    assign \imem_f_valid_i 1'0
     attribute \src "simple/issuer.py:114"
     switch { $16 }
       attribute \src "simple/issuer.py:114"
@@ -158441,16 +158322,16 @@ module \test_issuer
             switch { \go_insn_i }
               attribute \src "simple/issuer.py:126"
               case 1'1
-                assign \f_valid_i 1'1
+                assign \imem_f_valid_i 1'1
             end
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
-                assign \f_valid_i 1'1
+                assign \imem_f_valid_i 1'1
               attribute \src "simple/issuer.py:151"
               case
             end
@@ -158547,7 +158428,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158617,7 +158498,7 @@ module \test_issuer
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 32
-    connect \A \f_instr_o
+    connect \A \imem_f_instr_o
     connect \B $27
     connect \Y $26
   end
@@ -158636,7 +158517,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158688,7 +158569,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158740,7 +158621,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158783,7 +158664,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158830,7 +158711,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158877,7 +158758,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158918,7 +158799,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -158961,7 +158842,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -159008,7 +158889,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -159055,7 +158936,7 @@ module \test_issuer
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
             attribute \src "simple/issuer.py:147"
-            switch { \f_busy_o }
+            switch { \imem_f_busy_o }
               attribute \src "simple/issuer.py:147"
               case 1'1
               attribute \src "simple/issuer.py:151"
@@ -159215,7 +159096,4 @@ module \test_issuer
     end
     sync init
   end
-  connect \core_core_start_i 1'0
-  connect \core_core_stop_i 1'0
-  connect \core_bigendian 1'0
 end