arch-x86: Make JRCXZ instruction do 64-bit jump

Per the AMD64 Architecture Programming Manual:

The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode

and

In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.

This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.

Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index b5f77cd31e7ce2717da506efdd2e50585969ab89..04b3adce1fd1cb983debba68239b0487b5c56d59 100644 (file)
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -483,7 +483,7 @@
             0x0: LOOPNE(Jb);
             0x1: LOOPE(Jb);
             0x2: LOOP(Jb);
-            0x3: JRCX(Jb);
+            0x3: JRCXZ(Jb);
             0x4: IN(rAb,Ib);
             0x5: IN(rAv,Iv);
             0x6: OUT(Ib,rAb);

diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
index 390a08b3c36ab728af92e275ba1706a02790bd5c..d0fa31a5a6fa3fedf6071dc84e3875633882b2b4 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
@@ -210,8 +210,10 @@ def macroop JNO_I
     wrip t1, t2, flags=(nCOF,)
 };
 
-def macroop JRCX_I
+def macroop JRCXZ_I
 {
+    # Make the default data size of jumps 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
     .control_direct
 
     rdip t1