r600g: drop depth quirk on evergreen

none of the EG cards need the quirk.

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 21d3394ca6095160ddfd10d9571197a29a63e960..7337839a32ecaec6b38ff654b522ba5bfb992667 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1650,24 +1650,9 @@ void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
 {
        struct pipe_depth_stencil_alpha_state dsa;
        struct r600_pipe_state *rstate;
-       boolean quirk = false;
-
-       if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
-               rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
-               quirk = true;
 
        memset(&dsa, 0, sizeof(dsa));
 
-       if (quirk) {
-               dsa.depth.enabled = 1;
-               dsa.depth.func = PIPE_FUNC_LEQUAL;
-               dsa.stencil[0].enabled = 1;
-               dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
-               dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
-               dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
-               dsa.stencil[0].writemask = 0xff;
-       }
-
        rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
        r600_pipe_state_add_reg(rstate,
                                R_02880C_DB_SHADER_CONTROL,