r600g: add winsys support for CTL constants.
authorDave Airlie <airlied@redhat.com>
Thu, 30 Sep 2010 23:43:14 +0000 (09:43 +1000)
committerDave Airlie <airlied@redhat.com>
Fri, 1 Oct 2010 00:30:16 +0000 (10:30 +1000)
These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.

src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/evergreend.h
src/gallium/drivers/r600/r600_state.c
src/gallium/drivers/r600/r600d.h
src/gallium/winsys/r600/drm/evergreen_hw_context.c
src/gallium/winsys/r600/drm/r600_hw_context.c
src/gallium/winsys/r600/drm/r600d.h

index 5775b04cc7ab1fa54764f7c82ea76d418b72735e..21d3394ca6095160ddfd10d9571197a29a63e960 100644 (file)
@@ -1450,6 +1450,8 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
        r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
 
        if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
                float offset_units = rctx->rasterizer->offset_units;
index 54b26f6fb694ebadfe8ab9fd81c02581c478ad9d..ce2b667868b616df373f655e3abdd59d43006edd 100644 (file)
@@ -40,6 +40,9 @@
 #define EVERGREEN_SAMPLER_OFFSET                    0X0003C000
 #define EVERGREEN_SAMPLER_END                       0X0003CFF0
 
+#define EVERGREEN_CTL_CONST_OFFSET                  0x0003CFF0
+#define EVERGREEN_CTL_CONST_END                     0x0003E200
+
 #define EVENT_TYPE_ZPASS_DONE                  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 
 #define R_008970_VGT_NUM_INDICES                     0x008970
 #define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                    0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC                  0x03CFF4
+
 #endif
index 83eedd2040fad6de97c3e7bc6e7f1dd1d87f5348..c86bad7ff551a12bedafeebd2941d8563e4b5fb5 100644 (file)
@@ -126,6 +126,8 @@ static void r600_draw_common(struct r600_drawl *draw)
        r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
        /* build late state */
        if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
                float offset_units = rctx->rasterizer->offset_units;
index 169cda5295bc82d1eda2f16403d8dc76dc5accb9..02e3734fcc81b2b83c5acfabe53e481c98acc2b4 100644 (file)
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
 #define SQ_TEX_INST_GET_GRADIENTS_V 0x8
index a92c32e7df912f6d0811a6a411305ab94bfa215d..225027b8a3e9da55593e20657bb692782c1f7c77 100644 (file)
@@ -61,6 +61,11 @@ static const struct r600_reg evergreen_config_reg_list[] = {
        {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0},
 };
 
+static const struct r600_reg evergreen_ctl_const_list[] = {
+       {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+       {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg evergreen_context_reg_list[] = {
        {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0},
        {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0},
@@ -518,6 +523,11 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
                                   Elements(evergreen_context_reg_list));
        if (r)
                goto out_err;
+       r = r600_context_add_block(ctx, evergreen_ctl_const_list,
+                                  Elements(evergreen_ctl_const_list));
+       if (r)
+               goto out_err;
+
 
        /* PS SAMPLER */
        for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
index 53783e8f507878adb0936281f7464400861ff32f..88a86d2cf28b3aaa6f35b44f4f99fbb93ae9a6da 100644 (file)
@@ -134,6 +134,11 @@ static const struct r600_reg r600_config_reg_list[] = {
        {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0},
 };
 
+static const struct r600_reg r600_ctl_const_list[] = {
+       {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+       {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
 static const struct r600_reg r600_context_reg_list[] = {
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0},
@@ -591,6 +596,10 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
                                   Elements(r600_context_reg_list));
        if (r)
                goto out_err;
+       r = r600_context_add_block(ctx, r600_ctl_const_list,
+                                  Elements(r600_ctl_const_list));
+       if (r)
+               goto out_err;
 
        /* PS SAMPLER BORDER */
        for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
index 5c08c5a04d1234201792cee1f6e5ab9fa10461c3..ccc9ffaf8e39eea105d3b6f09d0da9a751899548 100644 (file)
 #define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
 #endif