op1 = randint(0, (1<<width)-1)
op2 = randint(0, (1<<width)-1)
- op2 = 0x4000
- op1 = 0x4300
+ op2 = 0x4100
+ op1 = 0x4000
#op2 = 0x3c00
vals.append((op1, op2,))
return vals
m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
- self.o.dividend[-len(am0):].eq(am0), # TODO: check
+ self.o.dividend[len(self.i.a.m):].eq(am0), # TODO: check
self.o.divisor_radicand.eq(bm0), # TODO: check
self.o.operation.eq(Const(0)) # TODO check: DIV
]
""" links module to inputs and outputs
"""
m.submodules.div1 = self
- #m.submodules.div1_out_overflow = self.o.of
-
m.d.comb += self.i.eq(i)
def elaborate(self, platform):
# also: round up to nearest radix
fmt.m_width = roundup(fmt.m_width + 4, log2_radix)
- cfg = DivPipeCoreConfig(fmt.m_width, 0*fmt.fraction_width, log2_radix)
+ cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
self.pspec.fpformat = fmt
self.pspec.log2_radix = log2_radix