ps.vdd("E", ('S', 0), 0, 0, 1)
ps.vss("E", ('S', 1), 0, 0, 1)
- ps.vdd("I", ('S', 2), 0, 5, 1)
- ps.vss("I", ('S', 3), 0, 5, 1)
+ ps.vdd("I", ('S', 2), 0, 0, 1)
+ ps.vss("I", ('S', 3), 0, 0, 1)
ps.sdram1("", ('S', 4), 0, 0, 21)
ps.mi2c("", ('S', 26), 0, 0, 2)
- ps.vss("I", ('S', 28), 0, 6, 1)
- ps.vdd("I", ('S', 29), 0, 6, 1)
- ps.vss("E", ('S', 30), 0, 13, 1)
- ps.vdd("E", ('S', 31), 0, 13, 1)
+ ps.vss("I", ('S', 28), 0, 1, 1)
+ ps.vdd("I", ('S', 29), 0, 1, 1)
+ ps.vss("E", ('S', 30), 0, 1, 1)
+ ps.vdd("E", ('S', 31), 0, 1, 1)
- ps.vdd("E", ('W', 0), 0, 1, 1)
- ps.vss("E", ('W', 1), 0, 1, 1)
- ps.vdd("I", ('W', 2), 0, 7, 1)
- ps.vss("I", ('W', 3), 0, 7, 1)
+ ps.vdd("E", ('W', 0), 0, 2, 1)
+ ps.vss("E", ('W', 1), 0, 2, 1)
+ ps.vdd("I", ('W', 2), 0, 2, 1)
+ ps.vss("I", ('W', 3), 0, 2, 1)
ps.sdram2("", ('W', 4), 0, 0, 12)
ps.sdram1("", ('W', 16), 0, 21, 9)
ps.uart("0", ('W', 22), 0)
ps.jtag("", ('W', 24), 0, 0, 4)
- ps.vss("I", ('W', 28), 0, 14, 1)
- ps.vdd("I", ('W', 29), 0, 14, 1)
- ps.vss("E", ('W', 30), 0, 8, 1)
- ps.vdd("E", ('W', 31), 0, 8, 1)
+ ps.vss("I", ('W', 28), 0, 3, 1)
+ ps.vdd("I", ('W', 29), 0, 3, 1)
+ ps.vss("E", ('W', 30), 0, 3, 1)
+ ps.vdd("E", ('W', 31), 0, 3, 1)
- ps.vss("I", ('E', 0), 0, 2, 1)
- ps.vdd("I", ('E', 1), 0, 2, 1)
- ps.vdd("I", ('E', 2), 0, 10, 1)
- ps.vss("I", ('E', 3), 0, 10, 1)
+ ps.vss("I", ('E', 0), 0, 4, 1)
+ ps.vdd("I", ('E', 1), 0, 4, 1)
+ ps.vdd("I", ('E', 2), 0, 4, 1)
+ ps.vss("I", ('E', 3), 0, 4, 1)
ps.mspi("0", ('E', 4), 0)
ps.gpio("", ('E', 9), 0, 0, 16)
ps.eint("", ('E', 25), 0, 0, 3)
- ps.vss("I", ('E', 28), 0, 9, 1)
- ps.vdd("I", ('E', 29), 0, 9, 1)
- ps.vss("I", ('E', 30), 0, 3, 1)
- ps.vdd("I", ('E', 31), 0, 3, 1)
+ ps.vss("I", ('E', 28), 0, 5, 1)
+ ps.vdd("I", ('E', 29), 0, 5, 1)
+ ps.vss("I", ('E', 30), 0, 5, 1)
+ ps.vdd("I", ('E', 31), 0, 5, 1)
- ps.vss("E", ('N', 0), 0, 2, 1)
- ps.vdd("E", ('N', 1), 0, 2, 1)
- ps.vdd("I", ('N', 2), 0, 12, 1)
- ps.vss("I", ('N', 3), 0, 12, 1)
+ ps.vss("E", ('N', 0), 0, 6, 1)
+ ps.vdd("E", ('N', 1), 0, 6, 1)
+ ps.vdd("I", ('N', 2), 0, 6, 1)
+ ps.vss("I", ('N', 3), 0, 6, 1)
#ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
#ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
#ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins
- ps.vss("I", ('N', 28), 0, 11, 1)
- ps.vdd("I", ('N', 29), 0, 11, 1)
- ps.vss("I", ('N', 30), 0, 4, 1)
- ps.vdd("I", ('N', 31), 0, 4, 1)
+ ps.vss("I", ('N', 28), 0, 7, 1)
+ ps.vdd("I", ('N', 29), 0, 7, 1)
+ ps.vss("I", ('N', 30), 0, 7, 1)
+ ps.vdd("I", ('N', 31), 0, 7, 1)
#ps.mquadspi("1", ('S', 0), 0)
name = None # ignore
elif name == 'sys_pllvcout':
name = 'sys_pll_vco_o'
- pad = ['p_' + name, name, name]
+ pad = ['p_' + name, name, name, "A"] # A for Analog
elif name == 'sys_plltestout':
name = 'sys_pll_testout_o'
pad = ['p_' + name, name, name]
print "found spec", found
assert found is not None
# whewwww. add the direction onto the pad spec list
- pad.append(found[-1])
+ dirn = found[-1]
+ if pad[-1] == 'A':
+ pad[-1] += dirn
+ else:
+ pad.append(dirn)
iopads.append(pad)
elif pad is not None:
iopads.append(pad)