Allow more test cases to be run with CXXSim

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 72d05a79173bb3b396e6ceb9e34e288b60a0f2d2..f65abface930bbe31a4001539f57f73d1fea899f 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -1,5 +1,9 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Delay
+
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 732e9f3a093dab7634e4ac22e36edea5ca227485..e1f82b77dc337467c1f9eeff306adc2ade4a7120 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -33,10 +33,11 @@ from nmutil.plru import PLRU
 from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory
 from nmigen.cli import rtlil
-if True:
-    from nmigen.back.pysim import Simulator, Delay, Settle
-else:
-    from nmigen.sim.cxxsim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator
+
 from nmutil.util import wrap
 
 

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 06031af0268862ac5f862d281a1945bf833e7013..fb01baf4f1d811c628c688fff0685f7122dae8fe 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -45,10 +45,10 @@ from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory
 from nmutil.util import wrap
 from nmigen.cli import main, rtlil
-if True:
-    from nmigen.back.pysim import Simulator, Delay, Settle
-else:
-    from nmigen.sim.cxxsim import Simulator, Delay, Settle
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
 
 
 SIM            = 0

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index a8c514f7d6e1816a132a804369ebd24596cfeee2..8e63bdec4a580971c4dd8a6272b17b687f6e1b0c 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -20,10 +20,10 @@ from nmutil.byterev import byte_reverse
 from nmutil.mask import Mask, masked
 from nmutil.util import Display
 
-if True:
-    from nmigen.back.pysim import Simulator, Delay, Settle
-else:
-    from nmigen.sim.cxxsim import Simulator, Delay, Settle
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
 from nmutil.util import wrap
 
 from soc.experiment.mem_types import (LoadStore1ToMMUType,