from ieee754.part_mux.part_mux import PMux
from ieee754.part_ass.passign import PAssign
from ieee754.part_cat.pcat import PCat
+from ieee754.part_repl.prepl import PRepl
from operator import or_, xor, and_, not_
from nmigen import (Signal, Const)
# TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
#def __Part__(self, offset, width, stride=1, *, src_loc_at=0):
- #def __Repl__(self, count, *, src_loc_at=0):
+
+ def __Repl__(self, count, *, src_loc_at=0):
+ return PRepl(self.m, self, count, self.partpoints)
def __Cat__(self, *args, src_loc_at=0):
args = [self] + list(args)
--- /dev/null
+# SPDX-License-Identifier: LGPL-2.1-or-later
+# See Notices.txt for copyright information
+
+"""
+Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+dynamically-partitionable "repl" class, directly equivalent
+to nmigen Repl
+
+See:
+
+* http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/repl
+* http://bugs.libre-riscv.org/show_bug.cgi?id=709
+
+"""
+
+
+
+modcount = 0 # global for now
+def PRepl(m, repl, qty, mask):
+ from ieee754.part_repl.repl import PartitionedRepl # recursion issue
+ global modcount
+ modcount += 1
+ pc = PartitionedRepl(repl, qty, mask)
+ setattr(m.submodules, "repl%d" % modcount, pc)
+ return pc.output
+