whitespace

diff --git a/experiments12/SPBlock_512W64B8W.v b/experiments12/SPBlock_512W64B8W.v
index 008d8776793307744f8661f37300248f07f8ad94..ddab96849db049dd31dfe260a2901affd5bfabf5 100644 (file)
--- a/experiments12/SPBlock_512W64B8W.v
+++ b/experiments12/SPBlock_512W64B8W.v
@@ -1,3 +1,7 @@
 (* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a, input [63:0] d, output [63:0] q, input [7:0] we, input clk);
+module SPBlock_512W64B8W(input [8:0] a,
+                        input [63:0] d,
+                        output [63:0] q,
+                        input [7:0] we,
+                        input clk);
 endmodule // SPBlock_512W64B8W

diff --git a/experiments12/memory.py b/experiments12/memory.py
index b540359728b89715afaa1a76571c7d5b66aceeb1..565d179ec20c196dcf9c2ed65b69f27bf7fb2dcc 100644 (file)
--- a/experiments12/memory.py
+++ b/experiments12/memory.py
@@ -18,7 +18,8 @@ class ADD(Elaboratable):
         a = Signal(9)
         q = Signal(64) # output
         d = Signal(64) # input
-        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=self.we, i_clk=ClockSignal())
+        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
+                                             i_we=self.we, i_clk=ClockSignal())
         m.submodules += sram
 
         # connect up some arbitrary signals